Texas Instruments Low Phase Noise Clock Evaluation Module — up to 1.5 Ghz User guide

Brand: Texas Instruments

Model: Low Phase Noise Clock Evaluation Module — up to 1.5 Ghz

Type: User guide

1 Features

2 General Description

3 Signal Path and Control

User's Guide

SCAU024 – September 2008

Low Phase Noise Clock Evaluation Module — up to 1.5

GHz

• Easy-to-use evaluation module to generate low

phase noise clocks up to 1.5 GHz

• Easy device programming via host-powered USB

port

• Rapid configuration through provided EVM Control

Software

• Can be powered from the USB port, or by an

external 3.3V power supply

• Single-ended or differential input; external crystal

can be used with on-chip oscillator

• Footprint for optional crystal filter on one output

Figure 1. CDCE62005EVM Evaluation Board

The CDCE62005 is a high performance, low phase noise frequency synthesizer and jitter cleaner. It

features an on-chip PLL with dual integrated LC Voltage Controlled Oscillators (VCOs) operating from

1.75–2.35 GHz. It provides support for three manually or automatically selected inputs, and provides up to

five differential, or ten single-ended, low-jitter outputs.

The CDCE62005 supports single-ended and differential input signals, as well as providing a crystal

oscillator circuit that operates in conjunction with an external AT-cut crystal.

The CDCE62005 is programmed through an SPI interface using the supplied EVM programming graphical

user interface (GUI).

The evaluation module (EVM) demonstrates the electrical performance of the device. This

fully-assembled, factory-tested evaluation board allows complete validation of all device functions. For

optimum performance, the board is equipped with 50 Ω SMA connectors and well-controlled 50 Ω

impedance microstrip transmission lines.

The CDCE62005 provides three selectable inputs – PRI REF, SEC REF, and AUX IN. The PRI REF and

SEC REF inputs can accept up to 1500 MHz in the fan-out mode. In the PLL mode, PRI REF and SEC

REF can accept an input at up to 500MHz from a differential signal source, or up to 250MHz from a single

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4 Software Selectable Options

5 Installing the EVM Control Software and USB Driver

Software Selectable Options

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ended CMOS signal source. The AUX IN allows the use of an external crystal in the frequency range of

3.25MHz to 42MHz. The CDCE62005EVM provides a PC-board footprint for mounting a 5mm × 3,2mm

SMD crystal. If the AUX IN is driven through the SMA connector, the on-board crystal must be removed,

and R65 must be populated with a 0 ohm resistor. The CDCE62005EVM also provides support for driving

the PRI REF signals from an on-board 5mm × 7mm crystal oscillator (U12).

The CDCE62005 provides up to five differential (LVDS or LVPECL) or ten single ended (LVCMOS) or any

combination of outputs up to 1.5 GHz (LVPECL). It operates as a jitter cleaner, or as a frequency

synthesizer, or both. An optional single ended output (AUX OUT) provides an LVCMOS copy of either the

third or fourth output. On the CDCE62005EVM the AUX OUT signal path has a footprint for an optional

crystal filter (U13).

The CDCE62005 can use either a completely-internal loop filter, or a partially-external loop filter. The

loop-filter selection will affect the phase noise and loop stability of the PLL. If the CDCE62005 is to be

used only as a frequency synthesizer, the completely internal loop filter option is recommended. If the

CDCE62005 is used as a jitter cleaner, the partially external loop filter option is recommended, because

this allows for lower loop bandwidths to be obtained using resistors and capacitors which are larger than

the ones available on-chip.

The CDCE62005 options are selected by programming the on-chip registers. The CDCE62005 datasheet

provides the detailed information needed to configure and use this device.

Each of the five outputs of the CDCE62005 may be configured as an LVPECL, LVDS, or LVCMOS type.

The CDCE62005 select/deselect the the 150 Ω load resistor required by the LVPECL output. The

corresponding load resistor must be selected in the software interface when an output is configured as

LVPECL.

The LVCMOS outputs can operate at frequencies up to 250MHz. The LVPECL outputs operate at up to

1.5GHz (fan-out mode). The LVDS outputs operate at up to 800MHz.

The provided EVM Control Software (EVMCS) communicates with the CDCE62005 through a USB

interface through the CDCE62005 SPI port. The USB controller is normally powered over the USB cable,

but can be optionally be powered by an external 5V DC adapter that is plugged into the additional power

connector on the EVM. When the USB/SPI programming interface is available for use, the on-board LED

D25 is illuminated.

In addition to writing commands to the CDCE62005 SRAM while the board is powered, configurations can

also be stored in the on-chip EEPROM. This allows the EVM to start up in the desired configuration upon

powerup.

The CDCE62005 has a mode which permanently locks the EEPROM. After this mode is selected, the

EEPROM contents within the CDCE62005 cannot be changed. This is useful when setting final

configurations.

The CDCE62005 EVMCS also allows device configurations to be saved into a configuration file (.INI),

which can be loaded by the EVMCS at a later time to restore the saved settings.

The CDCE62005 EVMCS requires a Java Runtime Environment (JRE) to be installed. The latest JRE is

available as a free download at http://java.com . Install the JRE first, before attempting to install the

CDCE62005 EVMCS. To start the installation of the EVM software, double-click on the file named

“ CDCE62005EVM-n_n_n-install.exe”, where n_n_n is the current software version number.

Note that the USB driver must be installed in the same installation folder as the EVMCS program file after

the setup completes and the USB cable is connected (first time only).

After the setup wizard completes start the EVMCS from the start menu (Start → Texas Instruments Inc →

CDCE62005 Software & Driver → CDCE62005).

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ProgramfileandUSB-controller

driverareinsamelocation

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Installing the EVM Control Software and USB Driver

Connect the USB cable to the EVM. If a box appears asking for an appropriate driver, Do not use the

automatic search option! Select a manual installation and when prompted for the driver location browse

to the CDCE62005EVM program file folder that was used during instillation. If Windows does not ask for a

driver, no action is needed.

After USB driver installation, the EVM software should connect properly and be ready for use. A green

light in the USB Status and SPI Bus Status boxes indicates a good USB connection, and a dark light

indicates a faulty USB connection or a faulty SPI bus.

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5.1 CDCE62005 Control User Interface

5.2 Using the EVM Control Software

Installing the EVM Control Software and USB Driver

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Figure 2. TI CDCE62005 EVMCS Display

The graphical layout of the EVMCS is based on the functional structure of the CDCE62005. Using the

EVMCS, the system designer can change the Input Frequency, Input Divider, Input type, Input selection,

PFD Charge Pump, Internal/External Loop Filter, Output MUX selection, Output Divider, and Output type.

Other configurations are selected by the software with user-selectable options as described in the steps

below. If the CDCE62005EVM is USB powered, the “Enable EVM Power” check box must be checked. If

the CDCE62005 is powered from an external source, the “Enable EVM Power” check box must be

unchecked.

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Installing the EVM Control Software and USB Driver

1. Primary/Secondary Reference

The primary or the secondary reference input buffer section on the EVMCS can be clicked for a popup

window that opens, as shown in Figure 3 , showing selections on the external input signal type

(differential or single ended), the external signal connection to the CDCE62005 primary/secondary

inputs (AC or DC termination), input-buffer internal termination (enabled or disabled), and the

input-buffer VBB voltage polarity (normal or inverted).

Figure 3. Input Buffer Properties

2. Reference Input Selection through Smart MUX

The Smart MUX section of the EVMCS can be clicked for a popup window that opens, as shown in

Figure 4 , showing

• Selections on the EECLKSEL option

– “0” suggests using the REF_SEL pin for input selection and disabling the auto-select feature

– “1” suggests using the auto-select feature and disabling the REF_SEL feature)

– the Smart MUX reshaping (reshaping either or both of the primary and secondary input signals,

introducing short delay to either or both of the primary and secondary input signals for fast

operation)

• Selection of the reference divider of the primary or the secondary input signal after the first of the

two Smart MUX-es

Figure 4. Smart MUX

3. PFD and Charge Pump Selection

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Installing the EVM Control Software and USB Driver

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The PFD and Charge Pump section of the EVMCS can be clicked for a popup window that opens, as

shown in Figure 5 , showing selections for the charge pump current and charge pump pulse width. For the

internal loop filter, lower charge pump currents work well and for the external loop filter, higher charge

pump currents work well.

Figure 5. Charge Pump

4. Loop Filter Selection

The Loop Filter section of the EVMCS can be clicked for a popup window that shows the internal

loop-filter configuration, where the values of the resistors and capacitors of the active loop filter can be

selected from the allowable dropdown list for each component.

Figure 6. Loop Filter, Internal Only

Alternately, the loop filter with additional external components can be enabled by clicking the “Use

External Loop Filter Components” button and by enabling the appropriate DIPswitches (SW9 and

SW10) on the bottom of the CDCE62005EVM as described in the “Configuring the Board” section of

this User’s Guide. The external loop filter components (C4, R4 and C5) are in green in the picture

displayed below. The component values entered into the text boxes are saved when a configuration

file is saved, and displayed when that configuration file is reloaded. However, the external component

values are not used by the EVMCS for calculations.

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Installing the EVM Control Software and USB Driver

Figure 7. Loop Filter, Additional External Components

5. Output MUX Selection

The Output MUX section of the EVMCS for each of the five outputs can be clicked to open a popup

window, shown in Figure 8 , showing each Output MUX clock source. These are selectable between

the primary input, secondary input, Smart MUX output or the PLL VCO core output.

Figure 8. Output MUX (each output channel)

6. Output Type Selection

The Output buffer section of the EVMCS for each of the five outputs can be clicked to open a popup

window that shows options for each output clock source. These are selectable between LVPECL, High

Swing LVPECL (in which cases the output 150 Ω termination is automatically enabled), Reduced

Range Link LVDS, General Purpose Link LVDS, LVCMOS (in which case each of the P and N act as

two separate LVCMOS outputs with the same frequency that can either be active, inverting, tri-state or

low) or each output can be disabled.

Figure 9. Output Buffer Config (each output)

7. PLL Dividers Selection

The input, feedback and prescaler dividers can be selected by clicking on tabs in the EVMCS which

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6 Configuring the Board

Configuring the Board

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opens a popup window displaying all the possible selections of those dividers. Care must be taken in

choosing these dividers, along with the VCO, charge pump and loop filter, such that the on-chip PLL of

the CDCE62005 can operate in a stable closed-loop manner. Refer to the CDCE62005 data sheet for

further information on appropriate configuration of the PLL for closed-loop operation. After the dividers

are set accordingly, the PLL LOCK indicator display on the EVMCS are a bright green color. Also, the

on-board LED D33 illuminates to indicate PLL lock. The output dividers for each output can also be

chosen from possible selections displayed in the popup window, opened by clicking the output-divider

tab in the EVMCS. Each output divider can also be disabled.

8. Write to CDCE62005 EEPROM

To write any particular setting to the EEPROM (locked or unlocked), the menu item at the top of the

EVMCS titled “Tool” must be clicked. This highlights the items “Write EEPROM Unlocked” and “Write

EEPROM Locked” as part of a drop-down menu. Choosing the appropriate one after setting the desired

PLL configurations writes to the EEPROM in its appropriate mode.

Figure 10. Tools – Write to EEPROM

Configuration for Programming and Testing (with USB cable attached) (Default Configuration)

The CDCE62005EVM is configured by default to operate with the USB cable attached and a 3.3V power

supply added to EXT VDD and GND. In this configuration the USB microcontroller is powered by the USB

port 5V supply, while the CDCE62005 is powered by the 3.3V external supply. This configuration is best

for programming the CDCE62005 while also taking measurements. This configuration removes the power

variation found in USB power supplies by isolating the CDCE62005 from the USB supply.

Configuration for Programming (using USB power)

The CDCE62005EVM can use power supplied through the USB cable as its sole power source. (Not

recommended for measurements) This capability is intended for saving configuration settings to the

CDCE62005 and later powering the device from its internal memory (useful during performance testing of

the device). In this configuration JP_3_3 must be moved from its default position to the new position

shown below. Also the “Enable EVM Power” box must be checked on the EVM display.

Configuration for On-board Reference Input Biasing

If the CDCE62005 on-chip biasing is not used for AC-coupled reference input signals for PRI_REF or

SEC_REF, the CDCE62005EVM can alternately be set up to provide on-board biasing for LVPECL or

LVDS inputs. These bias voltages of 1.2V for LVDS and 1.9V for LVPECL are derived from the on-board

voltage regulator (U3). The bias points are available for every leg of the differential signals at both

PRI_REF and SEC_REF and can be enabled by using the jumpers on the CDCE62005EVM, JP_3_4 and

JP_3_5 for PRI_REF and JP_3_6 and JP_3_7 for SEC_REF. Each of these jumpers can be configured as

shown below for either LVPECL or LVDS bias.

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Configuring the Board

Configuration for On-board External Loop Filter

If the CDCE62005 is configured as a jitter cleaner, it requires the use of the partially-external loop filter,

located on the bottom side of the CDCE62005EVM PC board. There are four external loop filter options

provided on the EVM. The external loop filter topology is as shown below.

The external loop filter can be chosen by selecting one from the four available options on the

CDCE62005EVM using the dip switches, SW9 and SW10, located at the bottom side of the EVM and

shown below.

Figure 11. External Loop Filter Selection Switches

Configuration for PLL Lock Detect

The CDCE62005 PLL lock detect can be chosen on the CDCE62005EVM as either an analog lock detect

or a digital lock detect using the jumper, JP_3_12, located at the back side of the CDCE62005EVM. This

jumper can be configured as shown in Figure 12 for either analog or digital lock detect.

Figure 12. Lock Detect Select Jumper

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7 CDCE62005EVM Board Schematic Diagram

PUR

+3V3

+5V

+3V3

+5V

+3V3

VCC_IN

VCCA

+3V3

VCC_PLL

+3V3

LVDS_BIAS

LVPECL_BIAS

VCC_VCO

VCC_OUT

+3V3

SDA

SCL

POR

PWR_EN

VCC_OUT_ON

VCCA_ON

PWR_EN

POR

VCC_OUT_ON

VCCA_ON

PS_RESET

SCL

SDA

Y0_150_TERM

Y1_150_TERM

Y2_150_TERM

Y3_150_TERM

Y4_150_TERM

PS_RESET

PLL_LOCK

SPI_MISO

SPI_CLK

SPI_MOSI

SPI_LE

AUX_SEL

REF_SEL

PD_

RESET_

MODE_SEL

LVPECL_BIAS_PG

LVDS_BIAS_PG

OSC_EN

MMBT4401

NPN

DeviceCommunication

External3.3VPower

(EXT Supply 5V)

22uF/20VKemetT495D226(1)020A(2)4095

PLLLOCK

CDMODE

ALLFlashing=ErrorseeGUI

S2,S3=0,0=AriesLABEVM

MANYVIASwithHeatSink

BIGTHERMALVIASforallPOWER&GND

1.2VRefVoltage 1.9VRefVoltage

0805FootPrint

LockAnalog

LockDigital

EXTVCC

GND

C35

22uF/20VLowESR

C35

22uF/20VLowESR

R79

249

R79

249

C37

10uF/6.3V

C37

10uF/6.3V

C42

0.1uF

C42

0.1uF

JP_3_12JP_3_12

EN#

IN1

OUT1

SENSE

OUT2

IN2

GND

RESET#

TPS77333DGK

1 2

R142

10k

R142

10k

C46

10uF/6.3V

C46

10uF/6.3V

R52

1.5k

R52

1.5k

C38

1uF

C38

1uF

1 2

R11

4.7k

R11

4.7k

C64

10uF/6.3V

C64

10uF/6.3V

R31

1.5k

R31

1.5k

EXT-VCC

1 2

R106

10k

R106

10k

R50

R87

4.7K

R87

4.7K

1 2

R51

1.5k

R51

1.5k

1 2

68.1

BLM15HD102SN1D

Vcc

SDA

Vss

SCL

24LC512

1 2

R109

10k

R109

10k

C74

10uF/6.3V

C74

10uF/6.3V

2N2222A

1 2

R115

49.9

R115

49.9

1 2

R117

86.6

R117

86.6

C32

33pF

C32

33pF

1 2

R166

10k

R166

10k

1 2

R49

1.5k

R49

1.5k

C48

10uF/6.3V

C48

10uF/6.3V

1 2

R167

10k

R167

10k

1 2

R58

10k

R58

10k

BLM15HD102SN1D

1 2

R143

10k

R143

10k

C31

22uF/20VLowESR

C31

22uF/20VLowESR

C59

0.1uF

C59

0.1uF

C29

33pF

C29

33pF

1 2

R138

4.7k

R138

4.7k

1 2

R129

4.7k

R129

4.7k

1 2

R110

10k

R110

10k

MBRS2040LT3

R733 R733

1 2

R144

10k

R144

10k

R515k R515k

2N2222A

R85

453

R85

453

GND

GND/HS

NC1

GND/HS

NC2

EN_

IN1

IN2

_RESET

OUT2

OUT1

GND/HS

NC3

GND/PWRPAD

TPS76701QPWP

R633 R633

1 2

R112

4.7k

R112

4.7k

R102301 R102301

R41.5k R41.5k

DM0

DP0

SDA

GND2

GND1

SCL

PUR

TEST1

TEST0

GND3

RST

GND4

VCC1

VCC2

P3.0/RxD/S0

P3.1/TxD/S1

P3.2

P3.4/T0

P0.0

P0.1

P0.2

P0.3

P0.4

P0.5

P0.6

P0.7

VCC3

SUSP

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

P2.0

P2.1

P2.2

P2.3

P2.4

P2.5

P2.6

P2.7

VREN

VDDOUT

P3.3/INT1#

P3.5

P3.6

P3.7

SELF/BUS

TEST2

TUSB3210

D25

LEDGREEN

D25

LEDGREEN

R86100k R86100k

R123301 R123301

1 3

JP_3_3JP_3_3

C43

1uF

C43

1uF

R21

15K

R21

15K

C70

10uF/6.3V

C70

10uF/6.3V

D33

LEDGREEN

D33

LEDGREEN

C40

0.1uF

C40

0.1uF

+5V

GND

TypeBUSB-Shield

+5V

GND

TypeBUSB-Shield

D26

LEDGREEN

D26

LEDGREEN

C73

10uF/6.3V

C73

10uF/6.3V

1 2

R59

10k

R59

10k

GND

R30

1.5k

R30

1.5k

R103301 R103301

C68

10uF/6.3V

C68

10uF/6.3V

12MHZ1

SE3409-ND

12MHZ1

SE3409-ND

C33

1uF

C33

1uF

D34

LEDGREEN

D34

LEDGREEN

BLM15HD102SN1D

C47

0.1uF

C47

0.1uF

1 2

R118

49.9

R118

49.9

J3J3

C81

10uF/6.3V

C81

10uF/6.3V

RESET1RESET1

C41

0.1uF

C41

0.1uF

1 2

R108

4.7k

R108

4.7k

MBRS2040LT3

R114301 R114301

R53

1.5k

R53

1.5k

CDCE62005EVM Board Schematic Diagram

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EXT_LFN

EXT_LFP

EXT_LFN

EXT_LFP

PLLLOOPFILTER

LowInducatnaceFilter(Layout)

LOOPBW~

FILTER1

FILTER2

FILTER3

FILTER4

JUSTforTEST

LOOPBW~650HzCP=3mA

LOOPBW~

LOOPBW~ (R3=5K,C3=20pF)

(R3=5K,C3=120pF)

SW9

TDA04H0SK1

SW9

TDA04H0SK1

R82

R74

5.1

R74

5.1

SW10

TDA04H0SK1

SW10

TDA04H0SK1

R88

5.1

R88

5.1

C106

10uF

C106

10uF

R76

5.1

R76

5.1

C116

100uF

C116

100uF

C105

1uF

C105

1uF

R75-NP

1.09K

R75-NP

1.09K

C109

4.7uFX5R-NP

C109

4.7uFX5R-NP

C114

47uF

C114

47uF

R81

C115

10uF

C115

10uF

C107

0.27uF-NP

C107

0.27uF-NP

C111

4.7uF

C111

4.7uF

R75

5.1

R75

5.1

C110

22uF

C110

22uF

C108

2.2uF

C108

2.2uF

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CDCE62005EVM Board Schematic Diagram

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VCC_OUT

YP0

YN0

YP1

YN1

YP2

YN2

YP3

YN3

YP4

YN4

Y0_150_TERM

Y1_150_TERM

Y2_150_TERM

Y3_150_TERM

Y4_150_TERM

YP0

YN0

YP1

YN1

YP2

YN2

YP3

YN3

YP4

YN4

OUTPUTCLOCKS

YP0

YN0

YP1

YN1

YP2

YN2

YP3

YN3

YP4

YN4

R218 150R218 150

J45

SMA-EDGE

J45

SMA-EDGE

R217

10k

R217

10k

J36

SMA-EDGE

J36

SMA-EDGE

R231 150R231 150

J39

SMA-EDGE

J39

SMA-EDGE

J43

SMA-EDGE

J43

SMA-EDGE

Q55

FDV303N

Q55

FDV303N

R226 150R226 150

1 2

R220

0-NP

R220

0-NP

Q58

FDV303N

Q58

FDV303N

Q54

FDV303N

Q54

FDV303N

J48

SMA-EDGE

J48

SMA-EDGE

Q62

FDV303N

Q62

FDV303N

1 2

R224

0-NP

R224

0-NP

Q60

FDV303N

Q60

FDV303N

1 2

R214

0-NP

R214

0-NP

J35

SMA-EDGE

J35

SMA-EDGE

R216 150R216 150

1 2

R234

0-NP

R234

0-NP

C120

0.1uF

C120

0.1uF

R223

150

R223

150

1 2

R229

0-NP

R229

0-NP

C119

0.1uF

C119

0.1uF

R213 150R213 150

Q56

FDV303N

Q56

FDV303N

R222

10k

R222

10k

C131

0.1uF

C131

0.1uF

Q57

FDV303N

Q57

FDV303N

C130

0.1uF

C130

0.1uF

1 2

R225

0-NP

R225

0-NP

J49

SMA-EDGE

J49

SMA-EDGE

R212

10k

R212

10k

C88

0.1uF

C88

0.1uF

1 2

R215

0-NP

R215

0-NP

C87

0.1uF

C87

0.1uF

C90

0.1uF

C90

0.1uF

Q45

FDV303N

Q45

FDV303N

R233 150R233 150

R232

10k

R232

10k

J34

SMA-EDGE

J34

SMA-EDGE

C86

0.1uF

C86

0.1uF

1 2

R219

0-NP

R219

0-NP

R228 150R228 150

R227

10k

R227

10k

Q61

FDV303N

Q61

FDV303N

1 2

R235

0-NP

R235

0-NP

J32

SMA-EDGE

J32

SMA-EDGE

Q59

FDV303N

Q59

FDV303N

R221 150R221 150

C89

0.1uF

C89

0.1uF

C84

0.1uF

C84

0.1uF

1 2

R230

0-NP

R230

0-NP

J41

SMA-EDGE

J41

SMA-EDGE

R21

1 150

R21

1 150

CDCE62005EVM Board Schematic Diagram

www.ti.com

Low Phase Noise Clock Evaluation Module — up to 1.5 GHz12 SCAU024 – September 2008

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VCC_IN

VCC_VCO

VCCA

VCC_OUT

VCC_VCO

VCC_PLL

VCC_IN

VCC_OUT

YP0

YN0

YP2

YN2

YP4

YN4

YP1

YN1

YP3

YN3

PRI_REFP

PRI_REFN

SEC_REFP

SEC_REFN

SPI_CLK

SPI_MOSI

SPI_MISO

SPI_LE

MODE_SEL

TESTOUTA

VBB

PLL_LOCK

RESET_

PD_

AUX_IN

EXT_LFP

EXT_LFN

REF_SEL

TESTOUTA

PAD

VCC_OUT

AUXOUT

61.44MHzFilter

C82

10uF/6.3V

C82

10uF/6.3V

C154

0.1uF

C154

0.1uF

C145

0.1uF

C145

0.1uF

BLM15HD102SN1D

C162

0.1uF

C162

0.1uF

C156

0.1uF

C156

0.1uF

TESTOUTA

VCC_AUXIN

VCC_AUXOUT

VCC2_PLL

VCC6

U0N

U0P

VCC5

U1N

U1P

VCC4

U2N

U2P

VCC3

SPI_MISO

MODE_SEL

POWER_DOWN

AUX_OUT

VCC0

U3N

U3P

VCC2

U4N

U4P

VCC1

REG_CAP2

GND_VCO

VCC_VCO

REF_SEL

SPI_CLK

SPI_LE

SPI_MOSI

REG_CAP1

RESET

VCC1_PLL

VCC2_PLL

SEC_REF+

SEC_REF-

VCC_IN

PRI_REF+

PRI_REF-

VCC_IN

VBB

EXT_LFP

AUX_IN

EXT_LFN

PLL_LOCK

VCC_VCO

THERMAL_PAD

CDCE62005

C155

0.1uF

C155

0.1uF

C150

0.1uF-NP

C150

0.1uF-NP

C157

0.1uF

C157

0.1uF

R133

GND4

OUT

GND3

GND2

GND1

GND5

GND

U13

XtalFltr61.44Mhz

U13

XtalFltr61.44Mhz

C148

0.1uF

C148

0.1uF

C151

0.1uF

C151

0.1uF

C152

0.1uF

C152

0.1uF

C161

0.1uF

C161

0.1uF

C160

0.1uF

C160

0.1uF

J46

SMA-EDGE

J46

SMA-EDGE

C158

0.1uF

C158

0.1uF

R141

C144

0.1uF

C144

0.1uF

1 2

R94

C159

0.1uF

C159

0.1uF

C141

0.1uF

C141

0.1uF

C149

0.1uF

C149

0.1uF

C142

0.1uF

C142

0.1uF

C75

2.2uF

C75

2.2uF

C163

0.1uF

C163

0.1uF

C83

10uF/6.3V

C83

10uF/6.3V

R134

C147

0.1uF

C147

0.1uF

R95

100

R95

100

C146

0.1uF

C146

0.1uF

www.ti.com

CDCE62005EVM Board Schematic Diagram

SCAU024 – September 2008 Low Phase Noise Clock Evaluation Module — up to 1.5 GHz 13

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VPECL_BIAS

VDS_BIAS

+3V3

PRI_REFN

PRI_REFP

SEC_REFN

SEC_REFP

AUX_IN

OSC_EN

PRI_REFN

PRI_REFP

INPUTCLOCKPRI INPUTCLOCKSEC

LAYOUTCritical

AUXIN

SEC_REFN

SEC_REFP

PRI_REFP

PRI_REFN

LVDS

BIAS

LVDS

LVPECL

BIAS BIAS BIAS

LVDS LVDS

LVPECL LVPECL

J104 SMA-EDGEJ104 SMA-EDGE

R136

49.9

R136

49.9

C71

1uF

C71

1uF

R137

49.9

R137

49.9

C85

5pf-NP

C85

5pf-NP

C65

1uF

C65

1uF

JP_3_7JP_3_7

C67

1uF

C67

1uF

C76

0.1uF

C76

0.1uF

C36

1uF

C36

1uF

C69

1uF

C69

1uF

JP_3_4JP_3_4

C50

1uF

C50

1uF

C57

1uF

C57

1uF

C80

0.1uF

C80

0.1uF

VCC

NC/OUTN

OUT/OUTP

GND

U12

PE7745DU-30.72M

U12

PE7745DU-30.72M

C77

0.1uF

C77

0.1uF

C58

1uF

C58

1uF

R130

49.9

R130

49.9

C78

0.1uF

C78

0.1uF

JP_3_6JP_3_6

BLM15HD102SN1D

R132

49.9

R132

49.9

R65

100k-NP

R65

100k-NP

C66

1uF

C66

1uF

J213

SMA-VERT

J213

SMA-VERT

C79

0.1uF

C79

0.1uF

R135

49.9-NP

R135

49.9-NP

J103 SMA-EDGEJ103 SMA-EDGE

R131

49.9

R131

49.9

JP_3_5JP_3_5

J203

SMA-EDGE

J203

SMA-EDGE

25.00MhzCrystal

Crystal25.00MHz

25.00MhzCrystal

Crystal25.00MHz

J204 SMA-EDGEJ204 SMA-EDGE

CDCE62005EVM Board Schematic Diagram

www.ti.com

Low Phase Noise Clock Evaluation Module — up to 1.5 GHz14 SCAU024 – September 2008

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www.ti.com

CDCE62005EVM Board Schematic Diagram

EVALUATION BOARD/KIT IMPORTANT NOTICE

Texas Instruments (TI) provides the enclosed product(s) under the following conditions:

This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION

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Should this evaluation board/kit not meet the specifications indicated in the User’s Guide, the board/kit may be returned within 30

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SCAU024 – September 2008 Low Phase Noise Clock Evaluation Module — up to 1.5 GHz 15

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CDCE62005EVM Board Schematic Diagram

www.ti.com

EVM WARNINGS AND RESTRICTIONS

It is important to operate this EVM within the input voltage range of 3 V to 3.6 V and the output voltage range of 0 V to 3.6 V.

Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are

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Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the

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During normal operation, some circuit components may have case temperatures greater than 120 ° C. The EVM is designed to

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these devices during operation, please be aware that these devices may be very warm to the touch.

16 Low Phase Noise Clock Evaluation Module — up to 1.5 GHz SCAU024 – September 2008

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Texas Instruments Low Phase Noise Clock Evaluation Module — up to 1.5 Ghz User guide

Texas Instruments Low Phase Noise Clock Evaluation Module — up to 1.5 Ghz User guide

Texas Instruments Low Phase Noise Clock Evaluation Module — up to 1.5 Ghz User guide

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