User's Guide
SCAU031 – June 2009
10.9-MHz to 1.175-GHz, Low Phase Noise Clock Evaluation
Board
Figure 1. CDCE421A Evaluation Board
Features:
• Easy-to-use evaluation board to generate low phase noise clocks between 10.9 MHz and 1.175 GHz
• Easy device programming via host-powered USB port
• Fast configuration through GUI software interface
• Total board power provided either through USB port or separate 3.3-V and ground connections
• LVCMOS input interface or crystal input
• Standard 6-pin XO package connection available
space
Contents
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1 General Description ......................................................................................................... 3
2 Signal Path and Control Circuitry .......................................................................................... 3
3 Block Description ............................................................................................................ 4
4 Software-Selectable Options ............................................................................................... 4
5 Installing the GUI Software and USB Driver ............................................................................. 5
6 Chronos GUI Software ...................................................................................................... 7
7 Configuring the Board ..................................................................................................... 10
8 Schematics and Layout .................................................................................................... 11
List of Figures
1 CDCE421A Evaluation Board .............................................................................................. 1
2 Enabled (Block A) and Disabled (Blocks B, C, D) Switch Positions .................................................. 3
3 Software Installation Screen 1 ............................................................................................. 5
4 Software Installation Screen 2 ............................................................................................. 6
5 TI Chronos GUI Window .................................................................................................... 7
6 Loop Filter Configuration Pop-Up Dialog ................................................................................. 8
7 CDCE421A Advanced Controls Pop-Up Dialog ......................................................................... 9
8 JP1 Settings ................................................................................................................. 11
9 CDCE421AEVM—Schematic ............................................................................................. 12
10 CDCE421AEVM—Schematic ............................................................................................. 13
11 CDCE421AEVM—Schematic ............................................................................................. 14
12 CDCE421AEVM—Schematic ............................................................................................. 15
13 CDCE421AEVM—Schematic ............................................................................................. 16
2 10.9-MHz to 1.175-GHz, Low Phase Noise Clock Evaluation Board SCAU031 – June 2009
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1 General Description
2 Signal Path and Control Circuitry
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General Description
The CDCE421A is a high-performance, low phase noise clock generator. It has two fully integrated,
low-noise, LC-based voltage-controlled oscillators (VCOs) that operate in the range of 1.75 GHz to 2.35
GHz.
The CDCE421A has an integrated crystal oscillator circuitry that operates in conjunction with an external
AT-cut crystal to produce a stable frequency reference for the PLL-based frequency synthesizer. A 3.3-V
LVCMOS level input can also be used instead of a crystal to provide a frequency reference to the PLL.
This evaluation module (EVM) is designed to demonstrate the electrical performance of the CDCE421A.
This fully assembled and factory-tested evaluation board allows complete validation of the CDCE421A
device functionalities. Throughout this document, the acronym EVM and the phrases evaluation module
and evaluation board are synonymous with the CDCE421AEVM. Figure 1 illustrates the CDCE421AEVM.
For optimum performance, the board is equipped with 50- Ω SMA connectors and well-controlled, 50- Ω
impedance microstrip transmission lines.
The CDCE421A can accept a 29-MHz to 44-MHz frequency input from either an LVCMOS source (up to
3.3 V) or a crystal in the same frequency range.
The CDCE421AEVM is divided into four blocks. The programming section and device power for each
block can be enabled or disabled through individual switches provided for each block. For example, in
order to enable power and programming for Block A, the switch must be in the position shown in Figure 2 .
The other blocks are disabled with the respective switches as the figure illustrates.
For more information about the CDCE421A, see the CDCE421A product data sheet available for
download from the TI web site (www.ti.com ).
Figure 2. Enabled (Block A) and Disabled (Blocks B, C, D) Switch Positions
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3 Block Description
3.1 Block A
3.2 Block B
3.3 Block C
3.4 Block D
4 Software-Selectable Options
Block Description
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This section summarizes the function of each block.
Block A includes a CDCE421A QFN device that accepts an LVCMOS reference input through the vertical
SMA input connector (Ref Input), which is already ac-coupled onboard the EVM.
This block includes a CDCE421A QFN device that uses an AT crystal. This block can be used as either a
crystal oscillator (XO) or a voltage-controlled crystal oscillator (VCXO). For use as an XO or VCXO, the
crystal should be mounted on either of the two crystal footprints on the board, and a vertical SMA input
connector must be installed on the provided footprint to be used as the control voltage input.
Block C can accommodate a 5 × 7 crystal oscillator. The oscillator package must also include a
fixed-frequency crystal with a specified load and range.
Block D includes a socket that fits the oscillator part used in block C.
The output frequency of the CDCE421A is always an integer multiple or integer divide of the input
frequency. The output frequency is determined through the selection of VCO1 or VCO2 and the
appropriate prescalar and output divider based on the values discussed in the CDCE421A product data
sheet .
The loop filter selection will affect the output frequency phase noise, and should be considered in
conjunction with the type of input used.
In LVDS mode, the device can achieve up to 400 MHz. In LVPECL mode, the device can achieve up to
1.175 GHz. The output signaling level and LVPECL termination are selectable through the software
interface.
The provided graphical user interface (GUI) software allows users to easily send commands to the
CDCE421A through the host-powered USB interface. The EVM includes a slave USB controller that
transmits the commands to the single-pin programming interface located on the CDCE421A. DC power for
the USB controller can either be derived from the 5-V power pin in the USB cable or by using an external
5-V ac adapter in the slot available on the EVM.
In addition to writing commands to the CDCE421A SRAM while the board is powered up, commands can
also be stored in either the nonvolatile USB microcontroller memory or the EEPROM included within the
CDCE421A. This option allows users to start the EVM in the desired state without requiring additional
programming at power-up.
Note: The CDCE421A does have a permanent EEPROM lock mode. After this mode, is selected
the EEPROM within the CDCE421A cannot be changed. This option is useful when setting
final configurations.
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5 Installing the GUI Software and USB Driver
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Installing the GUI Software and USB Driver
To start the software installation, run the CDCE421A Control GUI v 1.0.msi, software, available in the
CDCE421A product folder on TI.com. The screen shown in Figure 3 appears.
Figure 3. Software Installation Screen 1
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Installing the GUI Software and USB Driver
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Note the location of the installation folder because the USB driver must be installed to the same folder
after setup completes and the USB cable is connected, as indicated in Figure 4 .
Figure 4. Software Installation Screen 2
After the setup wizard completes, start the GUI interface from the Windows
®
Start menu (Start → Texas
Instruments → Chronos Eval ↑ TIChronosGUI.exe).
Connect the USB cable to the EVM. If Windows prompts you for an appropriate driver, do not use the
automatic search option. Instead, select the manual search, and when prompted for the driver location,
browse to the Chronos GUI file folder that was used during instillation. (No action is needed if Windows
does not prompt you for a different driver.)
Once the USB driver installation completes, the GUI software should load properly and be ready for use. A
green light in the USB communication box indicates a good USB connection; a red light indicates a faulty
USB connection. If you get a red light in the communication box, make sure that the correct USB driver is
properly installed and the USB cable is properly connected to the EVM.
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6 Chronos GUI Software
6.1 Using Software-Enabled Automatic PLL Selection
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Chronos GUI Software
Figure 5 illustrates the TI Chronos GUI software display.
Figure 5. TI Chronos GUI Window
The screenshot displayed in Figure 5 shows the on-chip PLL structure of the CDCE421A. In this display,
the user can change the Input Frequency, PFD Charge Pump, Loop Filter, and Output settings. The
balance of the settings are selected by the software with user-selectable options as described in the steps
below.
Step 1. IC Config and Input Calculator
Before programming the PLL, the EVM block that is being programmed must be selected in the IC
Block Config section of the GUI. For any block in the EVM that is being used, the first row of
calculations is useful when trying to investigate the input frequency to the CDCE421A required in order
to obtain a desired output frequency. The input is found by pressing the Calculate button.
Step 2. Store Crystal Frequency
If a crystal input is used in Block B of the EVM, the crystal frequency must be entered into the space
provided by clicking on the Device_EEPROM field found at the top of the software GUI. This action
opens a drop-down menu, where the user can click the menu item labeled Save Block B – XTAL Freq
to EEPROM. In this field, enter the crystal frequency in the format xx.xxx,specified in MHz.
Step 3. Output Calculator and Apply PLL Settings
The second row of calculations is used to get the PLL settings required to obtain a particular output
frequency provided by a given input frequency to CDCE421A. The input must be entered in the second
row as well as the place provided at the input of the PLL block diagram. After the Calculate button is
pressed, the adjacent drop-down menu is populated with several choices for the given input; the
desired output can then be chosen from this list. Choosing an output then sets the divider settings
within the PLL. Click on the Apply button (next to the drop-down menu) to write the PLL settings to the
SCAU031 – June 2009 10.9-MHz to 1.175-GHz, Low Phase Noise Clock Evaluation Board 7
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Chronos GUI Software
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device SRAM. If LVPECL output is desired, scroll through the Output type box until LVPECL is
displayed. This option automatically enables onboard LVPECL termination. If LVDS output is desired,
scroll through the Output type box until LVDS is displayed.
Step 4. PLL Bandwidth Select
If the user wants to adjust the PLL bandwidth, the Loop Filter block must be clicked. Clicking this block
brings up a pop-up screen, as shown in Figure 6 .
Figure 6. Loop Filter Configuration Pop-Up Dialog
For a clean reference input to CDCE421A (such as from an oscillator or crystal), the maximum
bandwidth and phase margin settings must be used, or 400 kHz and 80 degrees, respectively. The
PDF charge pump current must be set to its maximum (224 µ A). The PFD charge pump current can be
set by clicking on the PDF Charge Pump block. This selection then presents a drop-down menu with
the various charge pump current settings.
For a dirty reference input to CDCE421A, use the minimum bandwidth setting (50 kHz). Additionally, to
reduce the output jitter for a dirty input, the phase margin can be reduced to near-minimum (30
degrees), depending on the integration limits of the jitter that is deemed important for a given
application. To reduce the output jitter even further, reduce the charge pump current to near-minimum
(56 µ A), depending on the integration limits of the jitter.
Step 5. Write to CDCE421A EEPROM
To write any particular setting to the EEPROM (in locking or no-locking mode), the menu item at the
top of the GUI titled Device_EEPROM must be clicked. This action highlights the items Write settings
to EEPROM (No locking) and Write settings to EEPROM (Locking) as part of a drop-down menu.
Choose the appropriate option after setting the desired PLL configurations in order to write to the
EEPROM in the appropriate mode.
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6.2 Manual PLL Block Selection (Advanced Control)
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Chronos GUI Software
This GUI helps users to set the PLL without having to manually alter all the blocks individually within the
PLL. If a user is familiar with the general operation of PLLs, one may activate individual control of the PLL
blocks by clicking on the Advanced Control button. A new window appears, as shown in Figure 7 .
Figure 7. CDCE421A Advanced Controls Pop-Up Dialog
Table 1 summarizes the various menu options available in this dialog window.
Table 1. Advanced Control: Software Setting Options
Section Function
Selects between VCO1 and VCO2. Only one VCO can be
VCO Select used during operation. See the CDCE421A product data
sheet for VCO tuning ranges.
The prescalar selection will be determined in conjunction with
Prescalar the VCO and output divider selection. See the CDCE421A
product data sheet to determine the proper setting.
The output divider will be determined in conjunction with the
Output Divider. VCO and prescalar settings. See the CDCE421A product
data sheet to determine the proper setting.
Driver Select Selects between LVPECL or LVDS.
This option should be activated with using LVPECL output.
PECL config When selected, the USB controller will enable onboard
LVPECL termination.
Selects appropriate charge pump current. See screen
Charge Pump Current.
shotsxx for recommended configurations.
Bias 0 should be used at all times. Bias 1 is a reserved test
Loop Filter Bias Select
mode for TI.
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7 Configuring the Board
7.1 Configuration for Programming and Testing (with USB Cable Attached)—Default
Configuring the Board
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Table 1. Advanced Control: Software Setting Options (continued)
Section Function
Selects the loop filter C and R values. See screen shotsxx for
Loop Filter
recommended configurations.
When Enable VCO Calibration is selected, the CDCE421A
will use its internal calibration circuit to lock the PLL loop.
VCO Calibration
VCO Calibration Override should not be checked. (TI uses
manual calibration for test modes.)
This setting should be kept at 0000 ibias_100ua. Other
TI Test Use
settings are for TI internal use only.
Chronos IC Config
• Select Use U13 programming socket for rapid
programming of Chronos-enabled devices.
• Select Use U8 DIE/U9 QFN socket if the EVM is using a
direct-mounted die OR a QFN-mounted device. Note:
This setting is the typical configuration.
• Select Use U12XTAL EVAL if using the optional 6 pin
XO mounting pads (for Chronos-enabled oscillators).
Chronos Control
• Select Enable Power to run the entire board from the
host USB voltage. In this mode, the EVM will not need
an external 3.3-V power supply. If this option is not
selected, then a 3.3-V supply and ground connection
must be attached.
• Select Output Enable to provide a clock output. When
not selected, the output will go to a high-Z state.
• Push Write Chronos settings to RAM to download
settings to the CDCE421A onboard volatile SRAM.
These settings will be lost upon power down.
• Push Write Chronos settings to EEPROM NO LOCKING
when ready to store the configuration in the CDCE421A
nonvolatile EEPROM. The settings will be available after
power down. The settings can be changed at a later
time.
• Push Write Chronos settings to EEPROM LOCKING
only if the settings are permanent and final. After this
selection, the EEPROM will be locked and cannot be
altered at a later time.
A bright red light indicates that USB is not connected or not
USB communication communicating properly. A green light indicates a proper
USB connection.
The CDCE421AEVM can be powered from either the USB power supply or from an external source. The
CDCE421AEVM only requires a USB cable to be attached for programming purposes; however, for test
measurements, it is recommended to also use an external 3.3-V power supply. Test measurements can
also be taken with only the USB-supplied power. However, as a result of USB power variances, results
may degrade. It is also possible to program the CDCE421A and then disconnect the USB cable with minor
board configuration changes. To enable power and programming of any of the four blocks on the
CDCE421AEVM, the respective switch must be turned on, as explained earlier (see Section 2 ).
Configuration
The CDCE421AEVM is configured by default to operate with the USB cable attached and a 3.3-V power
supply added to AUX VDD and GND. In this configuration, the USB microcontroller is powered by the USB
port 5-V supply while the CDCE421A is powered by the 3.3-V external supply. This setup is optimal for
programming the CDCE421A while also taking measurements. This configuration removes the power
variation found in USB power supplies by isolating the CDCE421A from the USB supply.
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7.2 Configuration for Programming (with USB Cable Attached)
7.3 Configuration for Testing from a Saved Configuration (with USB Cable Removed after
8 Schematics and Layout
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Schematics and Layout
The CDCE421AEVM can also use power supplied through the USB cable as its sole power source.
However, as mentioned earlier, because of power-supply variances in the USB supply, this configuration
is not recommended for measurements. This setup is helpful for saving configuration settings to the
CDCE421A and then later powering the device from its internal memory (a useful option if there is no USB
port available on a PC in a lab or test chamber). In this configuration, JP1 must be moved from its default
position to the new position shown in Figure 8 . Additionally, the Enable (onboard) Power box must be
checked on the GUI software, followed by pushing the Apply software button.
Figure 8. JP1 Settings
Programming)
When operating the CDCE421A without the USB programming cable, the CDCE421AEVM must be
pre-programmed in one of the configurations discussed in this section and then reconfigured for external
power-supply usage.
Before making these board modifications, the CDCE421A settings must be saved with one of the above
USB cable attached configurations. Use the Write Chronos Settings to EEPROM NO LOCKING software
button to save the CDCE421A settings to the device-internal EEPROM. After the settings are saved to the
EEPROM, the USB cable can be removed. Once the cable has been disconnected, jumper JP1 should be
in the Using External 3.3-V Supply position (as shown in Figure 8 ). The EVM is now ready for use without
the USB cable connected. The CDCE421A will always start from its saved configuration state in this
mode.
If the CDCE421A must be isolated from the microcontroller, the switch that corresponds to the block in
use should be set to Off for CE_x, SDATA_x, and LVPECL_TERM_x (where x represents the block
name). The power line switch for that block, however, should be kept on. This sequence also allows for
the USB cable to be removed without affecting performance while the CDCE421A is powered up.
Figure 9 through Figure 11 show the printed circuit board (PCB) schematics for the CDCE421AEVM.
Note: Board layouts are not to scale. These figures are intended to show how the board is laid out;
they are not intended to be used for manufacturing CDCE421AEVM PCBs.
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PUR
S2
+3V3
+5V
+5V
+3V3
+5V
+3V3
+3V3
+3V3
+3V3
+3V3
+3V3
+3V3
VDD
+3V3
VDD
+3V3
+3V3
+3V3
+3V3
+3V3
+3V3
+3V3
+3V3
VDD
SDA
SCL
POR
PWR_EN
VDD_ON
PWR_EN
POR
SCL
SDA
EEPROM_WP
SDATA_A
CE_A
SDA
TA_B
SDA
TA_C
CE_B
CE_C
OPAMP_RD_A
SDATA_D
CE_D
OPAMP_RD_B
VDD_ON
OP
AMP_RD_C
OPAMP_RD_D
OP
AMP_EN_A
OPAMP_EN_B
OPAMP_EN_C
OPAMP_EN_D
LVPECL_TERM_D
LVPECL_TERM_C
LVPECL_TERM_B
LVPECL_TERM_A
VDD_A_ON
VDD_B_ON
VDD_C_ON
VDD_D_ON
MMBT4401
NPN
ControlPower
(EXTSupply5V)
CostumerEVMRevissionControlS2=1S3=0
LabEVMRevissionControlS2=0S3=0
Default=LVPECLTermination
Default=LVPECLTermination
Default=LVPECLTermination
Default=LVPECLTermination
EnableonlyoneOP-AMPatatime
CommunicationGood
DevicePower
+
C35
22uF/20VLowESR
+
C35
22uF/20VLowESR
1
2
R79
450
R79
450
C37
10uF/6.3V
C37
10uF/6.3V
C42
0.1uF
C42
0.1uF
3
1
2
Q4
2N2222A
Q4
2N2222A
EN#
3
IN1
5
OUT1
7
SENSE
1
OUT2
8
IN2
6
GND
4
RESET#
2
U2
TPS77333DGK
U2
TPS77333DGK
C38
1uF
C38
1uF
1 2
R82
10k
R82
10k
1
2
R31
1.5k
R31
1.5k
1
2
R80
100k-NP
R80
100k-NP
1
2
R50
1M
R50
1M
1 2
R51
1.5k
R51
1.5k
1
2
12MHZ1
ECS-120-S-5P-TR
12MHZ1
ECS-120-S-5P-TR
Vcc
8
SDA
5
A0
1
A1
2
A3
3
Vss
4
SCL
6
WP
7
U4
24LC512
U4
24LC512
1 2
R72
10k
R72
10k
D26
LEDGREEN
D26
LEDGREEN
12
C32
33pF
C32
33pF
1
2
R77
10k
R77
10k
1 2
R49
1.5k
R49
1.5k
1 2
R71
10k
R71
10k
1 3
2
JP1JP1
P4
VDD_EX
P4
VDD_EX
+
C31
22uF/20VLowESR
+
C31
22uF/20VLowESR
12
C29
33pF
C29
33pF
D8
MBRS2040LT3
D8
MBRS2040LT3
1
2
R733 R733
D25
LEDGREEN
D25
LEDGREEN
1
2
R515k R515k
3
1
2
Q1
2N2222A
Q1
2N2222A
1
2
R85
250
R85
250
GND
3
GND/HS1
1
GND/HS8
20
NC1
18
GND/HS7
19
GND/HS2
2
NC2
17
NC
4
EN_
5
IN1
6
IN2
7
_RESET
16
FB
15
OUT2
14
OUT1
13
GND/HS6
12
GND/HS5
11
GND/HS3
9
GND/HS4
10
NC3
8
GND/PWRPAD
21
U3
TPS76701QPWP
U3
TPS76701QPWP
1
2
R633 R633
1
2
R9310k R9310k
1
2
R4
1.5k
R4
1.5k
DM0
19
DP0
18
SDA
11
X1
61
X2
60
GND2
24
GND1
5
SCL
12
PUR
17
TEST1
15
TEST0
14
GND3
42
RST
13
GND4
59
VCC1
10
VCC2
39
P30/RxD/S0
58
P31/TxD/S1
57
P32
56
P34/T0
54
P00
43
P01
44
P02
45
P03
46
P04
47
P05
48
P06
49
P07
50
VCC3
62
SUSP
16
P1.0
31
P1.1
32
P1.2
33
P1.3
34
P1.4
35
P1.5
36
P1.6
40
P1.7
41
P2.0
22
P2.1
23
P2.2
25
P2.3
26
P2.4
27
P2.5
28
P2.6
29
P2.7
30
VREN
38
VDDOUT
37
S2
8
S3
9
P33/INT1
55
P35
53
P36
52
P37
51
SELF/BUS
21
TEST2
20
1
1
2
2
3
3
4
4
6
6
7
7
63
63
64
64
U1
TUSB3210
U1
TUSB3210
C43
1uF
C43
1uF
12
R21
15K
R21
15K
C40
0.1uF
C40
0.1uF
3
1
2
4
5
6
+5V
DM
DP
GND
J1
TypeBUSB-Shield
+5V
DM
DP
GND
J1
TypeBUSB-Shield
1 2
R59
10k
R59
10k
1 2
R65
301
R65
301
P5
GND
P5
GND
1
2
R30 1.5kR30 1.5k
1
2
C28
0.1uF
C28
0.1uF
C33
1uF
C33
1uF
D24
LEDGREEN
D24
LEDGREEN
1
2
3
J3
Adaptor5VDC
J3
Adaptor5VDC
12
43
5
RESET1
SW_PUSHBUTTON_5PIN
RESET1
SW_PUSHBUTTON_5PIN
12
R97
301
R97
301
C41
0.1uF
C41
0.1uF
D9
MBRS2040LT3
D9
MBRS2040LT3
1 2
R66
301
R66
301
1
2
R78
100k
R78
100k
1 2
R81
10k
R81
10k
Schematics and Layout
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Figure 9. CDCE421AEVM—Schematic
12 10.9-MHz to 1.175-GHz, Low Phase Noise Clock Evaluation Board SCAU031 – June 2009
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VDD
+3V3
+3V3
VDD
VDD
VDD
VDD
+3V3
OP
AMP_EN_A
OP
AMP_RD_A
CE_A
SDATA_A
LVPECL_TERM_A
VDD_A_ON
REF.AINPUT
12
R58
150
R58
150
1 2
R1
13
422
R1
13
422
1 2
R1
12
422
R1
12
422
12
R68
10K-NP
R68
10K-NP
2
3
4
5
1
J14
SMA-VERT
J14
SMA-VERT
2
3
4
5
1
J24
SMA-VERT
J24
SMA-VERT
12
R61
10K-NP
R61
10K-NP
1
2
R103
301
R103
301
C64
1uF
C64
1uF
12
R70
49.9
R70
49.9
Q18
FDV303N
Q18
FDV303N
12
R55
150
R55
150
D27
LEDGREEN
D27
LEDGREEN
1 2
R94
10k
R94
10k
1 2
R99
10k
R99
10k
C59
0.1uF
C59
0.1uF
3
1
2
Q5
2N2222A
Q5
2N2222A
C60
0.1uF
C60
0.1uF
2
3
4
5
1
J100
SMA-VERT
J100
SMA-VERT
C111
0.1uF
C111
0.1uF
+IN
3
NC1
1
SHDN
8
OUT
6
V+
7
-IN
2
V-
4
NC2
5
U17
TLV3501
U17
TLV3501
1
2
R109 10kR109 10k
1
2
8
7
3
4
6
5
SW1
TDA04H0SK1
SW1
TDA04H0SK1
C70
0.1uF
C70
0.1uF
Q10
FDV303N
Q10
FDV303N
CE
1
VCTL
14
VCC1
16
VCC2
17
TESTEN
19
SCANEN
15
SCANIN
24
OUTN
7
OUTP
10
GND1
8
GND2
9
TESTOUTA
20
SCANOUT
18
SDATA
3
XIN1
21
XIN2_XO
22
XIN2_VCXO
23
NC1
2
NC2
4
NC3
5
NC4
6
NC5
11
NC6
12
NC7
13
PWRPAD
25
U11
CDCE421_24QFN
U11
CDCE421_24QFN
1
2
R107
100k
R107
100k
1 2
R95
10k
R95
10k
C112
0.1uF
C112
0.1uF
C65 0.1uFC65 0.1uF
www.ti.com
Schematics and Layout
Figure 10. CDCE421AEVM—Schematic
SCAU031 – June 2009 10.9-MHz to 1.175-GHz, Low Phase Noise Clock Evaluation Board 13
Submit Documentation Feedback
+3V3
VDD
VDD
VDD
+3V3
VDD_B_ON
OUTPUT
+IN
3
NC1
1
SHDN
8
OUT
6
V+
7
-IN
2
V-
4
NC2
5
U16
TLV3501
U16
TLV3501
1
SMA-VERTSMA-VERT
1
2
R104
301
R104
301
1
SMA-VERTSMA-VERT
12
R54
150
R54
150
1 2
R92
10k
R92
10k
C62 0.1uFC62 0.1uF
D28
LEDGREEN
D28
LEDGREEN
1
2
R108
100k
R108
100k
1
2
8
7
3
4
6
5
SW2
TDA04H0SK1
SW2
TDA04H0SK1
1
2
3
4
5
6
XXMhz1
Crystal
XXMhz1
Crystal
C63
1uF
C63
1uF
1 2
R100
10k
R100
10k
Q9
FDV303N
Q9
FDV303N
1 2
R1
18
422
R1
18
422
Q16
FDV303N
Q16
FDV303N
1 2
R91
10k
R91
10k
3
1
2
Q6
2N2222A
Q6
2N2222A
12
R56
150
R56
150
C109
0.1uF
C109
0.1uF
C106
0.1uF
C106
0.1uF
C48
0.1uF
C48
0.1uF
1 2
R1
19
422
R1
19
422
CE
1
VCTL
14
VCC1
16
VCC2
17
TESTEN
19
SCANEN
15
SCANIN
24
OUTN
7
OUTP
10
GND1
8
GND2
9
TESTOUTA
20
SCANOUT
18
SDA
TA
3
XIN1
21
XIN2_XO
22
XIN2_VCXO
23
NC1
2
NC2
4
NC3
5
NC4
6
NC5
11
NC6
12
NC7
13
PWRPAD
25
U9
CDCE421_24QFN
U9
CDCE421_24QFN
1
2
R110 10kR110 10k
C49
0.1uF
C49
0.1uF
C110
0.1uF
C110
0.1uF
+3V3
VDD
OP
AMP_EN_B
OPAMP_RD_B
L
VPECL_TERM_B
CE_B
SDATA_B
2
3
4
5
1
J212
SMA-VERT
J212
SMA-VERT
2
3
4
5
J21J21
2
3
4
5
J11J11
Schematics and Layout
www.ti.com
Figure 11. CDCE421AEVM—Schematic
14 10.9-MHz to 1.175-GHz, Low Phase Noise Clock Evaluation Board SCAU031 – June 2009
Submit Documentation Feedback
+3V3
+3V3
VDD
VDD
VDD
VDD
+3V3
OPAMP_EN_C
OPAMP_RD_C
LVPECL_TERM_C
CE_C
SDATA_C
VDD_C_ON
OUTPUT
+IN
3
NC1
1
SHDN
8
OUT
6
V+
7
-IN
2
V-
4
NC2
5
U15
TLV3501
U15
TLV3501
1 2
R121
422
R121
422
CE
1
VCC
6
OUTN
5
OUTP
4
GND
3
SDA
TA
2
SP
ARE
7
U12
CDCE421_OSC
U12
CDCE421_OSC
C52
0.1uF
C52
0.1uF
C117
0.1uF
C117
0.1uF
1 2
R90
10k
R90
10k
C61 0.1uFC61 0.1uF
1
2
R111
100k
R111
100k
1 2
R101
10k
R101
10k
12
R57
150
R57
150
1
2
R105
301
R105
301
Q17
FDV303N
Q17
FDV303N
1
2
8
7
3
4
6
5
SW3
TDA04H0SK1
SW3
TDA04H0SK1
D29
LEDGREEN
D29
LEDGREEN
2
3
4
5
1
J22
SMA-VERT
J22
SMA-VERT
1
2
R84 0R84 0
2
3
4
5
1
J217
SMA-VERT
J217
SMA-VERT
C47
1uF
C47
1uF
Q11
FDV303N
Q11
FDV303N
2
3
4
5
1
J12
SMA-VERT
J12
SMA-VERT
1 2
R120
422
R120
422
3
1
2
Q7
2N2222A
Q7
2N2222A
1 2
R89
10k
R89
10k
1
2
R96
0-NP
R96
0-NP
1
2
R114 10kR114 10k
1
2
R86
100k-NP
R86
100k-NP
12
R63
150
R63
150
C108
0.1uF
C108
0.1uF
C116
0.1uF
C116
0.1uF
C51
0.1uF
C51
0.1uF
www.ti.com
Schematics and Layout
Figure 12. CDCE421AEVM—Schematic
SCAU031 – June 2009 10.9-MHz to 1.175-GHz, Low Phase Noise Clock Evaluation Board 15
Submit Documentation Feedback
+3V3
+3V3
VDD
VDD
VDD
VDD
+3V3
OPAMP_EN_D
OPAMP_RD_D
LVPECL_TERM_D
CE_D
SDATA_D
VDD_D_ON
1 2
R122
422
R122
422
1 2
R88
10k
R88
10k
1
2
R1
15100k
R1
15100k
Q15
FDV303N
Q15
FDV303N
12
R64
150
R64
150
2
3
4
5
1
J23
SMA-VERT
J23
SMA-VERT
1
2
R106
301
R106
301
1
2
R87
0
R87
0
1 2
R123
422
R123
422
C105
0.1uF
C105
0.1uF
12
R62
150
R62
150
Q13
FDV303N
Q13
FDV303N
D30
LEDGREEN
D30
LEDGREEN
CE
1
VCC
6
OUTN
5
OUTP
4
GND
3
SDA
TA
2
SPARE
7
U13
CDCE421_SOCKET
U13
CDCE421_SOCKET
1
2
R98 0R98 0
1 2
R83
10k
R83
10k
2
3
4
5
1
J13
SMA-VERT
J13
SMA-VERT
C107
0.1uF
C107
0.1uF
3
1
2
Q8
2N2222A
Q8
2N2222A
1
2
8
7
3
4
6
5
SW4
TDA04H0SK1
SW4
TDA04H0SK1
1 2
R102
10k
R102
10k
C55 0.1uFC55 0.1uF
C53
0.1uF
C53
0.1uF
1
2
R116 10kR116 10k
+IN
3
NC1
1
SHDN
8
OUT
6
V+
7
-IN
2
V
-
4
NC2
5
U14
TL
V3501
U14
TL
V3501
C54
0.1uF
C54
0.1uF
C46
1uF
C46
1uF
Schematics and Layout
www.ti.com
Figure 13. CDCE421AEVM—Schematic
16 10.9-MHz to 1.175-GHz, Low Phase Noise Clock Evaluation Board SCAU031 – June 2009
Submit Documentation Feedback
EVALUATION BOARD/KIT IMPORTANT NOTICE
Texas Instruments (TI) provides the enclosed product(s) under the following conditions:
This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES
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Should this evaluation board/kit not meet the specifications indicated in the User’s Guide, the board/kit may be returned within 30 days from
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Please read the User’s Guide and, specifically, the Warnings and Restrictions notice in the User’s Guide prior to handling the product. This
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No license is granted under any patent right or other intellectual property right of TI covering or relating to any machine, process, or
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This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES
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EVM WARNINGS AND RESTRICTIONS
It is important to operate this EVM within the input voltage range of –0.5 V to +4.0 V and the output voltage range of 0 to +3.6 V.
Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are questions
concerning the input range, please contact a TI field representative prior to connecting the input power.
Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the EVM.
Please consult the EVM User's Guide prior to connecting any load to the EVM output. If there is uncertainty as to the load specification,
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During normal operation, some circuit components may have case temperatures greater than +120 ° C. The EVM is designed to operate
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Copyright © 2009, Texas Instruments Incorporated
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