Humandata EDX-006 User manual

Type
User manual
HuMANDATA LTD.
Virtex-5 USB-FPGA Board
EDX-006
Users Manual
Ver. 1.0
Table of Contents
Revision History .............................................................................................. 1
Introduction .................................................................................................... 1
1. Specifications ..................................................................................................... 2
2. Overview ............................................................................................................ 3
2.1. Name of Parts .......................................................................................................3
2.2. Block Diagram ......................................................................................................4
2.3. Power Supply ........................................................................................................5
2.4. Clock ......................................................................................................................5
2.5. Development Environment .................................................................................5
3. USB Driver ........................................................................................................ 6
3.1. Install ....................................................................................................................6
3.2. Uninstall ...............................................................................................................8
4. FPGA Configuration ........................................................................................... 9
4.1. Download cable.....................................................................................................9
4.2. Setting Switch (SW1, SW3) .................................................................................9
4.3. USB Configuration ............................................................................................ 10
4.4. JTAG Configuration ........................................................................................... 11
5. Configuration Device ........................................................................................ 12
5.1. Generate programming file .............................................................................. 12
5.2. Device Programming......................................................................................... 13
5.3. Device Erasing................................................................................................... 13
5.4. Configure the FPGA.......................................................................................... 13
6. Initial setting of EEPROM for FT2232H .......................................................... 14
7. Additional Documentation and User Support ................................................... 15
Precautions
Do Not
1. This product uses ordinary off-the-shelf electronic components, and is therefore inappropriate for use in
applications that require special quality or reliability and are expected to protect human lives or prevent
accidents, such as safety mechanisms in fields including space, aeronautics, medicine, and nuclear
power.
2. Do not be used underwater or in high-humidity environments.
3. Do not be used in the presence of corrosive gases, combustible gases, or other flammable gases.
4. Do not turn on power when circuit board surface is in contact with other metal.
5. Do not apply voltage higher than rated voltage.
Attention
6. This manual may be revised in the future without notice owing to improvements.
7. All efforts have been made to produce the best manual possible, but if users notice an error or other
problem, we ask that they notify us.
8. Item 7 notwithstanding, HuMANDATA cannot be held liable for the consequences arising from use of
this product.
9. HuMANDATA cannot be held liable for consequences arising from using this product in a way different
from the uses described herein, or from uses not shown herein.
10. This manual, circuit diagrams, sample circuits, and other content may not be copied, reproduced, or
distributed without permission.
11. If the product emits smoke, catches fire, or becomes unusually hot, cut the power immediately.
12. Be careful of static electricity.
13. This product may be subject to the export restrictions of Japan, the United States, or other countries.
Purchasers are responsible for properly observing export restrictions.
14. HuMANDATA firmly refuses to export (including reexporting) products to countries or regions subject to
export restrictions.
Product Warranty and Scope of Support
1. HuMANDATA guarantees that its products can be assembled as shown in published circuit diagrams and other design documents.
There may be differences between actual components or their prescribed quantities and model numbers and those shown in circuit
diagrams.
2. Except for the guarantee in item 1, above, no guarantees whatsoever are made. When assembling the product as shown in a circuit
diagram is impossible, and the problem can be solved by revising the diagram, HuMANDATA will revise the diagram. When a
problem can be solved only by replacing components or modifying the product, HuMANDATA will take back the product to replace it
with a properly functioning product.
3. If the problem is minor, HuMANDATA will sometimes describe how to make the revision or modification, and ask the customer to
solve the problem.
4. HuMANDATA will determine how to honor the warranty, as through repair, replacement, return, or other action. The customer cannot
specify what action to take.
5. FPGAs and other components used in products sometimes have characteristic defects. Returns and replacements are not possible
even if such defects are discovered, whether before or after purchase.
6. HuMANDATA shall not be obligated to inform customers about defects in the main components used in products.
7. HuMANDATA shall not be obligated to provide support for products, or to provide support for the software of other companies
needed to use HuMANDATA products.
8. Published documentation shall be limited to that published by HuMANDATA at the time of product purchase, and HuMANDATA shall
not be obligated to provide any other documentation.
9. When repairs or replacements are provided under warranty in Japan, purchaser shall pay shipping charges for shipping to
HuMANDATA, and HuMANDATA shall pay shipping charges for shipping to purchaser.
10. When shipping from outside of Japan, purchaser shall pay all expenses including shipping charges and taxes.
11. Under whatever circumstances, HuMANDATA shall provide support for its products for a maximum of one year after shipping from
factory.
12. The Warranty is not applicable and support ends in the event of fire, storm and flood damage, earthquakes, lightning strikes, and
other natural disasters, as well as conflict or other occurrences.
13. Purchaser is assumed to have read and understood all the above when purchasing a HuMANDATA product.
Limitation of Liability
1. Purchasers assume all liability associated with the use of this product.
2. HuMANDATA assumes no liability whatsoever for any direct, indirect, special, incidental, or consequential damages arising from the
use of this product, even if HuMANDATA has been advised of the possibility of such damage, whether legal or in tort.
3. At the time this product is purchased, items 1 and 2 above shall be deemed to have been confirmed by purchaser.
Trademarks and Other Considerations
1. This manual uses various companies’ trademarks in places.
2. HuMANDATA is this company’s registered trademark.
HuMANDATA’s Philosophy
1. HuMANDATA endeavors to raise product quality. We continually make detailed improvements and adjustments that are not shown
in circuit diagrams.
2. HuMANDATA actively publishes, on the Web and in other ways, information considered useful to customers. Examples would be
how to use FPGAs and how to use development tools.
3. HuMANDATA makes efforts for the long-term provision of products and for continuing their long-term support.
4. Instead of concealing small product problems and documentation errors, HuMANDATA makes them public.
5. HuMANDATA abides by Japanese law and its spirit. We make no transactions with purchasers who commit illegal acts.
1
EDX-006 (Ver.1.0)
Revision History
Date
Version
Description
Jan. 15, 2010 1.0 Initial release.
Introduction
Thank you for buying our product EDX-006.
EDX-006 is an evaluation board of Xilinx FPGA. It equipped with power circuit, reset
circuit, crystal, memory and configuration device. So it can provide you with very
convenient and easy-to-use environment.
For USB interface, it has FTDI FT2232H. Channel B of FT2232H is oriented for
FPGA configuration and channel A is configured for a user communication interface
by using FTDIs virtual COM port and direct driver.
If you want to only configure the FPGA, you don’t need to prepare development
environment. But when you configure the configuration ROMand FPGA internal
SPI ROM, you need to prepare and use Xilinx oriented download cable.
2
EDX-006 (Ver.1.0)
1. Specifications
Model Name
EDX-006
FPGA
XC5VLX30-1FFG676C
USB Interface
FT2232H (FTDI)
Power Input
DC 5.0 [V] (Self Power)
Config. Device
M25P16-VMF6P (STMicro, 16Mbit) *
MRAM
MR2A16AYS35 (EverSpin, 4Mbit)
*
Dimensions
3.386" x 2.126" (86 x 54 [mm])
Weight
42 [g] typ.
User I/Os
100
User I/O Connectors
66-pin through-hole
dia. 0.9 [mm], 100[mil]/2.54 [mm] pitch
User Switch
1
User LEDs
2
On-Board Clock
50 [MHz] (External inputs are available) *
Status LEDs
2 : POWER (Red), DONE (Blue)
*
Power-On Reset
200 [ms] typ. (Configuration reset signal) *
JTAG Connector
SIL 7-pin socket, 2.54 [mm] pitch
PCB
6 Layer FR-4 t1.6 [mm] Immersion gold
Accessories
USB Cable (1.8m)
*
2 DIL 80-pin headers (Cuttable) *
RoHS Compliance
YES
* There may be cases when compatible parts are used.
3
EDX-006 (Ver.1.0)
2. Overview
2.1. Name of Parts
Component Side
Solder Side
User LED x2
Done LED (Blue)
Power LED (Red)
JTAG Connector
FPGA
(50MHz)
4
EDX-006 (Ver.1.0)
2.2. Block Diagram
5
EDX-006 (Ver.1.0)
2.3. Power Supply
This board operates from external 5.0V input. You can use external 5.0V input from
CNA and CNB. The external power supply should be sufficient and stabilized.
FT2232H operates in self-power mode. Please note that you can not use USB Bus
power. Internally required 3.3V, 2.5V and 1.0V are generated by on-boarded
regulators.
2.4. Clock
A crystal supplies 12MHz to the FT2232H, and a oscillator supplies 50MHz to the
FPGA. You can input external clock through CNA and CNB. For details please see
circuit schematics and pin assignment.
2.5. Development Environment
To develop and design FPGA internal circuit, you need to prepare circuit editor,
HDL editor or logic synthesis tool. These tools are provided by XILINX as ISE.
When you use them, you need an internet license. The version of ISE when
EDX-006 developed is Ver.10.1.03.
6
EDX-006 (Ver.1.0)
3. USB Driver
3.1. Install
To configure and communicate the FPGA, you should install device drivers on your
PC. The device driver was established by FTDI. Please download the driver file
named from our support page. For installation, please follow the steps below.
(*Windows XP is used in this example)
1. Select No, not this timethen click “Next”.
3. Browse the driver fi
les which you downloaded
from our support page.
2. Select Install from a list…” then click Next”.
4. EDX-006will be installed.
5. Keep coming, ED-CONFIGand USB Serial Portwill be recognized. Please
repeat same process for each devices.
*Non-WHQL compliant device driver will pop up a warning dialog window. When
you warned, please click YES or Continue Anyway”.
7
EDX-006 (Ver.1.0)
If installation is finished successfully, the three hardwares will be listed in device
manager.
8
EDX-006 (Ver.1.0)
3.2. Uninstall
To uninstall the device driver, please follow the steps below. Please make sure that
the EDX-006 is not attached to your PC before you operate device un-installation.
1. Open Control Panelthen click Add or Remove programs”.
2. Click Continue”.
3. Click Finish”.
9
EDX-006 (Ver.1.0)
4. FPGA Configuration
4.1. Download cable
You can configure the FPGA through USB by using application BitCfg”.
When you use configuration device, you need to use Xilinx download cable.
4.2. Setting Switch (SW1, SW3)
You can select configuration method by switching the SW3.
SW3
No.
1
2
USB
OFF OFF
JTAG
X ON
X : Dont Care
You can set configuration mode and others by SW1. For more information of each
pin, please refer to Virtex-5 user guide.
SW1
No.
1
2
3
4
5
6
7
8
LABEL
FS0
FS1
FS2
HSWAP_EN
X_M2
X_M1
X_M0
X_PROG
Default
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
Function
SPI Mode variation
I/O Pull-up
Configuration Mode
Target Select
Master SPI
Slave Serial
JTAG
X_M[ 2..0]
0 : 0 : 1
1 : 1 : 1
1 : 0 : 1
FS0, FS1, FS2
SPI variant select pins.
HSWAP_EN
Controls I/O pull-up during configuration.
ON : pull-up
OFF : 3-stated.
M2, M1, M0
Configuration mode setting. The mode showed above are compartment.
X_PROG
Select JTAG access target.
ON : Configuration device
OFF : FPGA
ON :Low (0)
OFF :High (1)
10
EDX-006 (Ver.1.0)
4.3. USB Configuration
We provide FPGA configuration application BitCfgfor free.
Please set the configuration mode to Slave Serial and set the target to FPGA.
To execute BitCfg, you need to use /D=argument by command line or BAT file.
/D= : Description name of FT2232 Ch.B ( EDX-006 HuMANDATA BFIXED)
example) BitCfg /D="EDX-006 HuMANDATA B"
Other two arguments are also available.
/C= : Configuration Rate (Please use 800000 as maximum value)
/F= : Path of a bit stream file.(Full-path)
example) BitCfg /D="EDX-006 HuMANDATA B" /C=500000 F=D:¥myLab¥EDX-006¥top.bit
By using /F=argument, configuration process is operated immediately.
Open .bitfile
Download the .bitfile to FPGA
When success indicated, DONE LED will be turned on
Configuration Time
Reset FPGA
11
EDX-006 (Ver.1.0)
4.4. JTAG Configuration
You can configure the FPGA and download data to configuration device by JTAG.
Pin assignment is as follows.
CN1
To configure the FPGA via JTAG, please refer to the following steps.
1. Double-click [Configuration Target Device] in [Processes] tab.
2. Select [Configure devices using Boundary-Scan (JTAG)].
3. Open the bit file you made.
4. Confirm [Verify] is not checked in [Device Programming Properties] dialog.
5. Select the FPGA icon, then open [Operations] menu and click [Program].
If configuration is completed successfully, the DONE LED will light up.
Pin No.
Signal Name
Direction
1
GND
I/O
2
TCK
IN
3
TDO
OUT
4
TMS
IN
5
VCC(3.3V)
OUT
6
TDI
IN
7
GND
I/O
12
EDX-006 (Ver.1.0)
5. Configuration Device
5.1. Generate programming file
To generate an MCS PROM file, please refer to following steps.
1. Double-click PROM File Formatterin iMPACT menu.
2. Select 3rd-Party SPI PROMas the Target.
3. Choose 16Mas SPI PROM Density.
4. Select the bit file you want to convert.
13
EDX-006 (Ver.1.0)
5. Double-click Generate File…” in iMPACT Processes tab.
6. PROM File Generation Succeededwill be showed.
5.2. Device Programming
Please set configuration mode to Master SPIwhen you program the device.
SW1
1 2 3 4 5 6 7 8
ON
X
X
X
X
OFF
X
X
X
X
X: Dont Care
5.3. Device Erasing
Select the device icon, and double-click Erasein configuration operations tab.
5.4. Configure the FPGA
Please set configuration mode switch as table below.
SW1
1 2 3 4 5 6 7 8
ON
X
X
X
X
OFF
X
X
X
X
X: Dont Care
14
EDX-006 (Ver.1.0)
6. Initial setting of EEPROM for FT2232H
The EEPROM for FT2232H is configured as below.
(FTDI MPROG Version 3.5)
15
EDX-006 (Ver.1.0)
7. Additional Documentation and User Support
The following documents and other supports are available at
http://www.hdl.co.jp/en/spc/EDX/edx-006/
Circuit Schematic
Pin List
Dimensional drawing
PCB drawing
Net List
Device drivers
Configuration application
and more.
Virtex-5 USB-FPGA Board
EDX-006
Users Manual
Ver. 1.0 ............................................Jan. 15, 2010
HuMANDATA LTD.
Address: 1-2-10-2F, Nakahozumi, Ibaraki
Osaka, Japan
ZIP 567-0034
Tel: 81-(0)72-620-2002 (Japanese)
Fax: 81-(0)72-620-2003 (Japanese/English)
URL: http://www.hdl.co.jp/en/ (Global)
http://www.hdl.co.jp/ (Japan)
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Humandata EDX-006 User manual

Type
User manual

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