ix
MPC Error Enable Register.......................................................................2-30
MPC Error Status Register........................................................................2-32
MPC Error Address Register.....................................................................2-34
MPC Error Attribute Register - MERAT..................................................2-34
PCI Interrupt Acknowledge Register ........................................................2-36
MPC Slave Address (0,1 and 2) Registers ................................................2-37
MPC Slave Address (3) Register...............................................................2-38
MPC Slave Offset/Attribute (0,1 and 2) Registers....................................2-39
MPC Slave Offset/Attribute (3) Registers.................................................2-40
General Purpose Registers.........................................................................2-41
PCI Registers....................................................................................................2-41
Vendor ID/ Device ID Registers ...............................................................2-43
PCI Command/ Status Registers................................................................2-43
Revision ID/ Class Code Registers............................................................2-45
I/O Base Register.......................................................................................2-46
Memory Base Register ..............................................................................2-46
PCI Slave Address (0,1,2 and 3) Registers................................................2-47
PCI Slave Attribute/ Offset (0,1,2 and 3) Registers..................................2-48
CONFIG_ADDRESS................................................................................2-49
PCI I/O CONFIG_ADDRESS Register ....................................................2-50
PCI I/O CONFIG_DATA Register ...........................................................2-51
Raven Interrupt Controller Implementation.............................................................2-52
Introduction.......................................................................................................2-52
The Raven Interrupt Controller (RavenMPIC) Features...........................2-52
Architecture...............................................................................................2-52
CSR’s Readability .....................................................................................2-53
Interrupt Source Priority............................................................................2-53
Processor’s Current Task Priority..............................................................2-53
Nesting of Interrupt Events........................................................................2-53
Spurious Vector Generation ......................................................................2-54
Interprocessor Interrupts (IPI) ...................................................................2-54
8259 Compatibility....................................................................................2-54
Raven-Detected Errors ..............................................................................2-55
Timers........................................................................................................2-55
Interrupt Delivery Modes ..........................................................................2-55
Block Diagram Description..............................................................................2-57
Program Visible Registers.........................................................................2-58
Interrupt Pending Register (IPR)...............................................................2-58
Interrupt Selector (IS)................................................................................2-58
Interrupt Request Register (IRR)...............................................................2-59
In-Service Register (ISR) ..........................................................................2-59
Interrupt Router .........................................................................................2-59