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CHAPTER 4 IP2 Chip
Introduction................................................................................................................4-1
Summary of Major Features...............................................................................4-1
Functional Description...............................................................................................4-2
General Description............................................................................................4-2
Cache Coherency................................................................................................4-2
Local Bus to IndustryPack DMA Controllers.....................................................4-3
Clocking Environments and Performance..........................................................4-5
Programmable Clock ..........................................................................................4-7
Error Reporting...................................................................................................4-7
Error Reporting as a Local Bus Slave .........................................................4-7
Error Reporting as a Local Bus Master .......................................................4-7
IndustryPack Error Reporting......................................................................4-8
Interrupts.............................................................................................................4-8
Overall Memory Map ................................................................................................4-9
Programming Model................................................................................................4-10
Chip ID Register...............................................................................................4-17
Chip Revision Register.....................................................................................4-17
Vector Base Register.........................................................................................4-18
IP_a, IP_b, IP_c, IP_d Memory Base Address Registers.................................4-19
IP_a or Double Size IP_ab Memory Base Address Registers ..................4-20
IP_b Memory Base Address Registers......................................................4-20
IP_c or Double Size IP_cd Memory Base Address Registers...................4-21
IP_d Memory Base Address Registers......................................................4-21
IP_a, IP_b, IP_c, IP_d Memory Size Registers................................................4-21
IP_a, IP_b, IP_c, and IP_d; IRQ0 and IRQ1 Interrupt Control Registers........4-23
IP_a, IP_b, IP_c, and IP_d; General Control Registers....................................4-24
IP Clock Register..............................................................................................4-28
DMA Arbitration Control Register...................................................................4-29
IP RESET Register ..........................................................................................4-30
Programming the DMA Controllers.................................................................4-31
DMA Enable Function...............................................................................4-33
DMA Control and Status Register Set Definition.....................................4-33
Programming the Programmable Clock....................................................4-43
Local Bus to IndustryPack Addressing....................................................................4-46
8-Bit Memory Space.........................................................................................4-46
16-Bit Memory Space.......................................................................................4-47
32-Bit Memory Space.......................................................................................4-48
IP_a I/O Space..................................................................................................4-49
IP_ab I/O Space................................................................................................4-50
IP_a ID Space ...................................................................................................4-51