NXP MPC560xP Reference guide

Type
Reference guide
Enhanced Signal Processing Extension and
Embedded Floating-Point Version 2
Auxiliary Processing Units
Programming Interface Manual
SPE2PIM
Rev. 1.0-2
08/2013
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Contents
Paragraph
Number Title
Page
Number
Contents
About This Book
Errata and Updates 1-i
Scope 1-i
Audience 1-i
Organization 1-ii
Suggested Reading 1-ii
General Information..................................................................................................... 1-ii
References.................................................................................................................... 1-ii
Related Documentation...............................................................................................1-iii
Chapter 1 Overview
1.1 High-Level Language Interface ....................................................................................... 1-1
1.2 Application Binary Interface (ABI) ................................................................................. 1-1
Chapter 2 High-Level Language Interface
2.1 Introduction...................................................................................................................... 2-1
2.2 High-Level Language Interface ....................................................................................... 2-1
2.2.1 Data Types ................................................................................................................... 2-1
2.2.2 Alignment .................................................................................................................... 2-2
2.2.2.1 Alignment of __ev64_*__ Types............................................................................. 2-2
2.2.2.2 Alignment of Aggregates and Unions Containing __ev64_*__ Types ................... 2-2
2.2.3 Extensions of C/C++ Operators for the New Types .................................................... 2-2
2.2.3.1 sizeof() ..................................................................................................................... 2-3
2.2.3.2 Assignment .............................................................................................................. 2-3
2.2.3.3 Address Operator ..................................................................................................... 2-3
2.2.3.4 Pointer Arithmetic ................................................................................................... 2-3
2.2.3.5 Pointer Dereferencing.............................................................................................. 2-3
2.2.3.6 Type Casting ............................................................................................................ 2-3
2.2.4 New Operators ............................................................................................................. 2-4
2.2.4.1 __ev64_*__ Initialization and Literals .................................................................... 2-4
2.2.4.2 New Operators Representing SPE2 Operations....................................................... 2-4
2.2.5 Programming Interface ................................................................................................ 2-5
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Contents
Paragraph
Number Title
Page
Number
Chapter 3
SPE2 Operations
3.1 Enhanced Signal Processing (SPE2) APU Extension Registers...................................... 3-1
3.1.1 Signal Processing and Embedded Floating-Point Status and Control Register
(SPEFSCR).............................................................................................................. 3-1
3.1.2 Accumulator (ACC)..................................................................................................... 3-3
3.2 Load and Store Instructions ............................................................................................. 3-4
3.2.1 Addressing Modes - Non-Update forms...................................................................... 3-4
3.2.1.1 Base + Scaled Immediate Addressing - non-update form ....................................... 3-4
3.2.1.2 Base + Index Addressing - non-update form........................................................... 3-5
3.2.2 Addressing Modes - Update forms .............................................................................. 3-5
3.2.3 Addressing Modes - Modify forms.............................................................................. 3-5
3.2.3.1 Linear addressing update mode ............................................................................... 3-6
3.2.3.2 Circular addressing modify mode............................................................................ 3-6
3.2.3.3 Bit-reversed addressing modify mode ..................................................................... 3-7
3.3 Notation ........................................................................................................................... 3-7
3.4 Instruction Fields ............................................................................................................. 3-8
3.5 Description of Instruction Operation ............................................................................. 3-10
3.6 Overview of Intrinsic Definition.................................................................................... 3-13
3.6.1 Saturation, Shift, and Bit Reverse Models................................................................. 3-14
3.6.1.1 Saturation...............................................................................................................3-14
3.6.1.2 Shift........................................................................................................................ 3-14
3.6.1.3 Bit Reverse............................................................................................................. 3-15
3.6.1.4 Load and Store Indexed with-Update Calculations ............................................... 3-15
3.7 Intrinsic Definitions ....................................................................................................... 3-15
3.7.1 SPE2 Intrinsic Definitions ......................................................................................... 3-16
3.7.2 EFP2 Intrinsic Definitions ....................................................................................... 3-958
3.8 Basic Instruction Mapping......................................................................................... 3-1021
Chapter 4
Additional Operations
4.1 Data Manipulation ........................................................................................................... 4-1
4.1.1 Creation Intrinsics........................................................................................................4-1
4.1.2 Convert Intrinsics.........................................................................................................4-2
4.1.3 Get Intrinsics................................................................................................................ 4-2
4.1.3.1 Get_Upper/Lower .................................................................................................... 4-2
4.1.3.2 Get Explicit Position................................................................................................ 4-3
4.1.4 Set Intrinsics ................................................................................................................ 4-4
4.1.4.1 Set_Upper/Lower..................................................................................................... 4-4
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Paragraph
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Number
4.1.4.2 Set Accumulator ...................................................................................................... 4-4
4.1.4.3 Set Explicit Position ................................................................................................ 4-6
4.2 Signal Processing Engine (SPE) APU Registers ............................................................. 4-6
4.2.1 Signal Processing and Embedded Floating-Point Status and Control Register
(SPEFSCR).............................................................................................................. 4-7
4.2.2 SPEFSCR Intrinsics..................................................................................................... 4-9
4.2.2.1 SPEFSCR Low-Level Accessors ............................................................................. 4-9
4.3 Application Binary Interface (ABI) Extensions ............................................................ 4-10
4.3.1 malloc(), realloc(), calloc(), and new......................................................................... 4-10
4.3.2 printf Example ........................................................................................................... 4-10
4.3.3 Additional Library Routines ...................................................................................... 4-11
Chapter 5
Programming Interface Examples
5.1 Data Type Initialization.................................................................................................... 5-1
5.1.1 __ev64_opaque__ Initialization................................................................................... 5-1
5.1.2 Array Initialization of SPE2 Data Types ..................................................................... 5-2
5.2 Fixed-Point Accessors ..................................................................................................... 5-3
5.2.1 __ev_create_sfix32_fs ................................................................................................. 5-3
5.2.2 __ev_create_ufix32_fs................................................................................................. 5-4
5.2.3 __ev_set_ufix32_fs ...................................................................................................... 5-4
5.2.4 __ev_set_sfix32_fs ...................................................................................................... 5-5
5.2.5 __ev_get_ufix32_fs...................................................................................................... 5-5
5.2.6 __ev_get_sfix32_fs ...................................................................................................... 5-5
5.3 Loads................................................................................................................................ 5-6
5.3.1 __ev_lddx..................................................................................................................... 5-6
5.3.2 __ev_ldd....................................................................................................................... 5-6
5.3.3 __ev_lhhesplatx ........................................................................................................... 5-6
5.3.4 __ev_lhhesplat .............................................................................................................5-7
Appendix A
Revision History
Glossary of Terms and Abbreviations
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Contents
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Page
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SPE2 Programming Interface Manual, Rev. 1.0-2
Freescale Semiconductor i
About This Book
The primary objective of this manual is to help programmers provide software that is compatible
across the family of processors that use the enhanced signal processing (SPE2) and embedded
floating-point version-2 (EFP2) auxiliary processing unit (APU) extension.
Errata and Updates
Freescale recommends using the most recent version of the documentation. The information in this
book is subject to change without notice, as described in the disclaimers on the title page of this
book. To locate any published errata or updates for this document, refer to the website at
http://www.freescale.com.
To obtain more information, contact your sales representative or visit our website at
http://www.freescale.com.
Scope
The scope of this manual does not include a description of individual SPE2 and EFP2
implementations. Each PowerPC™ processor is unique in its implementation of the SPE2 and
EFP2.
Audience
This manual supports system software and application programmers who want to use the SPE2
and EFP2 APUs to develop products. Users should understand the following concepts:
Operating systems
Microprocessor system design
Basic principles of RISC processing
SPE2 instruction set
EFP2 instruction set
SPE2 Programming Interface Manual, Rev. 1.0-2
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Organization
The following list summarizes and briefly describes the major sections of this manual:
Chapter 1, “Overview, provides a general understanding of what the programming model
defines in the SPE2 and EFP2 APUs.
Chapter 2, “High-Level Language Interface, is useful for software engineers who need to
understand how to access SPE2 and EFP2 functionality from high level languages such as
C and C++.
Chapter 3, “SPE2 Operations, describes all instructions in the SPE2 and EFP2 APUs.
Chapter 4, “Additional Operations, describes data manipulation, SPE floating-point status
and control register (SPEFSCR) operations, ABI extensions (malloc(), realloc(), calloc(),
and new), a printf example, and additional library routines.
Chapter 5, “Programming Interface Examples,gives examples of valid and invalid
initializations of the SPE2 data types.
Appendix A, “Revision History, lists the major differences between revisions of the
Enhanced Signal Processing Engine Auxiliary Processing Unit Programming Interface
Manual.
This manual also includes a glossary and an index.
Suggested Reading
The following sections note additional reading that can provide background for the information in
this manual as well as general information about the architecture.
General Information
The following documentation, which is published by Morgan-Kaufmann Publishers, 340 Pine
Street, Sixth Floor, San Francisco, CA, provides useful information about the PowerPC
architecture and general computer architecture:
The PowerPC Architecture: A Specification for a New Family of RISC Processors, Second
Edition, by International Business Machines, Inc.
System V Application Binary Interface, Edition 4.1.
References
The following documents may interest readers of this manual:
ISO/IEC 9899:1999 Programming Languages - C (ANSI C99 Specification).
DWARF Debugging Information Format, Version 3 (Revision 2.1, Draft 7), Oct. 29, 2001,
available from http://www.eagercon.com/dwarf/dwarf3std.htm.
SPE2 Programming Interface Manual, Rev. 1.0-2
Freescale Semiconductor iii
The PowerPC Architecture: A Specification for A New Family of RISC Processors.
International Business Machines (IBM). San Francisco: Morgan Kaufmann, 1994. (IBM
provides a website at Programming Environments Manual for 32-Bit Implementations of
the PowerPC Architecture (MPCFPE32B).
System V Application Binary Interface, Edition 4.1.
System V Application Binary Interface Draft, 24 April 2001.
System V Application Binary Interface, PowerPC Processor Supplement, Rev. A.
System V Interface Definition, Fourth Edition.
Related Documentation
Freescale documentation is available from the sources listed on the back cover of most manuals.
The following list includes documentation that is related to topics in this manual:
AltiVec™ Technology Programming Interface Manual
e500 Application Binary Interface (ABI)
Freescale’s Enhanced PowerPC Architecture Implementation Standards
Freescale Book E Implementation Standards: APU ID Reference
e500 ABI Save/Restore Routines
EREF: A Reference for Freescale Book E and the e500 CoreThis book provides a
higher-level view of the programming model as it is defined by Book E, the Freescale
Book E implementation standards, and the e500 microprocessor.
Reference manuals (formerly called user’s manuals)—These books provide details about
individual implementations.
Addenda/errata to reference or user’s manuals—Because some processors have follow-on
parts, an addendum is provided that describes the additional features and functionality
changes. These addenda are intended for use with the corresponding reference or user’s
manual.
Application notes—These short documents address specific design issues that are useful to
programmers and engineers working with Freescale processors.
Additional literature is published as new processors become available. For a current list of
documentation, refer to http://www.freescale.com.
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Chapter 1 Overview
This document defines a programming model to use with the enhanced signal processing (SPE2)
and embedded floating-point version 2 (EFP2) auxiliary processing units (APU). This document
describes three types of programming interfaces:
A high-level language interface that is intended for use within programming languages,
such as C or C++
An application binary interface (ABI) that defines low-level coding conventions
An assembly language interface
1.1 High-Level Language Interface
The high-level language interface enables programmers to use the SPE2 and EFP2 APUs from
programming languages such as C and C++, and describes fundamental data types for the SPE2
and EFP2 programming model. See Chapter 2, “High-Level Language Interface, for details about
this interface.
1.2 Application Binary Interface (ABI)
The SPE2 and EFP2 programming model extends the existing PowerPC ABIs. The extension is
independent of the endian mode. The ABI reviews the data types and register usage conventions
for vector register files and describes setup of the stack frame. Save and Restore functions for the
vector register are included in the ABI section to advocate uniformity of method among compilers
for saving and restoring vector registers.
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Overview
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Chapter 2 High-Level Language Interface
2.1 Introduction
This document defines a programming model to use with the enhanced signal processing (SPE2)
and the embedded floating-point version 2 (EFP2) auxiliary processing unit (APU) instruction
sets. The purpose of the programming model is to give users the ability to write code that utilizes
the APUs in a high-level language, such as C or C++.
Users should not be concerned with issues such as register allocation, scheduling, and conformity
to the underlying ABI, which are all associated with writing code at the assembly level.
2.2 High-Level Language Interface
The high-level language interface for SPE2 and EFP2 is intended to accomplish the following
goals:
Provide an efficient and expressive mechanism to access SPE2 and EFP2 functionality from
programming languages such as C and C++
Define a minimal set of language extensions that unambiguously describe the intent of the
programmer while minimizing the impact on existing PowerPC compilers and development
tools
Define a minimal set of library extensions that are needed to support SPE2 and EFP2
2.2.1 Data Types
Table 2-1 describes a set of fundamental data types that the SPE programming model introduces.
NOTE
The type _ev64_ stands for embedded vector of data width 64 bits.
Table 2-1. Data Types
New C/C++ Type Interpretation of Contents Values
__ev64_u8__ 8 unsigned 8-bit integers 0...255
__ev64_s8__ 8 signed 8-bit integers -128...127
__ev64_u16__ 4 unsigned 16-bit integers 0...65535
__ev64_s16__ 4 signed 16-bit integers -32768...32767
__ev64_u32__ 2 unsigned 32-bit integers 0...2
32
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High-Level Language Interface
The __ev64_opaque__ data type is an opaque data type that can represent any of the specified
__ev64_*__ data types. All of the __ev64_*__ data types are available to programmers.
2.2.2 Alignment
Refer to the e500 ABI for full alignment details.
2.2.2.1 Alignment of __ev64_*__ Types
A defined data item of any __ev64_*__ data type in memory is naturally aligned on an 8-byte
boundary. A pointer to any naturally aligned __ev64_*__ data type points to an 8-byte boundary.
However, some implementations of SPE2 allow relaxed alignment of vector data. The compiler is
responsible for providing options to align vector data on the natural boundary and to whatever
boundary an implementation may support. A program is incorrect if it attempts to dereference a
pointer to an __ev64_*__ type if the pointer does not contain an address aligned to a boundary
supported by the targeted implementation.
In the SPE2 architecture, a load/store to an unsupported address boundary causes an alignment
exception.
2.2.2.2 Alignment of Aggregates and Unions Containing __ev64_*__ Types
Aggregates (structures and arrays) and unions containing __ev64_*__ variables must be aligned
to supported boundaries and their internal organization must be padded, if necessary, so that each
internal __ev64_*__ variable is aligned to a supported boundary. A supported boundary of
__ev64_*__ data types always includes the natural boundary of 8-bytes and also includes whatever
boundary a targeted implemtation supports.
2.2.3 Extensions of C/C++ Operators for the New Types
Most C/C++ operators do not permit any of their arguments to be one of the __ev64_*__ types.
Let 'a' and 'b' be variables of any __ev64_*__ type, and 'p' be a pointer to any __ev64_*__ type.
The normal C/C++ operators are extended to include the operations in the following sections.
__ev64_s32__ 2 signed 32-bit integers -2
31
...2
31
- 1
__ev64_u64__ 1 unsigned 64-bit integer 0...2
64
- 1
__ev64_s64__ 1 signed 64-bit integer -2
63
...2
63
- 1
__ev64_fs__ 2 floats IEEE-754 single-precision values
__ev64_opaque__ any of the above
Table 2-1. Data Types (continued)
New C/C++ Type Interpretation of Contents Values
High-Level Language Interface
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2.2.3.1 sizeof()
The functions sizeof(a) and sizeof(*p) return 8.
2.2.3.2 Assignment
Assignment is allowed only if both the left- and right-hand sides of an expression are the same
__ev64_*__ type. For example, the expression a=b is valid and represents assignment of 'b' to 'a'.
The one exception to the rule occurs when 'a' or 'b' is of type __ev64_opaque__. Let 'o' be of type
__ev64_opaque__ and let 'a' be of any __ev64_*__ type.
The assignments a=o and o=a are allowed and have implicit casts. Otherwise, the expression is
invalid, and the compiler must signal an error.
2.2.3.3 Address Operator
The operation &a is valid if 'a' is an __ev64_*__ type. The result of the operation is a pointer to 'a'.
2.2.3.4 Pointer Arithmetic
The usual pointer arithmetic can be performed on p. In particular, p+1 is a pointer to the next
__ev64_*__ element after p.
2.2.3.5 Pointer Dereferencing
If 'p' is a pointer to an __ev64_*__ type, *p implies either a 64-bit SPE load from the address,
equivalent to the intrinsic __ev_ldd(p,0), or a 64-bit SPE store to that address, equivalent to the
intrinsic __ev_stdd(p,0). Dereferencing a pointer to a non-__ev64_*__ type produces the standard
behavior of either a load or a copy of the corresponding type.
Section 2.2.2.1, “Alignment of __ev64_*__ Types,describes unaligned accesses.
2.2.3.6 Type Casting
Pointers to __ev64_*__ and existing types may be cast back and forth to each other. Casting a
pointer to an __ev64_*__ type represents an (unchecked) assertion that the address is 8-byte
aligned.
Casting from a integral type to a pointer to an __ev64_*__ type is allowed.
For example:
__ev64_u16__ *a = (__ev64_u16__ *) 0x48;
Casting between __ev64_*__ types and existing types is not allowed.
Casting between __ev64_*__ types and pointers to existing types is not allowed.
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High-Level Language Interface
The behaviors expected from such casting are provided instead of using intrinsics.
The intrinsics provide the ability to extract existing data types out of __ev64_*__ variables as well
as the ability to insert into and/or create __ev64_*__ variables from existing data types. Normal C
casts provide casts from one __ev64_*__ type to another.
An implicit cast is performed when going to __ev64_opaque__ from any other __ev64_*__ type.
An implicit cast occurs when going from __ev64_opaque__ to any other __ev64_*__ type. The
implicit casts that occur when going between __ev64_opaque__ and any other __ev64_*__ type
also apply to pointers of type __ev64_opaque__. When casting between any two __ev64_*__
types not including __ev64_opaque__, an explicit cast is required. When casting between pointers
to any two __ev64_*__ types not including __ev64_opaque__, an explicit cast is required. No cast
or promotion performs a conversion; the bit pattern of the result is the same as the bit pattern of
the argument that is cast.
2.2.4 New Operators
New operators are introduced to construct __ev64_*__ values and allow full access to the
functionality that the SPE2 architecture provides.
2.2.4.1 __ev64_*__ Initialization and Literals
The __ev64_opaque__ type is the only __ev64_*__ type that cannot be initialized. The remaining
__ev64_*__ types can be initialized using the C99 array initialization syntax. Each type is treated
as an array of the specified data contents of the appropriate size. The following code exemplifies
the initialization of these types:
__ev64_u8__ a = { 0, 1, 2, 3, 4, 5, 6, 7 };
__ev64_s8__ b = { -1, -2, -3, -4, -5, -6, 0, 7 };
__ev64_u16__ c = { 0, 1, 2, 3 };
__ev64_s16__ d = { -1, -2, -3, 4 };
__ev64_u32__ e = { 3, 4 };
__ev64_s32__ f = { -2, 4 };
__ev64_u64__ g = { 17 } ;
__ev64_s64__ h = { 23 } ;
__ev64_fs__ i = { 2.4, -3.2 };
e = __ev_addw(a, (__ev64_s16__){2,1,5,2});
2.2.4.2 New Operators Representing SPE2 Operations
New operators are introduced to allow full access to the functionality that the SPE2 architecture
provides. Language structures that parse like function calls represent these operators in the
programming language.
The names associated with these operations are all prefixed with "__ev_". The appearance of one
of these forms can indicate one of the following:
A specific SPE2 operation, like __ev_addw(__ev64_opaque__ a, __ev64_opaque__ b)
High-Level Language Interface
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A predicate computed from a SPE2 operation, like __ev_all_eq(__ev64_opaque__ a,
__ev64_opaque__ b)
Creation, insertion, extraction of __ev64_opaque__ values
Each operator representing an SPE2 operation takes a list of arguments representing the input
operands (in the order in which they are shown in the architecture specification) and returns a
result that could be void. The programming model restricts the operand types that are permitted
for each SPE2 operation. Predicate intrinsics handle comparison operations in the SPE2
programming model.
Each compare operation has the following predicate intrinsics associated with it:
•_any_
_all_
_upper_
•_lower_
_select_
Each predicate returns an integer (0/1) with the result of the compare. The compiler allocates a CR
field for use in the comparison and to optimize conditional statements.
2.2.5 Programming Interface
This document does not prohibit or require an implementation to provide any set of include files
to provide access to the intrinsics. If an implementation requires that an include file be used before
the use of the intrinsics described in this document, that file should be <spe.h>.
This document does require that prototypes for the additional library routines described are
accessible by means of the include file <spe.h>. If an implementation should provide a __SPE__,
define it with a nonzero value. That definition should not occur in the <spe.h> header file.
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Chapter 3
SPE2 Operations
This chapter describes the instructions of the enhanced signal processing (SPE2) and embedded
floating-point version 2 (EFP2) auxiliary processing units (APU).
3.1 Enhanced Signal Processing (SPE2) APU Extension
Registers
The SPE2 includes the following two registers:
The signal processing and embedded floating-point status and control register (SPEFSCR),
which is described in
Section 3.1.1, “Signal Processing and Embedded Floating-Point
Status and Control Register (SPEFSCR).”
A 64-bit accumulator, which is described in Section 3.1.2, “Accumulator (ACC).”
3.1.1 Signal Processing and Embedded Floating-Point Status and
Control Register (SPEFSCR)
The SPEFSCR, which is shown in Figure 3-1, is used for status and control of SPE2 instructions.
Table 3-1 describes SPEFSCR bits.
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Field SOVH OVH FGH FXH FINVH FDBZH FUNFH FOVFH FINXS FINVS FDBZS FUNFS FOVFS MODE
Reset 0000_0000_0000_0000
R/W R/W
48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
Field SOV OV FG FX FINV FDBZ FUNF FOVF FINXE FINVE FDBZE FUNFE FOVFE FRMC
Reset 0000_0000_0000_0000
R/W R/W
SPR SPR 512
Figure 3-1. Signal Processing and Embedded Floating-Point Status and Control
Register (SPEFSCR)
High-Word Error Bits
Status Bits
Enable Bits
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SPE2 Operations
Table 3-1. SPEFSCR Field Descriptions
Bits Name Function
32 SOVH Summary integer overflow high, which is set whenever an instruction other than mtspr sets OVH. SOVH
remains set until a mtspr[SPEFSCR] clears it.
33 OVH Integer overflow high. An overflow occurred in the upper half of the register while executing a SPE
integer instruction.
34 FGH Embedded floating-point guard bit high. Floating-point guard bit from the upper half. The value is
undefined if the processor takes a floating-point exception caused by input error, floating-point overflow,
or floating-point underflow.
35 FXH Embedded floating-point sticky bit high. Floating bit from the upper half. The value is undefined if the
processor takes a floating-point exception caused by input error, floating-point overflow, or floating-point
underflow.
36 FINVH Embedded floating-point invalid operation error high. Set when an input value on the high side is a NaN,
Inf, or Denorm. Also set on a divide if both the dividend and divisor are zero.
37 FDBZH Embedded floating-point divide by zero error high. Set if the dividend is non-zero and the divisor is zero.
38 FUNFH Embedded floating-point underflow error high
39 FOVFH Embedded floating-point overflow error high
40–41 Reserved and should be cleared
42 FINXS Embedded floating-point inexact sticky. FINXS = FINXS | FGH | FXH | FG | FX
43 FINVS Embedded floating-point invalid operation sticky. Location for software to use when implementing true
IEEE floating-point.
44 FDBZS Embedded floating-point divide by zero sticky. FDBZS = FDBZS | FDBZH | FDBZ
45 FUNFS Embedded floating-point underflow sticky. Storage location for software to use when implementing true
IEEE floating-point.
46 FOVFS Embedded floating-point overflow sticky. Storage location for software to use when implementing true
IEEE floating-point.
47 MODE Embedded floating-point mode (read-only on e500)
48 SOV Integer summary overflow. Set whenever an SPE instruction other than mtspr sets OV. SOV remains
set until mtspr[SPEFSCR] clears it.
49 OV Integer overflow. An overflow occurred in the lower half of the register while a SPE integer instruction
was executed.
50 FG Embedded floating-point guard bit. Floating-point guard bit from the lower half. The value is undefined
if the processor takes a floating-point exception caused by input error, floating-point overflow, or
floating-point underflow.
51 FX Embedded floating-point sticky bit. Floating bit from the lower half. The value is undefined if the
processor takes a floating-point exception caused by input error, floating-point overflow, or floating-point
underflow.
52 FINV Embedded floating-point invalid operation error. Set when an input value on the high side is a NaN, Inf,
or Denorm. Also set on a divide if both the dividend and divisor are zero.
53 FDBZ Embedded floating-point divide by zero error. Set if the dividend is non-zero and the divisor is zero.
54 FUNF Embedded floating-point underflow error
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NXP MPC560xP Reference guide

Type
Reference guide

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