MPC5604P Microcontroller Reference Manual, Rev. 6
12 Freescale Semiconductor
24.3.8 Power-down mode ..........................................................................................................759
24.3.9 Auto-clock-off mode .......................................................................................................760
24.4 Register descriptions .....................................................................................................................760
24.4.1 Introduction .....................................................................................................................760
24.4.2 Control logic registers .....................................................................................................762
24.4.3 Interrupt registers ............................................................................................................765
24.4.4 DMA registers .................................................................................................................768
24.4.5 Threshold registers ..........................................................................................................770
24.4.6 Conversion Timing Registers CTR[0] ............................................................................772
24.4.7 Mask registers .................................................................................................................772
24.4.8 Delay registers ................................................................................................................775
24.4.9 Data registers ..................................................................................................................775
Chapter 25Cross Triggering Unit (CTU)
25.1 Introduction ...................................................................................................................................777
25.2 CTU overview ...............................................................................................................................777
25.3 Functional description ...................................................................................................................778
25.3.1 Trigger events features ....................................................................................................778
25.3.2 Trigger generator subunit (TGS) .....................................................................................779
25.3.3 TGS in triggered mode ...................................................................................................779
25.3.4 TGS in sequential mode ..................................................................................................780
25.3.5 TGS counter ....................................................................................................................781
25.4 Scheduler subunit (SU) .................................................................................................................782
25.4.1 ADC commands list ........................................................................................................784
25.4.2 ADC commands list format ............................................................................................784
25.4.3 ADC results .....................................................................................................................785
25.5 Reload mechanism ........................................................................................................................785
25.6 Power safety mode ........................................................................................................................786
25.6.1 MDIS bit .........................................................................................................................786
25.6.2 STOP mode .....................................................................................................................787
25.7 Interrupts and DMA requests ........................................................................................................787
25.7.1 DMA support ..................................................................................................................787
25.7.2 CTU faults and errors .....................................................................................................787
25.7.3 CTU interrupt/DMA requests .........................................................................................788
25.8 Memory map .................................................................................................................................790
25.8.1 Trigger Generator Sub-unit Input Selection Register (TGSISR) ....................................794
25.8.2 Trigger Generator Sub-unit Control Register (TGSCR) .................................................797
25.8.3 Trigger x Compare Register (TxCR, x = 0...7) ...............................................................798
25.8.4 TGS Counter Compare Register (TGSCCR) ..................................................................798
25.8.5 TGS Counter Reload Register (TGSCRR) .....................................................................798
25.8.6 Commands list control register 1 (CLCR1) ....................................................................799
25.8.7 Commands list control register 2 (CLCR2) ....................................................................799
25.8.8 Trigger handler control register 1 (THCR1) ...................................................................800
25.8.9 Trigger handler control register 2 (THCR2) ...................................................................801
25.8.10Commands list register x (x = 1,...,24) (CLRx) ..............................................................803