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MPC5604P Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1
Qorivva MPC5604P Microcontroller
Reference Manual
Devices Supported:
MPC5603P
MPC5604P
MPC560XPRM
Rev. 6
17 June 2014
MPC5604P Microcontroller Reference Manual, Rev. 6
2 Freescale Semiconductor
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MPC5604P Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1
Chapter 1Introduction
1.1 The MPC5604P microcontroller family ..........................................................................................21
1.2 Target applications ..........................................................................................................................22
1.2.1 Application examples .......................................................................................................22
1.3 Features ...........................................................................................................................................23
1.4 Block diagram .................................................................................................................................24
1.5 Critical performance parameters .....................................................................................................26
1.6 Chip-level features ..........................................................................................................................26
1.7 Module features ...............................................................................................................................28
1.7.1 High performance e200z0 core processor .........................................................................28
1.7.2 Crossbar switch (XBAR) ..................................................................................................28
1.7.3 Enhanced direct memory access (eDMA) ........................................................................29
1.7.4 Flash memory ...................................................................................................................29
1.7.5 Static random access memory (SRAM) ............................................................................30
1.7.6 Interrupt controller (INTC) ...............................................................................................31
1.7.7 System status and configuration module (SSCM) ............................................................31
1.7.8 System clocks and clock generation .................................................................................31
1.7.9 Frequency-modulated phase-locked loop (FMPLL) .........................................................32
1.7.10 Main oscillator ..................................................................................................................32
1.7.11 Internal RC oscillator ........................................................................................................32
1.7.12 Periodic interrupt timer (PIT) ...........................................................................................33
1.7.13 System timer module (STM) ............................................................................................33
1.7.14 Software watchdog timer (SWT) ......................................................................................33
1.7.15 Fault collection unit (FCU) ...............................................................................................33
1.7.16 System integration unit – Lite (SIUL) ..............................................................................34
1.7.17 Boot and censorship ..........................................................................................................34
1.7.18 Error correction status module (ECSM) ...........................................................................35
1.7.19 Peripheral bridge (PBRIDGE) ..........................................................................................35
1.7.20 Controller area network (FlexCAN) .................................................................................35
1.7.21 Safety port (FlexCAN) ......................................................................................................36
1.7.22 FlexRay .............................................................................................................................36
1.7.23 Serial communication interface module (LINFlex) ..........................................................37
1.7.24 Deserial serial peripheral interface (DSPI) .......................................................................38
1.7.25 Pulse width modulator (FlexPWM) ..................................................................................38
1.7.26 eTimer ...............................................................................................................................39
1.7.27 Analog-to-digital converter (ADC) module .....................................................................40
1.7.28 Cross triggering unit (CTU) ..............................................................................................41
1.7.29 Nexus development interface (NDI) .................................................................................41
1.7.30 Cyclic redundancy check (CRC) ......................................................................................42
1.7.31 IEEE 1149.1 JTAG controller ...........................................................................................42
1.7.32 On-chip voltage regulator (VREG) ...................................................................................43
1.8 Developer environment ...................................................................................................................43
1.9 Package ............................................................................................................................................43
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Chapter 2MPC5604P memory map
Chapter 3Signal Description
3.1 144-pin LQFP pinout ......................................................................................................................49
3.2 100-pin LQFP pinout ......................................................................................................................50
3.3 Pin description .................................................................................................................................51
3.3.1 Power supply and reference voltage pins .........................................................................51
3.3.2 System pins .......................................................................................................................53
3.3.3 Pin muxing ........................................................................................................................54
3.4 CTU / ADCs / FlexPWM / eTimers connections ............................................................................67
Chapter 4Clock Description
4.1 Clock architecture ...........................................................................................................................73
4.2 Available clock domains .................................................................................................................76
4.2.1 FMPLL_n input reference clock .......................................................................................76
4.2.2 Clock selectors ..................................................................................................................77
4.2.3 Auxiliary clock dividers ....................................................................................................78
4.2.4 External clock divider ......................................................................................................78
4.3 Alternate module clock domains .....................................................................................................78
4.3.1 FlexCAN clock domains ...................................................................................................79
4.3.2 FlexRay clock domains .....................................................................................................79
4.3.3 SWT clock domains ..........................................................................................................79
4.3.4 Nexus Message Clock (MCKO) .......................................................................................79
4.3.5 Cross Triggering Unit (CTU) clock domains ...................................................................79
4.3.6 IPS bus clock sync bridge .................................................................................................80
4.3.7 Peripherals behind the IPS bus clock sync bridge ............................................................80
4.4 Clock behavior in STOP and HALT mode ......................................................................................81
4.5 Software controlled power management/clock gating ....................................................................81
4.6 System clock functional safety ........................................................................................................82
4.7 IRC 16 MHz internal RC oscillator (RC_CTL) ..............................................................................82
4.8 XOSC external crystal oscillator .....................................................................................................83
4.8.1 Functional description .......................................................................................................83
4.8.2 Register description ..........................................................................................................84
4.9 Frequency Modulated Phase Locked Loop (FMPLL) ....................................................................85
4.9.1 Introduction .......................................................................................................................85
4.9.2 Overview ...........................................................................................................................85
4.9.3 Features .............................................................................................................................85
4.9.4 Memory map .....................................................................................................................86
4.9.5 Register description ..........................................................................................................86
4.9.6 Functional description .......................................................................................................89
4.9.7 Recommendations .............................................................................................................92
4.10 Clock Monitor Unit (CMU) ............................................................................................................92
4.10.1 Overview ...........................................................................................................................92
4.10.2 Main features ....................................................................................................................93
4.10.3 Functional description .......................................................................................................93
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4.10.4 Memory map and register description ..............................................................................95
Chapter 5Clock Generation Module (CGM)
5.1 Introduction ...................................................................................................................................103
5.1.1 Features .........................................................................................................................................104
5.1.2 Modes of operation ........................................................................................................................104
5.1.2.1 Normal and Reset Modes of Operation ..........................................................................104
5.1.3 External signal description ............................................................................................................104
5.1.4 Memory map and registers description .........................................................................................104
5.1.5 Register descriptions .....................................................................................................................107
5.1.5.1 Output Clock Enable register (CGM_OC_EN) ..............................................................107
5.1.5.2 Output Clock Division Select register (CGM_OCDS_SC) ............................................108
5.1.5.3 System Clock Select Status register (CGM_SC_SS) ......................................................109
5.1.5.4 Auxiliary Clock 0 Select Control register (CGM_AC0_SC) .........................................110
5.1.5.5 Auxiliary Clock 0 Divider Configuration register (CGM_AC0_DC0) ..........................111
5.1.5.6 Auxiliary Clock 1 Select Control register (CGM_AC1_SC) .........................................111
5.1.5.7 Auxiliary Clock 1 Divider Configuration register (CGM_AC1_DC0) ..........................112
5.1.5.8 Auxiliary Clock 2 Select Control register (CGM_AC2_SC) .........................................113
5.1.5.9 Auxiliary Clock 2 Divider Configuration Register (CGM_AC2_DC0) .........................113
5.1.5.10Auxiliary Clock 3 Select Control register (CGM_AC3_SC) ........................................114
5.1.5.11Auxiliary Clock 3 Divider Configuration register (CGM_AC3_DC0) .........................115
5.2 Functional description ...................................................................................................................116
5.2.1 System clock generation ................................................................................................................116
5.2.1.1 System clock source selection .......................................................................................116
5.2.1.2 ......................................................................................................System clock disable 116
5.2.2 Auxiliary clock generation ...........................................................................................................117
5.2.2.1 ....................................................................................Auxiliary clock source selection 119
5.2.2.2 ......................................................................................Dividers functional description 119
5.2.3 Output clock multiplexing .............................................................................................................119
5.2.4 Output clock division selection .....................................................................................................120
Chapter 6Mode Entry Module (ME)
6.1 Introduction ...................................................................................................................................121
6.1.1 Overview .........................................................................................................................121
6.1.2 Features ...........................................................................................................................121
6.1.3 Modes of Operation ........................................................................................................122
6.2 External signal description ............................................................................................................123
6.3 Memory map and registers description .........................................................................................123
6.3.1 Register summary ...........................................................................................................123
6.3.2 Memory Map ..................................................................................................................126
6.3.3 Registers description .......................................................................................................131
6.4 Functional description ...................................................................................................................150
6.4.1 Mode transition request ..................................................................................................150
6.4.2 Mode details ....................................................................................................................152
6.4.3 Mode transition process ..................................................................................................155
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6.4.4 Protection of mode configuration registers .....................................................................162
6.4.5 Mode transition interrupts ...............................................................................................162
6.4.6 Peripheral clock gating ...................................................................................................164
6.4.7 Application example .......................................................................................................165
Chapter 7Power Control Unit (PCU)
7.1 Introduction ...................................................................................................................................167
7.1.1 Features ...........................................................................................................................168
7.1.2 Modes of operation .........................................................................................................168
7.2 External signal description ............................................................................................................168
7.3 Memory map and register definition .............................................................................................168
7.3.1 Memory map ...................................................................................................................168
7.3.2 Register descriptions .......................................................................................................170
7.4 Functional description ...................................................................................................................172
7.4.1 General ............................................................................................................................172
7.4.2 Reset / Power-on reset ....................................................................................................172
7.4.3 PCU configuration ..........................................................................................................172
7.4.4 Mode transitions .............................................................................................................172
7.4.5 Power domain control state machine ..............................................................................173
7.5 Initialization information ...............................................................................................................182
Chapter 8Reset Generation Module (RGM)
8.1 Introduction ...................................................................................................................................183
8.2 Features .........................................................................................................................................184
8.3 Modes of operation ........................................................................................................................184
8.4 External signal description ............................................................................................................185
8.5 Memory map and registers description .........................................................................................185
8.5.1 Registers description .......................................................................................................188
8.6 Functional description ...................................................................................................................197
8.6.1 Reset state machine .........................................................................................................197
8.6.2 Destructive resets ............................................................................................................200
8.6.3 External reset ..................................................................................................................200
8.6.4 Functional resets .............................................................................................................201
8.6.5 Alternate event generation ..............................................................................................201
8.6.6 Boot mode capturing .......................................................................................................202
Chapter 9Interrupt Controller (INTC)
9.1 Introduction ...................................................................................................................................203
9.2 Features .........................................................................................................................................203
9.3 Block diagram ...............................................................................................................................205
9.4 Modes of operation ........................................................................................................................205
9.4.1 Normal mode ..................................................................................................................205
9.5 Memory map and registers description .........................................................................................207
9.5.1 Module memory map ......................................................................................................207
9.5.2 Registers description .......................................................................................................207
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9.6 Functional description ...................................................................................................................215
9.6.1 Interrupt request sources .................................................................................................223
9.6.2 Priority management .......................................................................................................224
9.6.3 Handshaking with processor ...........................................................................................225
9.7 Initialization/application information ............................................................................................228
9.7.1 Initialization flow ............................................................................................................228
9.7.2 Interrupt exception handler .............................................................................................228
9.7.3 ISR, RTOS, and task hierarchy .......................................................................................230
9.7.4 Order of execution ..........................................................................................................231
9.7.5 Priority ceiling protocol ..................................................................................................232
9.7.6 Selecting priorities according to request rates and deadlines .........................................232
9.7.7 Software configurable interrupt requests ........................................................................233
9.7.8 Lowering priority within an ISR .....................................................................................234
9.7.9 Negating an interrupt request outside of its ISR .............................................................234
9.7.10 Examining LIFO contents ...............................................................................................235
Chapter 10System Status and Configuration Module (SSCM)
10.1 Introduction ...................................................................................................................................237
10.1.1 Overview .........................................................................................................................237
10.1.2 Features ...........................................................................................................................237
10.1.3 Modes of operation .........................................................................................................238
10.2 Memory map and register description ...........................................................................................238
10.2.1 Memory map ...................................................................................................................238
10.2.2 Register description ........................................................................................................238
10.3 Functional description ...................................................................................................................245
10.4 Initialization/application information ............................................................................................245
10.4.1 Reset ................................................................................................................................245
Chapter 11System Integration Unit Lite (SIUL)
11.1 Introduction ...................................................................................................................................247
11.2 Overview .......................................................................................................................................247
11.3 Features .........................................................................................................................................248
11.3.1 Register protection ..........................................................................................................249
11.4 External signal description ............................................................................................................249
11.4.1 Detailed signal descriptions ............................................................................................249
11.5 Memory map and register description ...........................................................................................250
11.5.1 SIUL memory map .........................................................................................................250
11.5.2 Register description ........................................................................................................251
11.6 Functional description ...................................................................................................................269
11.6.1 General ............................................................................................................................269
11.6.2 Pad control ......................................................................................................................269
11.6.3 General purpose input and output pads (GPIO) ..............................................................269
11.6.4 External interrupts ...........................................................................................................270
11.7 Pin muxing ....................................................................................................................................271
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Chapter 12Peripheral Bridge (PBRIDGE)
12.1 Introduction ...................................................................................................................................273
12.1.1 Block diagram .................................................................................................................273
12.1.2 Overview .........................................................................................................................273
12.1.3 Modes of operation .........................................................................................................274
12.2 Functional description ...................................................................................................................274
12.2.1 Access support ................................................................................................................274
12.2.2 General operation ............................................................................................................274
Chapter 13e200z0 and e200z0h Core
13.1 Overview .......................................................................................................................................275
13.2 Features .........................................................................................................................................275
13.2.1 Microarchitecture summary ............................................................................................276
13.3 Core registers and programmer’s model .......................................................................................280
13.3.1 Unimplemented SPRs and read-only SPRs ....................................................................283
13.4 Instruction summary ......................................................................................................................283
Chapter 14Crossbar Switch (XBAR)
14.1 Introduction ...................................................................................................................................285
14.2 Block diagram ...............................................................................................................................285
14.3 Overview .......................................................................................................................................286
14.4 Features .........................................................................................................................................286
14.5 Modes of operation ........................................................................................................................286
14.5.1 Normal mode ..................................................................................................................286
14.5.2 Debug mode ....................................................................................................................286
14.6 Functional description ...................................................................................................................287
14.6.1 Overview .........................................................................................................................287
14.6.2 General operation ............................................................................................................287
14.6.3 Master ports ....................................................................................................................288
14.6.4 Slave ports .......................................................................................................................288
14.6.5 Priority assignment .........................................................................................................288
14.6.6 Arbitration .......................................................................................................................288
Chapter 15Error Correction Status Module (ECSM)
15.1 Introduction ...................................................................................................................................291
15.2 Overview .......................................................................................................................................291
15.3 Features .........................................................................................................................................291
15.4 Memory map and registers description .........................................................................................291
15.4.1 Memory map ...................................................................................................................292
15.4.2 Registers description .......................................................................................................293
15.4.3 ECSM_reg_protection ....................................................................................................310
Chapter 16Internal Static RAM (SRAM)
16.1 Introduction ...................................................................................................................................313
16.2 SRAM operating mode ..................................................................................................................313
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16.3 Module memory map ....................................................................................................................313
16.4 Register descriptions .....................................................................................................................313
16.5 SRAM ECC mechanism ................................................................................................................313
16.5.1 Access timing ..................................................................................................................314
16.5.2 Reset effects on SRAM accesses ....................................................................................315
16.6 Functional description ...................................................................................................................315
16.7 Initialization and application information .....................................................................................315
Chapter 17Flash Memory
17.1 Introduction ...................................................................................................................................317
17.2 Platform Flash controller ...............................................................................................................317
17.2.1 Introduction .....................................................................................................................317
17.2.2 Modes of operation .........................................................................................................319
17.2.3 External signal descriptions ............................................................................................319
17.2.4 Memory map and registers description ...........................................................................319
17.2.5 Functional description .....................................................................................................321
17.2.6 Basic interface protocol ..................................................................................................322
17.2.7 Access protections ..........................................................................................................322
17.2.8 Read cycles — buffer miss .............................................................................................322
17.2.9 Read cycles — buffer hit ................................................................................................323
17.2.10Write cycles .....................................................................................................................323
17.2.11Error termination .............................................................................................................323
17.2.12Access pipelining ............................................................................................................324
17.2.13Flash error response operation ........................................................................................324
17.2.14Bank0 page read buffers and prefetch operation ............................................................324
17.2.15Bank1 temporary holding register ..................................................................................327
17.2.16Read-While-Write functionality .....................................................................................327
17.2.17Wait state emulation ........................................................................................................329
17.2.18Timing diagrams .............................................................................................................330
17.3 Flash memory ................................................................................................................................337
17.3.1 Introduction .....................................................................................................................337
17.3.2 Main features ..................................................................................................................337
17.3.3 Block diagram .................................................................................................................337
17.3.4 Functional description .....................................................................................................339
17.3.5 Operating modes .............................................................................................................343
17.3.6 Registers description .......................................................................................................346
17.3.7 Register map ...................................................................................................................347
17.3.8 Programming considerations ..........................................................................................378
Chapter 18Enhanced Direct Memory Access (eDMA)
18.1 Introduction ...................................................................................................................................391
18.2 Overview .......................................................................................................................................391
18.3 Features .........................................................................................................................................392
18.4 Modes of operation ........................................................................................................................393
18.4.1 Normal mode ..................................................................................................................393
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18.4.2 Debug mode ....................................................................................................................393
18.5 Memory map and register definition .............................................................................................394
18.5.1 Memory map ...................................................................................................................394
18.5.2 Register descriptions .......................................................................................................396
18.6 Functional description ...................................................................................................................416
18.6.1 eDMA microarchitecture ................................................................................................416
18.6.2 eDMA basic data flow ....................................................................................................418
18.6.3 eDMA performance ........................................................................................................420
18.7 Initialization / application information ..........................................................................................423
18.7.1 eDMA initialization ........................................................................................................423
18.7.2 DMA programming errors ..............................................................................................425
18.7.3 DMA request assignments ..............................................................................................426
18.7.4 DMA arbitration mode considerations ...........................................................................426
18.7.5 DMA transfer ..................................................................................................................427
18.7.6 TCD status ......................................................................................................................430
18.7.7 Channel linking ...............................................................................................................431
18.7.8 Dynamic programming ...................................................................................................432
Chapter 19DMA Channel Mux (DMA_MUX)
19.1 Introduction ...................................................................................................................................435
19.1.1 Overview .........................................................................................................................435
19.1.2 Features ...........................................................................................................................435
19.1.3 Modes of operation .........................................................................................................436
19.2 External signal description ............................................................................................................436
19.2.1 Overview .........................................................................................................................436
19.3 Memory map and register definition .............................................................................................436
19.3.1 Memory map ...................................................................................................................436
19.3.2 Register descriptions .......................................................................................................437
19.4 DMA request mapping ..................................................................................................................438
19.5 Functional description ...................................................................................................................439
19.5.1 DMA channels with periodic triggering capability ........................................................440
19.5.2 DMA channels with no triggering capability .................................................................442
19.6 Initialization/application information ............................................................................................442
19.6.1 Reset ................................................................................................................................442
19.6.2 Enabling and configuring sources ...................................................................................442
Chapter 20
FlexRay Communication Controller (FlexRay)
20.1 Introduction ...................................................................................................................................447
20.1.1 Color coding ...................................................................................................................447
20.1.2 Overview .........................................................................................................................447
20.1.3 Features ...........................................................................................................................448
20.1.4 Modes of operation .........................................................................................................449
20.2 External signal description ............................................................................................................450
20.2.1 Detailed signal descriptions ............................................................................................451
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20.3 Controller host interface clocking .................................................................................................452
20.4 Protocol engine clocking ...............................................................................................................452
20.4.1 PLL Clocking ..................................................................................................................452
20.5 Memory map and register description ...........................................................................................452
20.5.1 Memory map ...................................................................................................................452
20.5.2 Register descriptions .......................................................................................................458
20.6 Functional description ...................................................................................................................526
20.6.1 Message buffer concept ..................................................................................................526
20.6.2 Physical message buffer ..................................................................................................526
20.6.3 Message buffer types ......................................................................................................527
20.6.4 FlexRay memory layout ..................................................................................................533
20.6.5 Physical message buffer description ...............................................................................535
20.6.6 Individual message buffer functional description ...........................................................544
20.6.7 Individual message buffer search ....................................................................................569
20.6.8 Individual message buffer reconfiguration .....................................................................572
20.6.9 Receive FIFO ..................................................................................................................573
20.6.10Channel device modes ....................................................................................................577
20.6.11External clock synchronization .......................................................................................579
20.6.12Sync frame ID and sync frame deviation tables .............................................................580
20.6.13MTS generation ..............................................................................................................583
20.6.14Key slot transmission ......................................................................................................584
20.6.15Sync frame filtering ........................................................................................................584
20.6.16Strobe signal support .......................................................................................................585
20.6.17Timer support ..................................................................................................................586
20.6.18Slot status monitoring .....................................................................................................587
20.6.19System bus access ...........................................................................................................591
20.6.20Interrupt support .............................................................................................................592
20.6.21Lower bit rate support .....................................................................................................595
20.7 Application information ................................................................................................................596
20.7.1 Initialization sequence ....................................................................................................596
20.7.2 Shut down sequence ........................................................................................................597
20.7.3 Number of usable message buffers .................................................................................597
20.7.4 Protocol control command execution .............................................................................598
20.7.5 Protocol reset command ..................................................................................................599
20.7.6 Message buffer search on simple message buffer configuration ....................................600
Chapter 21Deserial Serial Peripheral Interface (DSPI)
21.1 Introduction ...................................................................................................................................605
21.2 Block diagram ...............................................................................................................................605
21.3 Overview .......................................................................................................................................606
21.4 Features .........................................................................................................................................606
21.5 Modes of operation ........................................................................................................................607
21.5.1 Master mode ...................................................................................................................607
21.5.2 Slave mode ......................................................................................................................607
21.5.3 Module disable mode ......................................................................................................608
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21.5.4 Debug mode ....................................................................................................................608
21.6 External signal description ............................................................................................................608
21.6.1 Signal overview ..............................................................................................................608
21.6.2 Signal names and descriptions ........................................................................................608
21.7 Memory map and registers description .........................................................................................610
21.7.1 Memory map ...................................................................................................................610
21.7.2 Registers description .......................................................................................................611
21.8 Functional description ...................................................................................................................628
21.8.1 Modes of operation .........................................................................................................629
21.8.2 Start and stop of DSPI transfers ......................................................................................630
21.8.3 Serial Peripheral Interface (SPI) configuration ..............................................................631
21.8.4 DSPI baud rate and clock delay generation ....................................................................634
21.8.5 Transfer formats ..............................................................................................................637
21.8.6 Continuous Serial communications clock .......................................................................644
21.8.7 Interrupts/DMA requests ................................................................................................646
21.8.8 Power saving features .....................................................................................................647
21.9 Initialization and application information .....................................................................................648
21.9.1 Managing queues ............................................................................................................648
21.9.2 Baud rate settings ............................................................................................................648
21.9.3 Delay settings ..................................................................................................................650
21.9.4 MPC5604P DSPI compatibility with QSPI of the MPC500 MCUs ...............................650
21.9.5 Calculation of FIFO pointer addresses ...........................................................................651
Chapter 22
LIN Controller (LINFlex)
22.1 Introduction ...................................................................................................................................655
22.2 Main features .................................................................................................................................655
22.2.1 LIN mode features ..........................................................................................................655
22.2.2 UART mode features ......................................................................................................655
22.2.3 Features common to LIN and UART ..............................................................................655
22.3 General description .......................................................................................................................656
22.4 Fractional baud rate generation .....................................................................................................657
22.5 Operating modes ...........................................................................................................................659
22.5.1 Initialization mode ..........................................................................................................660
22.5.2 Normal mode ..................................................................................................................660
22.5.3 Low power mode (Sleep) ................................................................................................660
22.6 Test modes .....................................................................................................................................660
22.6.1 Loop Back mode .............................................................................................................660
22.6.2 Self Test mode .................................................................................................................661
22.7 Memory map and registers description .........................................................................................661
22.7.1 Memory map ...................................................................................................................661
22.8 Functional description ...................................................................................................................687
22.8.1 UART mode ....................................................................................................................687
22.8.2 LIN mode ........................................................................................................................689
22.8.3 8-bit timeout counter .......................................................................................................697
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22.8.4 Interrupts .........................................................................................................................699
Chapter 23FlexCAN
23.1 Introduction ...................................................................................................................................701
23.1.1 Overview .........................................................................................................................701
23.1.2 FlexCAN module features ..............................................................................................702
23.1.3 Modes of operation .........................................................................................................703
23.2 External signal description ............................................................................................................704
23.2.1 Overview .........................................................................................................................704
23.2.2 Signal Descriptions .........................................................................................................704
23.3 Memory map and registers description .........................................................................................704
23.3.1 FlexCAN memory mapping ............................................................................................704
23.3.2 Message buffer structure .................................................................................................706
23.3.3 Rx FIFO structure ...........................................................................................................710
23.3.4 Registers description .......................................................................................................712
23.4 Functional description ...................................................................................................................730
23.4.1 Overview .........................................................................................................................730
23.4.2 Transmit process .............................................................................................................730
23.4.3 Arbitration process ..........................................................................................................731
23.4.4 Receive process ...............................................................................................................732
23.4.5 Matching process ............................................................................................................733
23.4.6 Data coherence ................................................................................................................734
23.4.7 Rx FIFO ..........................................................................................................................737
23.4.8 CAN protocol related features ........................................................................................738
23.4.9 Modes of operation details ..............................................................................................743
23.4.10Interrupts .........................................................................................................................744
23.4.11Bus interface ...................................................................................................................745
23.5 Initialization/application information ............................................................................................745
23.5.1 FlexCAN initialization sequence ....................................................................................745
Chapter 24
Analog-to-Digital Converter (ADC)
24.1 Overview .......................................................................................................................................747
24.1.1 Device-specific features ..................................................................................................747
24.1.2 Device-specific pin configuration features .....................................................................748
24.1.3 Device-specific implementation .....................................................................................748
24.2 Introduction ...................................................................................................................................748
24.3 Functional description ...................................................................................................................749
24.3.1 Analog channel conversion .............................................................................................749
24.3.2 Analog clock generator and conversion timings .............................................................752
24.3.3 ADC sampling and conversion timing ............................................................................753
24.3.4 ADC CTU (Cross Triggering Unit) ................................................................................756
24.3.5 Programmable analog watchdog .....................................................................................757
24.3.6 DMA functionality ..........................................................................................................759
24.3.7 Interrupts .........................................................................................................................759
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24.3.8 Power-down mode ..........................................................................................................759
24.3.9 Auto-clock-off mode .......................................................................................................760
24.4 Register descriptions .....................................................................................................................760
24.4.1 Introduction .....................................................................................................................760
24.4.2 Control logic registers .....................................................................................................762
24.4.3 Interrupt registers ............................................................................................................765
24.4.4 DMA registers .................................................................................................................768
24.4.5 Threshold registers ..........................................................................................................770
24.4.6 Conversion Timing Registers CTR[0] ............................................................................772
24.4.7 Mask registers .................................................................................................................772
24.4.8 Delay registers ................................................................................................................775
24.4.9 Data registers ..................................................................................................................775
Chapter 25Cross Triggering Unit (CTU)
25.1 Introduction ...................................................................................................................................777
25.2 CTU overview ...............................................................................................................................777
25.3 Functional description ...................................................................................................................778
25.3.1 Trigger events features ....................................................................................................778
25.3.2 Trigger generator subunit (TGS) .....................................................................................779
25.3.3 TGS in triggered mode ...................................................................................................779
25.3.4 TGS in sequential mode ..................................................................................................780
25.3.5 TGS counter ....................................................................................................................781
25.4 Scheduler subunit (SU) .................................................................................................................782
25.4.1 ADC commands list ........................................................................................................784
25.4.2 ADC commands list format ............................................................................................784
25.4.3 ADC results .....................................................................................................................785
25.5 Reload mechanism ........................................................................................................................785
25.6 Power safety mode ........................................................................................................................786
25.6.1 MDIS bit .........................................................................................................................786
25.6.2 STOP mode .....................................................................................................................787
25.7 Interrupts and DMA requests ........................................................................................................787
25.7.1 DMA support ..................................................................................................................787
25.7.2 CTU faults and errors .....................................................................................................787
25.7.3 CTU interrupt/DMA requests .........................................................................................788
25.8 Memory map .................................................................................................................................790
25.8.1 Trigger Generator Sub-unit Input Selection Register (TGSISR) ....................................794
25.8.2 Trigger Generator Sub-unit Control Register (TGSCR) .................................................797
25.8.3 Trigger x Compare Register (TxCR, x = 0...7) ...............................................................798
25.8.4 TGS Counter Compare Register (TGSCCR) ..................................................................798
25.8.5 TGS Counter Reload Register (TGSCRR) .....................................................................798
25.8.6 Commands list control register 1 (CLCR1) ....................................................................799
25.8.7 Commands list control register 2 (CLCR2) ....................................................................799
25.8.8 Trigger handler control register 1 (THCR1) ...................................................................800
25.8.9 Trigger handler control register 2 (THCR2) ...................................................................801
25.8.10Commands list register x (x = 1,...,24) (CLRx) ..............................................................803
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25.8.11FIFO DMA control register (FDCR) ..............................................................................805
25.8.12FIFO control register (FCR) ...........................................................................................805
25.8.13FIFO threshold register (FTH) ........................................................................................807
25.8.14FIFO status register (FST) ..............................................................................................807
25.8.15FIFO Right aligned data x (x = 0,...,3) (FRx) ..................................................................809
25.8.16FIFO signed Left aligned data x (x = 0,...,3) (FLx) .........................................................810
25.8.17Cross triggering unit error flag register (CTUEFR) .......................................................810
25.8.18Cross triggering unit interrupt flag register (CTUIFR) ..................................................811
25.8.19Cross triggering unit interrupt/DMA register (CTUIR) .................................................812
25.8.20Control ON time register (COTR) ..................................................................................813
25.8.21Cross triggering unit control register (CTUCR) .............................................................814
25.8.22Cross triggering unit digital filter (CTUDF) ...................................................................815
25.8.23Cross triggering unit power control register (CTUPCR) ................................................816
Chapter 26FlexPWM
26.1 Overview .......................................................................................................................................817
26.2 Features .........................................................................................................................................817
26.3 Modes of operation ........................................................................................................................818
26.4 Block diagrams ..............................................................................................................................819
26.4.1 Module level ...................................................................................................................819
26.4.2 PWM submodule ............................................................................................................820
26.5 External signal descriptions ..........................................................................................................820
26.5.1 PWMA[n] and PWMB[n] — external PWM pair ..........................................................820
26.5.2 PWMX[n] — auxiliary PWM signal ..............................................................................820
26.5.3 FAULT[n] — fault inputs ...............................................................................................821
26.5.4 EXT_SYNC — external synchronization signal ............................................................821
26.5.5 EXT_FORCE — external output force signal ................................................................821
26.5.6 OUT_TRIG0[n] and OUT_TRIG1[n] — output triggers ...............................................821
26.5.7 EXT_CLK — external clock signal ................................................................................821
26.6 Memory map and registers ............................................................................................................821
26.6.1 FlexPWM module memory map .....................................................................................821
26.6.2 Register descriptions .......................................................................................................825
26.6.3 Submodule registers ........................................................................................................825
26.6.4 Configuration registers ...................................................................................................844
26.6.5 Fault channel registers ....................................................................................................850
26.7 Functional description ...................................................................................................................854
26.7.1 Center-aligned PWMs .....................................................................................................854
26.7.2 Edge-aligned PWMs .......................................................................................................855
26.7.3 Phase-shifted PWMs .......................................................................................................855
26.7.4 Double switching PWMs ................................................................................................857
26.7.5 ADC triggering ...............................................................................................................858
26.7.6 Enhanced capture capabilities (E-Capture) .....................................................................860
26.7.7 Synchronous switching of multiple outputs ....................................................................862
26.8 Functional details ..........................................................................................................................863
26.8.1 PWM clocking ................................................................................................................863
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26.8.2 Register reload logic .......................................................................................................864
26.8.3 Counter synchronization .................................................................................................865
26.8.4 PWM generation .............................................................................................................866
26.8.5 Output compare capabilities ...........................................................................................867
26.8.6 Force out logic ................................................................................................................867
26.8.7 Independent or complementary channel operation .........................................................869
26.8.8 Deadtime insertion logic .................................................................................................870
26.8.9 Top/bottom correction .....................................................................................................871
26.8.10Manual correction ...........................................................................................................873
26.8.11Output logic ....................................................................................................................874
26.8.12E-Capture ........................................................................................................................875
26.8.13Fault protection ...............................................................................................................876
26.8.14Fault pin filter .................................................................................................................877
26.8.15Automatic fault clearing .................................................................................................878
26.8.16Manual fault clearing ......................................................................................................878
26.8.17Fault testing .....................................................................................................................879
26.9 PWM generator loading ................................................................................................................879
26.9.1 Load enable .....................................................................................................................879
26.9.2 Load frequency ...............................................................................................................880
26.9.3 Reload flag ......................................................................................................................881
26.9.4 Reload errors ...................................................................................................................881
26.9.5 Initialization ....................................................................................................................881
26.10Clocks ............................................................................................................................................882
26.11 Interrupts .......................................................................................................................................882
26.12DMA ..............................................................................................................................................883
Chapter 27eTimer
27.1 Introduction ...................................................................................................................................885
27.2 Features .........................................................................................................................................885
27.3 Module block diagram ..................................................................................................................887
27.4 Channel block diagram ..................................................................................................................888
27.5 External signal descriptions ..........................................................................................................888
27.5.1 ETC[5:0]—eTimer input/outputs ....................................................................................888
27.6 Memory map and registers ............................................................................................................888
27.6.1 Overview .........................................................................................................................888
27.6.2 Timer channel registers ...................................................................................................892
27.6.3 Watchdog timer registers ................................................................................................907
27.6.4 Configuration registers ...................................................................................................908
27.7 Functional description ...................................................................................................................909
27.7.1 General ............................................................................................................................909
27.7.2 Counting modes ..............................................................................................................910
27.7.3 Other features ..................................................................................................................915
27.8 Clocks ............................................................................................................................................916
27.9 Interrupts .......................................................................................................................................917
27.10DMA ..............................................................................................................................................918
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Chapter 28Functional Safety
28.1 Introduction ...................................................................................................................................919
28.2 Register protection module ...........................................................................................................919
28.2.1 Overview .........................................................................................................................919
28.2.2 Features ...........................................................................................................................919
28.2.3 Modes of operation .........................................................................................................920
28.2.4 External signal description ..............................................................................................920
28.2.5 Memory map and registers description ...........................................................................920
28.2.6 Functional description .....................................................................................................924
28.2.7 Reset ................................................................................................................................928
28.3 Software Watchdog Timer (SWT) .................................................................................................928
28.3.1 Overview .........................................................................................................................928
28.3.2 Features ...........................................................................................................................928
28.3.3 Modes of operation .........................................................................................................928
28.3.4 External signal description ..............................................................................................929
28.3.5 SWT memory map and registers description ..................................................................929
28.3.6 Functional description .....................................................................................................934
Chapter 29Fault Collection Unit (FCU)
29.1 Introduction ...................................................................................................................................937
29.1.1 Overview .........................................................................................................................937
29.1.2 Features ...........................................................................................................................940
29.1.3 Modes of operation .........................................................................................................940
29.2 Memory map and register definition .............................................................................................940
29.2.1 Memory map ...................................................................................................................941
29.2.2 Register summary ...........................................................................................................941
29.2.3 Register descriptions .......................................................................................................943
29.3 Functional description ...................................................................................................................953
29.3.1 State machine ..................................................................................................................954
29.3.2 Output generation protocol .............................................................................................955
Chapter 30Wakeup Unit (WKPU)
30.1 Overview .......................................................................................................................................959
30.2 Features .........................................................................................................................................959
30.3 External signal description ............................................................................................................959
30.4 Memory map and registers description .........................................................................................959
30.4.1 Memory map ...................................................................................................................959
30.4.2 Registers description .......................................................................................................960
30.5 Functional description ...................................................................................................................961
30.5.1 General ............................................................................................................................961
30.5.2 Non-Maskable Interrupts ................................................................................................962
Chapter 31Periodic Interrupt Timer (PIT)
31.1 Introduction ...................................................................................................................................965
31.2 Features .........................................................................................................................................965
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31.3 Signal description ..........................................................................................................................966
31.4 Memory map and registers description .........................................................................................966
31.4.1 Memory map ...................................................................................................................966
31.4.2 Registers description .......................................................................................................967
31.5 Functional description ...................................................................................................................970
31.5.1 General ............................................................................................................................970
31.5.2 Interrupts .........................................................................................................................971
31.6 Initialization and application information .....................................................................................972
31.6.1 Example configuration ....................................................................................................972
Chapter 32System Timer Module (STM)
32.1 Overview .......................................................................................................................................973
32.2 Features .........................................................................................................................................973
32.3 Modes of operation ........................................................................................................................973
32.4 External signal description ............................................................................................................973
32.5 Memory map and registers description .........................................................................................973
32.5.1 Memory map ...................................................................................................................973
32.5.2 Registers description .......................................................................................................974
32.6 Functional description ...................................................................................................................978
Chapter 33Cyclic Redundancy Check (CRC)
33.1 Introduction ...................................................................................................................................979
33.1.1 Glossary ..........................................................................................................................979
33.2 Main features .................................................................................................................................979
33.2.1 Standard features .............................................................................................................979
33.3 Block diagram ...............................................................................................................................979
33.3.1 IPS bus interface .............................................................................................................980
33.4 Functional description ...................................................................................................................980
33.5 Memory map and registers description .........................................................................................982
33.5.1 CRC Configuration Register (CRC_CFG) .....................................................................983
33.5.2 CRC Input Register (CRC_INP) .....................................................................................984
33.5.3 CRC Current Status Register (CRC_CSTAT) .................................................................985
33.5.4 CRC Output Register (CRC_OUTP) ..............................................................................985
33.6 Use cases and limitations ..............................................................................................................986
Chapter 34Boot Assist Module (BAM)
34.1 Overview .......................................................................................................................................991
34.2 Features .........................................................................................................................................991
34.3 Boot modes ....................................................................................................................................991
34.4 Memory map .................................................................................................................................991
34.5 Functional description ...................................................................................................................992
34.5.1 Entering boot modes .......................................................................................................992
34.5.2 MPC5604P boot pins ......................................................................................................993
34.5.3 Reset Configuration Half Word (RCHW) .......................................................................994
34.5.4 Single chip boot mode ....................................................................................................995
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34.5.5 Boot through BAM .........................................................................................................996
34.5.6 Boot from UART—autobaud disabled .........................................................................1002
34.5.7 Bootstrap with FlexCAN—autobaud disabled .............................................................1003
34.6 FlexCAN boot mode download protocol ....................................................................................1004
34.6.1 Autobaud feature ...........................................................................................................1004
34.6.2 Interrupt ........................................................................................................................1016
34.7 Censorship ...................................................................................................................................1016
Chapter 35Voltage Regulators and Power Supplies
35.1 Voltage regulator .........................................................................................................................1023
35.1.1 High Power or Main Regulator (HPREG) ....................................................................1023
35.1.2 Low Voltage Detectors (LVD) and Power On Reset (POR) .........................................1023
35.1.3 VREG digital interface .................................................................................................1024
35.1.4 Registers Description ....................................................................................................1025
35.2 Power supply strategy .................................................................................................................1026
Chapter 36IEEE 1149.1 Test Access Port Controller (JTAGC)
36.1 Introduction .................................................................................................................................1029
36.2 Block diagram .............................................................................................................................1029
36.3 Overview .....................................................................................................................................1029
36.4 Features .......................................................................................................................................1030
36.5 Modes of operation ......................................................................................................................1030
36.5.1 Reset ..............................................................................................................................1030
36.5.2 IEEE 1149.1-2001 defined test modes ..........................................................................1030
36.6 External signal description ..........................................................................................................1031
36.7 Memory map and registers description .......................................................................................1031
36.7.1 Instruction register ........................................................................................................1032
36.7.2 Bypass register ..............................................................................................................1032
36.7.3 Device identification register ........................................................................................1032
36.7.4 Boundary scan register ..................................................................................................1033
36.8 Functional description .................................................................................................................1033
36.8.1 JTAGC reset configuration ...........................................................................................1033
36.8.2 IEEE 1149.1-2001 (JTAG) Test Access Port (TAP) .....................................................1033
36.8.3 TAP controller state machine ........................................................................................1034
36.8.4 JTAGC instructions .......................................................................................................1036
36.8.5 Boundary scan ...............................................................................................................1038
36.9 e200z0 OnCE controller ..............................................................................................................1038
36.9.1 e200z0 OnCE controller block diagram .......................................................................1038
36.9.2 e200z0 OnCE controller functional description ...........................................................1039
36.9.3 e200z0 OnCE controller registers description ..............................................................1039
36.10Initialization/Application Information ........................................................................................1041
Chapter 37Nexus Development Interface (NDI)
37.1 Introduction .................................................................................................................................1043
37.2 Block diagram .............................................................................................................................1043
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37.3 Features .......................................................................................................................................1044
37.4 Modes of operation ......................................................................................................................1045
37.4.1 Nexus reset ....................................................................................................................1045
37.4.2 Full-Port mode ..............................................................................................................1046
37.5 External signal description ..........................................................................................................1046
37.5.1 Nexus signal reset states ...............................................................................................1046
37.6 Memory map and registers description .......................................................................................1047
37.6.1 Nexus debug interface registers ....................................................................................1047
37.6.2 Registers description .....................................................................................................1048
37.7 Functional description .................................................................................................................1058
37.7.1 Enabling Nexus clients for TAP access ........................................................................1058
37.7.2 Configuring the NDI for Nexus messaging ..................................................................1058
37.7.3 Programmable MCKO frequency .................................................................................1059
37.7.4 Nexus messaging ..........................................................................................................1059
37.7.5 EVTO sharing ...............................................................................................................1060
37.7.6 Debug mode control ......................................................................................................1060
Chapter 38Document Revision History
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