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MPC5675K Microcontroller Reference Manual, Rev 10
Freescale Semiconductor 1
Qorivva MPC5675K Microcontroller
Reference Manual
Devices Supported:
32-bit Qorivva dual-core MCU built on Power Architecture® technology,
suitable for ISO26262 ASIL-D chassis and safety applications
MPC5673K
MPC5674K
MPC5675K
MPC5675KRM
Rev 10
Nov 2013
MPC5675K Microcontroller Reference Manual, Rev 10
2 Freescale Semiconductor
MPC5675K Microcontroller Reference Manual, Rev. 10
Freescale Semiconductor 3
Chapter 1
Introduction
1.1 The MPC5675K microcontroller .....................................................................................................33
1.2 MPC5675K microcontroller comparison.........................................................................................34
1.2.1 Block diagram....................................................................................................................36
1.3 Feature summary..............................................................................................................................38
1.4 Feature details ..................................................................................................................................39
1.4.1 High-performance e200z7d core processor.......................................................................39
1.4.2 Crossbar Switch (XBAR) ..................................................................................................40
1.4.3 Memory Protection Unit (MPU)........................................................................................40
1.4.4 Enhanced Direct Memory Access (eDMA) controller ......................................................40
1.4.5 Interrupt Controller (INTC)...............................................................................................40
1.4.6 Frequency-Modulated Phase-Locked Loop (FMPLL) ......................................................41
1.4.7 External Bus Interface (EBI) .............................................................................................41
1.4.8 On-chip flash memory .......................................................................................................42
1.4.9 Cache memory...................................................................................................................42
1.4.10 On-chip internal static RAM (SRAM)...............................................................................42
1.4.11 DRAM controller...............................................................................................................42
1.4.12 Boot Assist Module (BAM)...............................................................................................43
1.4.13 Parallel Data Interface (PDI) .............................................................................................43
1.4.14 Deserial Serial Peripheral Interface (DSPI) modules ........................................................43
1.4.15 Serial Communication Interface Module (LINFlex).........................................................44
1.4.16 FlexCAN............................................................................................................................45
1.4.17 Dual-channel FlexRay controller.......................................................................................45
1.4.18 Periodic Interrupt Timer (PIT)...........................................................................................45
1.4.19 System Timer Module (STM)............................................................................................45
1.4.20 Motor control (MOTC) peripherals...................................................................................46
1.4.21 Redundancy Control and Checker Unit (RCCU) ..............................................................48
1.4.22 Software Watchdog Timer (SWT).....................................................................................48
1.4.23 Fault Collection and Control Unit (FCCU) .......................................................................49
1.4.24 System Integration Unit Lite (SIUL).................................................................................49
1.4.25 Cyclic Redundancy Checker (CRC) unit...........................................................................49
1.4.26 Non-Maskable Interrupt (NMI) .........................................................................................50
1.4.27 System Status and Configuration Module (SSCM)...........................................................50
1.4.28 Nexus Development Interface (NDI).................................................................................50
1.4.29 IEEE 1149.1 JTAG Controller (JTAGC) ...........................................................................50
Chapter 2
Memory Map
2.1 Introduction......................................................................................................................................53
Chapter 3
Signal Description
3.1 Package pinouts................................................................................................................................61
3.2 Pin descriptions................................................................................................................................64
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3.2.1 Multiplexed pins ................................................................................................................64
3.2.2 Power supply and reference voltage pins ........................................................................109
3.2.3 System pins......................................................................................................................115
Chapter 4
Functional Safety
4.1 Overview........................................................................................................................................119
4.2 Redundancy....................................................................................................................................119
4.3 Sphere of Replication (SoR) ..........................................................................................................119
4.3.1 Input synchronization ......................................................................................................120
4.3.2 Sphere of Replication (SoR)............................................................................................121
4.4 Built-In Self-Test (BIST)................................................................................................................121
4.4.1 BIST during boot .............................................................................................................121
4.4.2 Software-triggered BIST during operation......................................................................122
4.4.3 Software-triggered self-tests after boot............................................................................122
4.5 Memory error detection and correction..........................................................................................122
4.6 Monitoring......................................................................................................................................122
4.7 Software measures..........................................................................................................................122
4.8 Fault reaction..................................................................................................................................123
4.9 External measures ..........................................................................................................................123
Chapter 5
Boot and Operating Modes
5.1 Boot modes.....................................................................................................................................125
5.2 Hardware configuration..................................................................................................................125
5.3 Boot-sector search..........................................................................................................................125
5.3.1 Potential boot sectors.......................................................................................................125
5.3.2 Reset configuration halfword (RCHW)...........................................................................127
5.3.3 Boot and alternate boot....................................................................................................127
5.4 Device behavior by boot mode.......................................................................................................127
5.4.1 Single-chip mode—unsecured.........................................................................................127
5.4.2 Single-chip mode—secured.............................................................................................128
5.4.3 Serial boot loader mode—public password enabled........................................................128
5.4.4 Serial boot loader mode—flash memory password enabled ...........................................128
5.4.5 Static mode.......................................................................................................................128
5.5 Operating modes ............................................................................................................................128
5.5.1 Lock Step Mode (LSM)...................................................................................................129
5.5.2 Decoupled Parallel mode (DPM).....................................................................................129
5.6 Selecting LSM or DPM..................................................................................................................130
5.6.1 Entering DPM..................................................................................................................130
5.6.2 Entering LSM ..................................................................................................................130
Chapter 6
e200z7 Core
6.1 e200z7 Overview............................................................................................................................133
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6.1.1 Features............................................................................................................................134
6.1.2 Microarchitecture summary.............................................................................................135
6.2 Programming model.......................................................................................................................139
6.2.1 Register set.......................................................................................................................139
6.2.2 Instruction set...................................................................................................................142
6.2.3 Interrupts and exception handling....................................................................................144
6.3 Microarchitecture summary ...........................................................................................................148
6.3.1 Instruction unit features ...................................................................................................150
6.3.2 Integer unit features.........................................................................................................150
6.3.3 Load/Store Unit (LSU) features.......................................................................................150
6.3.4 L1 cache features .............................................................................................................150
6.3.5 Memory Management Unit (MMU) features ..................................................................151
6.3.6 System bus (core complex interface) features.................................................................152
6.3.7 Nexus 3+ module features ...............................................................................................152
Chapter 7
General-Purpose Static RAM (SRAM)
7.1 Introduction....................................................................................................................................153
7.2 SRAM Controller (SRAMC) .........................................................................................................153
7.2.1 Overview..........................................................................................................................153
7.2.2 ECC on SRAM array address lines..................................................................................153
7.2.3 System integration ...........................................................................................................153
7.3 SRAM operating mode...................................................................................................................157
7.4 Registers.........................................................................................................................................158
7.5 SRAM ECC mechanism.................................................................................................................158
7.5.1 Access timing...................................................................................................................158
7.5.2 Reset effects on SRAM accesses.....................................................................................159
7.6 Functional description....................................................................................................................160
7.7 Initialization and application information......................................................................................160
Chapter 8
Flash Memory
8.1 Introduction....................................................................................................................................161
8.1.1 Features............................................................................................................................162
8.1.2 Modes of operation..........................................................................................................163
8.2 Memory map and registers.............................................................................................................164
8.2.1 Module memory map.......................................................................................................164
8.2.2 Register overview ............................................................................................................166
8.2.3 Register descriptions........................................................................................................167
8.2.4 Shadow sector..................................................................................................................201
8.2.5 Test sector ........................................................................................................................207
8.2.6 Functional description......................................................................................................211
8.2.7 Interaction in LSM and DPM ..........................................................................................216
8.3 Programming considerations..........................................................................................................217
8.3.1 Modify operations............................................................................................................217
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8.3.2 User test mode .................................................................................................................222
8.3.3 Error Correction Code (ECC)..........................................................................................225
8.3.4 Protection strategies.........................................................................................................227
Chapter 9
Multi-Layer AHB Crossbar Switch (XBAR)
9.1 Introduction....................................................................................................................................229
9.1.1 Logical master IDs...........................................................................................................229
9.1.2 Master port allocation......................................................................................................230
9.1.3 Slave port allocation ........................................................................................................231
9.2 XBAR registers..............................................................................................................................232
9.2.1 Register summary ............................................................................................................233
9.2.2 XBAR register descriptions.............................................................................................233
9.3 Overview........................................................................................................................................236
9.3.1 Features............................................................................................................................236
9.3.2 Limitations.......................................................................................................................237
9.3.3 General operation.............................................................................................................237
9.3.4 Coherency........................................................................................................................238
9.3.5 XBAR_2 configuration....................................................................................................238
9.3.6 Port splitter.......................................................................................................................238
9.3.7 Arbitration........................................................................................................................239
9.3.8 Priority assignment ..........................................................................................................240
9.3.9 Master port functionality .................................................................................................240
9.3.10 Slave port functionality....................................................................................................243
9.4 Initialization/application information.............................................................................................249
9.5 Interface..........................................................................................................................................249
9.5.1 Overview..........................................................................................................................249
9.5.2 Master ports .....................................................................................................................249
9.5.3 Slave ports........................................................................................................................250
Chapter 10
Peripheral Bridge (PBRIDGE)
10.1 Introduction....................................................................................................................................253
10.2 Block interface ...............................................................................................................................253
10.3 Features ..........................................................................................................................................253
10.4 Memory map and register description............................................................................................254
10.4.1 Register access.................................................................................................................254
10.4.2 Memory map....................................................................................................................254
10.4.3 Register descriptions........................................................................................................256
10.5 Functional description....................................................................................................................260
10.5.1 Access support.................................................................................................................261
10.5.2 General operation.............................................................................................................261
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Chapter 11
Analog-to-Digital Converter (ADC)
11.1 Introduction....................................................................................................................................263
11.2 Features ..........................................................................................................................................263
11.2.1 External connections........................................................................................................263
11.2.2 Internal connections.........................................................................................................264
11.2.3 Inter-module communication...........................................................................................264
11.2.4 Debug mode.....................................................................................................................266
11.3 Memory map and register descriptions..........................................................................................266
11.3.1 Register descriptions........................................................................................................270
11.4 Functional description....................................................................................................................302
11.4.1 ADC channel muxing ......................................................................................................302
11.4.2 Analog channel conversion..............................................................................................306
11.4.3 Analog clock generator and conversion timings..............................................................311
11.4.4 ADC sampling and conversion timing.............................................................................312
11.4.5 Programmable analog watchdog......................................................................................313
11.4.6 Mode of operation............................................................................................................314
11.4.7 Interrupts..........................................................................................................................314
11.4.8 DMA functionality...........................................................................................................316
11.4.9 Power-down mode ...........................................................................................................316
11.4.10Auto-clock-off mode........................................................................................................317
11.4.11Self-testing.......................................................................................................................317
Chapter 12
Boot Assist Module (BAM)
12.1 Overview........................................................................................................................................327
12.2 Features ..........................................................................................................................................327
12.3 Safety aspects.................................................................................................................................327
12.4 Boot modes.....................................................................................................................................327
12.5 Memory map..................................................................................................................................328
12.6 Functional description....................................................................................................................328
12.6.1 Entering boot modes........................................................................................................328
12.6.2 Reset Configuration Halfword Source (RCHW).............................................................330
12.6.3 Single chip boot mode .....................................................................................................332
12.6.4 Boot through BAM..........................................................................................................332
12.6.5 Boot from UART—autobaud disabled ............................................................................338
12.6.6 Bootstrap with FlexCAN—autobaud disabled ................................................................339
12.6.7 Autobaud feature..............................................................................................................340
12.6.8 Interrupt ...........................................................................................................................350
Chapter 13
Clock Architecture
13.1 System clock generation.................................................................................................................351
13.2 Clock selection...............................................................................................................................357
13.2.1 System Clock Selector 0..................................................................................................357
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13.2.2 External Clock Selector ...................................................................................................357
13.2.3 Auxiliary Clock Selector 0 ..............................................................................................358
13.2.4 Auxiliary Clock Selector 1 ..............................................................................................358
13.2.5 Auxiliary Clock Selector 2 ..............................................................................................358
13.2.6 Auxiliary Clock Selector 3 ..............................................................................................359
13.2.7 Auxiliary Clock Selector 4 ..............................................................................................359
13.3 System clock dividers.....................................................................................................................359
13.3.1 SYS_CLK, Core_CLK, and Flash_CLK divider.............................................................360
13.3.2 PERI0 divider ..................................................................................................................360
13.3.3 PERI1 divider ..................................................................................................................361
13.3.4 External clock divider......................................................................................................361
13.3.5 Auxiliary clock dividers...................................................................................................361
13.4 Clock tree architecture functional safety........................................................................................362
13.4.1 Clock monitoring.............................................................................................................362
13.4.2 Clock domains and clock tree..........................................................................................362
13.4.3 Safe Mode........................................................................................................................362
13.5 Alternate module clock domains....................................................................................................363
13.5.1 FlexCAN clock domains..................................................................................................363
13.5.2 FlexRay clock domains....................................................................................................364
13.5.3 SWT clock domains.........................................................................................................364
13.5.4 Cross Triggering Unit (CTU) clock domains ..................................................................365
13.5.5 IPS bus clock sync bridge................................................................................................365
13.5.6 Peripherals behind the IPS Bus Clock Sync Bridge ........................................................366
13.6 Clock requirements in STOP and HALT mode..............................................................................366
13.7 Detailed module descriptions.........................................................................................................368
Chapter 14
Clock Generation Module (MC_CGM)
14.1 Introduction....................................................................................................................................369
14.1.1 Overview..........................................................................................................................369
14.1.2 Features............................................................................................................................370
14.2 External signal description.............................................................................................................370
14.3 Memory map and register definition..............................................................................................370
14.3.1 Register descriptions........................................................................................................376
14.4 Functional Description...................................................................................................................386
14.4.1 System Clock Generation ................................................................................................386
14.4.2 Dividers Functional Description......................................................................................391
14.4.3 Output Clock Multiplexing..............................................................................................391
14.4.4 Output Clock Division Selection.....................................................................................392
Chapter 15
Clock Monitor Unit (CMU)
15.1 Overview........................................................................................................................................393
15.2 Main features..................................................................................................................................393
15.3 Functional description....................................................................................................................393
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15.3.1 Crystal clock monitor.......................................................................................................394
15.4 Memory map and register description............................................................................................395
15.4.1 Control status register (CMU_CSR)................................................................................396
15.4.2 Frequency display register (CMU_FDR) ........................................................................397
15.4.3 High-frequency reference register A (CMU_HFREFR_A).............................................398
15.4.4 Low-frequency reference register A (CMU_LFREFR_A)..............................................398
15.4.5 Interrupt status register (CMU_ISR) ...............................................................................399
15.4.6 Measurement duration register (CMU_MDR) ................................................................400
15.5 CMU integration ............................................................................................................................400
Chapter 16
Cyclic Redundancy Checker (CRC) Unit
16.1 Introduction....................................................................................................................................403
16.2 Main features..................................................................................................................................403
16.2.1 Standard features..............................................................................................................403
16.3 Block diagram................................................................................................................................403
16.4 Signal description...........................................................................................................................403
16.5 Memory map and registers.............................................................................................................404
16.5.1 Register description .........................................................................................................404
16.6 Functional description....................................................................................................................407
16.7 Use cases and limitations ...............................................................................................................409
Chapter 17
Coherency Unit (CU)
17.1 Introduction....................................................................................................................................413
17.2 Features ..........................................................................................................................................413
17.2.1 Block diagram..................................................................................................................413
17.2.2 ACP_CU interface signals...............................................................................................416
17.3 Memory map..................................................................................................................................417
17.3.1 Register descriptions........................................................................................................422
17.4 Functional description....................................................................................................................430
17.4.1 Arbitration and routing ....................................................................................................430
17.4.2 Protocol and handshaking................................................................................................431
17.4.3 Snoop queue.....................................................................................................................432
17.4.4 Lock Step mode (LSM) considerations ...........................................................................432
17.4.5 Stop mode considerations ................................................................................................433
17.4.6 Memory synchronization control.....................................................................................433
17.5 Timing diagrams.............................................................................................................................435
Chapter 18
Cross-Triggering Unit (CTU)
18.1 Introduction....................................................................................................................................437
18.2 Block diagram................................................................................................................................437
18.3 CTU overview................................................................................................................................437
18.4 Memory map and registers description..........................................................................................438
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18.4.1 Register description .........................................................................................................442
18.5 Functional description....................................................................................................................471
18.5.1 Interaction with other peripherals....................................................................................471
18.5.2 Trigger events features.....................................................................................................473
18.5.3 Trigger Generator Sub Unit (TGS)..................................................................................473
18.5.4 TGS in Triggered Mode...................................................................................................473
18.5.5 TGS in sequential mode...................................................................................................475
18.5.6 TGS counter.....................................................................................................................476
18.5.7 Debug mode.....................................................................................................................477
18.6 Scheduler sub unit (SU) .................................................................................................................477
18.6.1 ADC commands list.........................................................................................................479
18.6.2 ADC commands list format.............................................................................................479
18.6.3 ADC results......................................................................................................................480
18.7 Reload mechanism .........................................................................................................................481
18.8 STOP mode....................................................................................................................................482
18.9 Interrupts and DMA requests.........................................................................................................482
18.9.1 DMA support...................................................................................................................482
18.9.2 CTU faults and errors ......................................................................................................482
18.9.3 CTU interrupt/DMA requests..........................................................................................483
Chapter 19
Enhanced Direct Memory Access (eDMA)
19.1 Introduction....................................................................................................................................487
19.1.1 Overview..........................................................................................................................488
19.1.2 Features............................................................................................................................488
19.2 Memory map and register description............................................................................................494
19.2.1 Register descriptions........................................................................................................498
19.3 Functional description....................................................................................................................522
19.3.1 eDMA microarchitecture.................................................................................................522
19.3.2 DMA basic data flow.......................................................................................................524
19.3.3 DMA performance...........................................................................................................527
19.4 Initialization/application information.............................................................................................530
19.4.1 DMA initialization...........................................................................................................530
19.4.2 DMA programming errors...............................................................................................531
19.4.3 DMA arbitration mode considerations ............................................................................531
19.4.4 DMA transfer...................................................................................................................533
19.4.5 TCD status .......................................................................................................................536
19.4.6 Channel linking................................................................................................................537
19.4.7 Dynamic programming....................................................................................................538
19.4.8 Hardware request release timing......................................................................................541
Chapter 20
eDMA Channel Mux (DMACHMUX)
20.1 Introduction....................................................................................................................................543
20.1.1 Overview..........................................................................................................................543
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20.1.2 Features............................................................................................................................543
20.1.3 Modes of operation..........................................................................................................544
20.2 External signal description.............................................................................................................544
20.2.1 Overview..........................................................................................................................544
20.3 Memory map and register description............................................................................................544
20.3.1 Register descriptions........................................................................................................546
20.4 DMACHMUX request source slot mapping..................................................................................547
20.5 DMACHMUX trigger inputs .........................................................................................................549
20.6 Functional description....................................................................................................................549
20.6.1 DMA channels with periodic triggering capability .........................................................549
20.6.2 DMA channels with no triggering capability ..................................................................551
20.6.3 “Always enabled” DMA sources.....................................................................................551
20.7 Initialization/application information.............................................................................................552
20.7.1 Reset.................................................................................................................................552
20.7.2 Enabling and configuring sources....................................................................................552
Chapter 21
Deserial Serial Peripheral Interface (DSPI)
21.1 Introduction....................................................................................................................................557
21.1.1 Overview..........................................................................................................................557
21.1.2 Features............................................................................................................................557
21.1.3 DSPI configurations.........................................................................................................558
21.1.4 Modes of operation..........................................................................................................559
21.2 External signal description.............................................................................................................560
21.2.1 Overview..........................................................................................................................560
21.2.2 Detailed signal description...............................................................................................561
21.3 Memory map and register description............................................................................................561
21.3.1 Memory map....................................................................................................................561
21.3.2 Register descriptions........................................................................................................563
21.4 Functional description....................................................................................................................578
21.4.1 Start and stop of DSPI transfers.......................................................................................579
21.4.2 Serial Peripheral Interface (SPI) configuration ...............................................................580
21.4.3 DSPI baud rate and clock delay generation.....................................................................582
21.4.4 Transfer formats...............................................................................................................585
21.4.5 Continuous serial communications clock ........................................................................593
21.4.6 Parity generation and check.............................................................................................595
21.4.7 Interrupts/DMA requests .................................................................................................596
21.4.8 Power- saving features.....................................................................................................597
21.5 Initialization and application information......................................................................................598
21.5.1 Managing queues.............................................................................................................598
21.5.2 Switching master and slave mode....................................................................................599
21.5.3 Baud rate settings.............................................................................................................599
21.5.4 Delay settings...................................................................................................................600
21.5.5 Calculation of FIFO pointer addresses ............................................................................601
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Chapter 22
External Bus Interface (EBI)
22.1 Introduction....................................................................................................................................603
22.1.1 Overview..........................................................................................................................603
22.1.2 Features............................................................................................................................603
22.1.3 Modes of operation..........................................................................................................603
22.2 External signal description.............................................................................................................606
22.2.1 Overview..........................................................................................................................606
22.2.2 Detailed signal descriptions.............................................................................................606
22.2.3 Signal output buffer enable logic by mode......................................................................609
22.3 Memory map and register description............................................................................................610
22.3.1 Register descriptions........................................................................................................610
22.4 Functional description....................................................................................................................618
22.4.1 EBI features .....................................................................................................................618
22.4.2 External bus operations....................................................................................................624
22.5 Initialization/application information.............................................................................................662
22.5.1 Booting from external memory........................................................................................662
22.5.2 Running with SDR (Single Data Rate) burst memories ..................................................663
22.5.3 Running with asynchronous memories............................................................................663
22.5.4 Connecting an MCU to multiple memories.....................................................................666
22.5.5 EBI operation with reduced pinout MCUs ......................................................................667
22.5.6 Summary of differences from MPC5xx...........................................................................671
Chapter 23
Error Correction Status Module (ECSM)
23.1 Introduction....................................................................................................................................673
23.2 Features ..........................................................................................................................................673
23.3 Memory map and register description............................................................................................673
23.3.1 Memory map....................................................................................................................673
23.3.2 Registers description........................................................................................................676
23.3.3 ECC registers...................................................................................................................682
Chapter 24
Enhanced Motor Control Timer (eTimer)
24.1 Introduction....................................................................................................................................697
24.1.1 Overview..........................................................................................................................697
24.1.2 Features............................................................................................................................697
24.1.3 Module block diagram.....................................................................................................698
24.1.4 Channel block diagram....................................................................................................699
24.2 External signal descriptions ...........................................................................................................700
24.2.1 TIO[5:0]—Timer Input/Outputs......................................................................................700
24.2.2 TAI[3:0]—Timer Auxiliary Inputs ..................................................................................700
24.3 Memory map and registers.............................................................................................................700
24.3.1 Module memory map.......................................................................................................701
24.3.2 Register descriptions........................................................................................................704
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24.3.3 Timer channel registers....................................................................................................705
24.3.4 Watchdog timer registers .................................................................................................718
24.3.5 Configuration registers ....................................................................................................719
24.4 Functional description....................................................................................................................721
24.4.1 General.............................................................................................................................721
24.4.2 Counting modes...............................................................................................................722
24.4.3 Other features...................................................................................................................728
24.5 Interrupts ........................................................................................................................................729
24.6 DMA...............................................................................................................................................729
24.7 eTimer initialization .......................................................................................................................730
Chapter 25
Fault Collection and Control Unit (FCCU)
25.1 Introduction....................................................................................................................................731
25.1.1 Glossary and abbreviations..............................................................................................732
25.2 Main features..................................................................................................................................732
25.3 Block diagram................................................................................................................................733
25.4 Signal description...........................................................................................................................734
25.5 Debug mode ...................................................................................................................................734
25.6 Register interface............................................................................................................................734
25.7 Memory map and register description............................................................................................734
25.7.1 FCCU Control Register (FCCU_CTRL).........................................................................736
25.7.2 FCCU CTRL Key Register (FCCU_CTRLK).................................................................739
25.7.3 FCCU Configuration Register (FCCU_CFG) .................................................................739
25.7.4 FCCU CF Configuration Register n (FCCU_CF_CFGn)................................................741
25.7.5 FCCU NCF Configuration Register 0 (FCCU_NCF_CFG0)..........................................744
25.7.6 FCCU CFS Configuration Register n (FCCU_CFS_CFGn)...........................................746
25.7.7 FCCU NCFS Configuration Register n (FCCU_NCFS_CFGn) .....................................747
25.7.8 FCCU CF Status Register n (FCCU_CFSn)....................................................................748
25.7.9 FCCU CF Key Register (FCCU_CFK) ...........................................................................750
25.7.10FCCU NCF Status Register 0 (FCCU_NCFS0)..............................................................751
25.7.11FCCU NCF Key Register (FCCU_NCFK) .....................................................................753
25.7.12FCCU NCF Enable Register 0 (FCCU_NCFE0) ............................................................753
25.7.13FCCU NCF Timeout Enable Register 0 (FCCU_NCF_TOE0).......................................754
25.7.14FCCU NCF Timeout Register (FCCU_NCF_TO) ..........................................................755
25.7.15FCCU CFG Timeout Register (FCCU_CFG_TO) ..........................................................756
25.7.16FCCU I/O Control Register (FCCU_EINOUT)..............................................................757
25.7.17FCCU Status Register (FCCU_STAT).............................................................................758
25.7.18FCCU SC Freeze Status Register (FCCU_SCFS)...........................................................759
25.7.19FCCU CF Fake Register (FCCU_CFF)...........................................................................760
25.7.20FCCU NCF Fake Register (FCCU_NCFF).....................................................................761
25.7.21FCCU IRQ Status Register (FCCU_IRQ_STAT)............................................................762
25.7.22FCCU IRQ Enable Register (FCCU_IRQ_EN) ..............................................................763
25.7.23FCCU XTMR Register (FCCU_XTMR) ........................................................................764
25.7.24FCCU MCS Register (FCCU_MCS)...............................................................................764
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25.8 Functional description....................................................................................................................765
25.8.1 Definitions .......................................................................................................................765
25.8.2 Finite State Machine (FSM) description..........................................................................766
25.8.3 Definition of critical signals ............................................................................................767
25.8.4 Self-checking capabilities................................................................................................768
25.8.5 Reset interface..................................................................................................................769
25.8.6 Fault priority scheme and nesting....................................................................................769
25.8.7 Fault recovery ..................................................................................................................770
25.8.8 FCCU fault inputs............................................................................................................775
25.8.9 Module outputs ................................................................................................................776
25.8.10WKUP/NMI interface......................................................................................................776
25.8.11STCU interface ................................................................................................................777
25.8.12NVM interface.................................................................................................................778
25.8.13FCCU_F interface............................................................................................................779
Chapter 26
Fast Ethernet Controller (FEC)
26.1 Introduction....................................................................................................................................785
26.1.1 Overview..........................................................................................................................785
26.1.2 Block diagram..................................................................................................................786
26.1.3 Features............................................................................................................................787
26.2 Modes of operation.........................................................................................................................788
26.2.1 Full and half duplex operation.........................................................................................788
26.2.2 Interface options ..............................................................................................................788
26.2.3 Address recognition options ............................................................................................789
26.2.4 Internal loopback .............................................................................................................789
26.2.5 Debug mode.....................................................................................................................789
26.3 Programming model.......................................................................................................................789
26.3.1 Top level module memory map .......................................................................................790
26.3.2 Detailed memory map (control/status registers)..............................................................790
26.3.3 MIB Block Counters Memory Map.................................................................................792
26.3.4 Registers...........................................................................................................................794
26.4 Functional description....................................................................................................................816
26.4.1 Initialization sequence .....................................................................................................816
26.4.2 User initialization (prior to asserting ECR[ETHER_EN]) ..............................................817
26.4.3 Microcontroller initialization...........................................................................................818
26.4.4 User initialization (after asserting ECR[ETHER_EN])...................................................818
26.4.5 Network interface options................................................................................................818
26.4.6 FEC frame transmission...................................................................................................819
26.4.7 FEC frame reception........................................................................................................820
26.4.8 Ethernet address recognition............................................................................................821
26.4.9 Hash algorithm.................................................................................................................823
26.4.10Full duplex flow control ..................................................................................................826
26.4.11Inter-Packet Gap (IPG) time............................................................................................827
26.4.12Collision handling............................................................................................................827
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26.4.13Internal and external loopback.........................................................................................827
26.4.14Ethernet error-handling procedure...................................................................................828
26.5 Buffer descriptors...........................................................................................................................829
26.5.1 Driver/DMA operation with buffer descriptors...............................................................829
26.5.2 Ethernet receive buffer descriptor (RxBD)......................................................................831
26.5.3 Ethernet transmit buffer descriptor (TxBD) ....................................................................833
Chapter 27
FlexCAN Module
27.1 Introduction....................................................................................................................................837
27.1.1 Overview..........................................................................................................................838
27.1.2 FlexCAN module features ...............................................................................................838
27.1.3 Modes of operation..........................................................................................................839
27.2 External signal description.............................................................................................................840
27.2.1 Overview..........................................................................................................................840
27.2.2 Signal descriptions...........................................................................................................840
27.3 Memory map and register description............................................................................................840
27.3.1 FlexCAN memory mapping.............................................................................................840
27.3.2 Message buffer structure..................................................................................................843
27.3.3 Rx FIFO structure............................................................................................................847
27.3.4 Register descriptions........................................................................................................849
27.4 Functional description....................................................................................................................867
27.4.1 Overview..........................................................................................................................867
27.4.2 Transmit process..............................................................................................................868
27.4.3 Arbitration process...........................................................................................................868
27.4.4 Receive process................................................................................................................869
27.4.5 Matching process.............................................................................................................871
27.4.6 Data coherence.................................................................................................................872
27.4.7 Rx FIFO...........................................................................................................................875
27.4.8 CAN protocol related features.........................................................................................876
27.4.9 Interrupts..........................................................................................................................882
27.4.10Bus interface ....................................................................................................................882
27.5 Initialization/application information.............................................................................................883
27.5.1 FlexCAN initialization sequence.....................................................................................883
27.5.2 FlexCAN addressing and RAM size configurations........................................................884
27.6 Programming Considerations.........................................................................................................885
Chapter 28
Motor Control Pulse Width Modulator Module (FlexPWM)
28.1 Introduction....................................................................................................................................887
28.1.1 Overview..........................................................................................................................887
28.1.2 Features............................................................................................................................887
28.1.3 Modes of operation..........................................................................................................888
28.1.4 Block diagrams ................................................................................................................889
28.2 External signal descriptions ...........................................................................................................890
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28.2.1 PWMA[n] and PWMB[n]—External PWM pair ............................................................890
28.2.2 PWMX[n]—Auxiliary PWM signal................................................................................891
28.2.3 FAULT[n]—Fault inputs..................................................................................................891
28.2.4 EXT_SYNC—External Synchronization Signal.............................................................891
28.2.5 EXT_FORCE—External Output Force Signal................................................................891
28.2.6 OUT_TRIG0[n] and OUT_TRIG1[n]—Output Triggers................................................891
28.2.7 EXT_CLK—External Clock Signal ................................................................................891
28.3 Memory map and registers.............................................................................................................891
28.3.1 FlexPWM module memory map......................................................................................891
28.3.2 Register descriptions........................................................................................................896
28.3.3 Configuration Registers...................................................................................................914
28.3.4 Fault Channel Registers...................................................................................................919
28.4 Functional description....................................................................................................................922
28.4.1 Block diagram..................................................................................................................922
28.4.2 PWM capabilities.............................................................................................................922
28.4.3 Functional details.............................................................................................................931
28.4.4 PWM generator loading...................................................................................................947
28.5 Resets .............................................................................................................................................950
28.6 Clocks.............................................................................................................................................950
28.7 Interrupts ........................................................................................................................................950
28.8 DMA...............................................................................................................................................951
Chapter 29
FlexRay Communication Controller (FLEXRAY)
29.1 Introduction....................................................................................................................................953
29.1.1 Reference .........................................................................................................................953
29.1.2 Glossary ...........................................................................................................................953
29.1.3 Color coding ....................................................................................................................954
29.1.4 Overview..........................................................................................................................954
29.1.5 Features............................................................................................................................956
29.1.6 Modes of operation..........................................................................................................957
29.2 External signal description.............................................................................................................958
29.2.1 Detailed signal descriptions.............................................................................................958
29.3 Controller host interface clocking..................................................................................................959
29.4 Protocol engine clocking................................................................................................................959
29.4.1 Oscillator clocking...........................................................................................................960
29.5 Memory map and register description............................................................................................960
29.5.1 Memory map....................................................................................................................960
29.5.2 Register descriptions........................................................................................................965
29.6 Functional description..................................................................................................................1040
29.6.1 Message buffer concept .................................................................................................1040
29.6.2 Physical message buffer.................................................................................................1041
29.6.3 Message buffer types .....................................................................................................1042
29.6.4 Flexray Memory Area Layout .......................................................................................1048
29.6.5 Physical Message Buffer Description............................................................................1051
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29.6.6 Individual message buffer functional description..........................................................1060
29.6.7 Individual Message Buffer Search.................................................................................1077
29.6.8 Individual Message Buffer Reconfiguration..................................................................1080
29.6.9 Receive FIFOs ...............................................................................................................1080
29.6.10Channel Device Modes..................................................................................................1087
29.6.11External Clock Synchronization....................................................................................1089
29.6.12Sync Frame ID and Sync Frame Deviation Tables........................................................1090
29.6.13MTS Generation ............................................................................................................1093
29.6.14Key Slot Transmission...................................................................................................1094
29.6.15Sync Frame Filtering .....................................................................................................1094
29.6.16Strobe Signal Support ....................................................................................................1095
29.6.17Timer Support ................................................................................................................1096
29.6.18Slot Status Monitoring...................................................................................................1097
29.6.19System Bus Access........................................................................................................1101
29.6.20Interrupt Support............................................................................................................1102
29.6.21Lower Bit Rate Support.................................................................................................1106
29.6.22PE Data Memory (PE DRAM)......................................................................................1107
29.6.23CHI Lookup-Table Memory (CHI LRAM)...................................................................1108
29.6.24Memory Content Error Detection..................................................................................1109
29.6.25Memory Error Injection.................................................................................................1113
29.7 Application Information...............................................................................................................1115
29.7.1 Module Configuration....................................................................................................1115
29.7.2 Initialization Sequence...................................................................................................1116
29.7.3 Memory Error Injection out of POC:default config ......................................................1118
29.7.4 Shutdown Sequence.......................................................................................................1118
29.7.5 Number of Usable Message Buffers..............................................................................1118
29.7.6 Protocol Control Command Execution..........................................................................1120
29.7.7 Message Buffer Search on Simple Message Buffer Configuration...............................1121
Chapter 30
Frequency-Modulated Phase-Locked Loop (FMPLL)
30.1 Introduction..................................................................................................................................1125
30.2 Overview......................................................................................................................................1125
30.3 Features ........................................................................................................................................1125
30.4 Memory map................................................................................................................................1126
30.5 Register descriptions....................................................................................................................1126
30.5.1 Control Register (CR)....................................................................................................1127
30.5.2 Modulation Register (MR).............................................................................................1128
30.6 Functional description..................................................................................................................1129
30.6.1 Normal mode .................................................................................................................1129
30.6.2 Progressive clock switching...........................................................................................1130
30.6.3 Normal mode with frequency modulation.....................................................................1130
30.6.4 Power down mode .........................................................................................................1131
30.7 Recommendations........................................................................................................................1131
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Chapter 31
Inter-Integrated Circuit Bus Controller Module (I
2
C)
31.1 Introduction..................................................................................................................................1133
31.1.1 Features..........................................................................................................................1133
31.1.2 Block diagram................................................................................................................1133
31.1.3 DMA interface...............................................................................................................1134
31.1.4 Modes of operation........................................................................................................1135
31.2 External signal description...........................................................................................................1136
31.3 Memory map and registers...........................................................................................................1136
31.3.1 Module memory map.....................................................................................................1136
31.3.2 Register descriptions......................................................................................................1136
31.4 Functional description..................................................................................................................1143
31.4.1 I-Bus protocol ................................................................................................................1143
31.4.2 Interrupts........................................................................................................................1147
31.5 Initialization/application information...........................................................................................1148
31.5.1 I
2
C programming examples...........................................................................................1148
31.5.2 DMA application information .......................................................................................1152
Chapter 32
Interrupt Controller (INTC)
32.1 Introduction..................................................................................................................................1157
32.1.1 Module overview...........................................................................................................1157
32.1.2 Block diagram................................................................................................................1157
32.1.3 Features..........................................................................................................................1158
32.2 Modes of operation.......................................................................................................................1159
32.2.1 Normal mode .................................................................................................................1159
32.2.2 Debug mode...................................................................................................................1160
32.3 Memory map and register description..........................................................................................1160
32.3.1 Memory map..................................................................................................................1160
32.3.2 Register information ......................................................................................................1161
32.4 Functional description..................................................................................................................1169
32.4.1 Interrupt request sources................................................................................................1169
32.4.2 Priority management......................................................................................................1170
32.4.3 Handshaking with processor..........................................................................................1172
32.5 Initialization/application information...........................................................................................1174
32.5.1 Initialization flow...........................................................................................................1174
32.5.2 Interrupt exception handler............................................................................................1174
32.5.3 ISR, RTOS, and task hierarchy......................................................................................1176
32.5.4 Order of execution .........................................................................................................1176
32.5.5 Priority ceiling protocol.................................................................................................1178
32.5.6 Selecting priorities according to request rates and deadlines ........................................1179
32.5.7 Software-settable interrupt requests...............................................................................1179
32.5.8 Lowering priority within an ISR....................................................................................1180
32.5.9 Negating an interrupt request outside of its ISR............................................................1180
32.5.10Examining LIFO contents..............................................................................................1181
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32.6 Interrupt sources...........................................................................................................................1181
Chapter 33
JTAG Controller (JTAGC)
33.1 Introduction..................................................................................................................................1197
33.1.1 Overview........................................................................................................................1197
33.1.2 Features..........................................................................................................................1197
33.1.3 Modes of operation........................................................................................................1198
33.2 External signal description...........................................................................................................1199
33.2.1 Overview........................................................................................................................1199
33.2.2 Detailed signal descriptions...........................................................................................1199
33.3 Register description......................................................................................................................1200
33.3.1 Register descriptions......................................................................................................1200
33.4 Functional description..................................................................................................................1203
33.4.1 JTAGC reset configuration ............................................................................................1203
33.4.2 IEEE 1149.1-2001 (JTAG) test access port...................................................................1203
33.4.3 TAP controller state machine.........................................................................................1204
33.4.4 Enabling debug of a censored device ............................................................................1206
33.4.5 JTAGC block instructions..............................................................................................1208
33.4.6 Boundary scan................................................................................................................1211
33.5 Initialization/application information...........................................................................................1211
Chapter 34
LIN Controller (LINFlexD)
34.1 Introduction..................................................................................................................................1213
34.2 Main features................................................................................................................................1213
34.2.1 LIN mode features .........................................................................................................1214
34.2.2 UART mode features .....................................................................................................1214
34.2.3 Debug mode...................................................................................................................1215
34.3 The LIN protocol..........................................................................................................................1215
34.3.1 Dominant and recessive logic levels..............................................................................1215
34.3.2 LIN frames.....................................................................................................................1215
34.3.3 LIN header.....................................................................................................................1216
34.3.4 Response........................................................................................................................1217
34.4 LINFlexD and software intervention ...........................................................................................1218
34.5 Summary of operating modes ......................................................................................................1218
34.6 Controller-level operating modes.................................................................................................1219
34.6.1 Initialization mode.........................................................................................................1219
34.6.2 Normal mode .................................................................................................................1220
34.6.3 Sleep (low-power) mode................................................................................................1220
34.7 LIN modes....................................................................................................................................1220
34.7.1 Master mode ..................................................................................................................1220
34.7.2 Slave mode.....................................................................................................................1222
34.7.3 Slave mode with identifier filtering...............................................................................1224
34.7.4 Slave mode with automatic resynchronization..............................................................1227
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34.8 Test modes....................................................................................................................................1229
34.8.1 Loopback mode..............................................................................................................1229
34.8.2 Self-test mode ................................................................................................................1229
34.9 UART mode .................................................................................................................................1230
34.9.1 Data frame structure.......................................................................................................1230
34.9.2 Buffer.............................................................................................................................1231
34.9.3 UART transmitter ..........................................................................................................1232
34.9.4 UART receiver...............................................................................................................1233
34.10Memory map and register description..........................................................................................1235
34.10.1LIN Control Register 1 (LINCR1).................................................................................1237
34.10.2LIN Interrupt Enable Register (LINIER).......................................................................1240
34.10.3LIN Status Register (LINSR).........................................................................................1241
34.10.4LIN Error Status Register (LINESR).............................................................................1244
34.10.5UART Mode Control Register (UARTCR) ...................................................................1245
34.10.6UART Mode Status Register (UARTSR) ......................................................................1247
34.10.7LIN Timeout Control Status Register (LINTCSR)........................................................1249
34.10.8LIN Output Compare Register (LINOCR)....................................................................1250
34.10.9LIN Timeout Control Register (LINTOCR)..................................................................1251
34.10.10LIN Fractional Baud Rate Register (LINFBRR).........................................................1251
34.10.11LIN Integer Baud Rate Register (LINIBRR)...............................................................1252
34.10.12LIN Checksum Field Register (LINCFR) ...................................................................1253
34.10.13LIN Control Register 2 (LINCR2)...............................................................................1253
34.10.14Buffer Identifier Register (BIDR)................................................................................1254
34.10.15Buffer Data Register Least Significant (BDRL) register.............................................1255
34.10.16Buffer Data Register Most Significant (BDRM) register............................................1256
34.10.17Identifier Filter Enable Register (IFER)......................................................................1257
34.10.18Identifier Filter Match Index (IFMI) register ..............................................................1257
34.10.19Identifier Filter Mode Register (IFMR).......................................................................1258
34.10.20Identifier Filter Control Registers (IFCR0–IFCR15) ..................................................1258
34.10.21Global Control Register (GCR)...................................................................................1259
34.10.22UART Preset Timeout (UARTPTO) register...............................................................1260
34.10.23UART Current Timeout (UARTCTO) register............................................................1261
34.10.24DMA Transmit Enable (DMATXE) register ...............................................................1261
34.10.25DMA Receive Enable (DMARXE) register................................................................1262
34.11 DMA interface..............................................................................................................................1263
34.11.1Master node, transmit mode...........................................................................................1263
34.11.2Master node, receive mode............................................................................................1267
34.11.3Slave node, transmit mode.............................................................................................1270
34.11.4Slave node, receive mode ..............................................................................................1273
34.11.5UART node, transmit mode...........................................................................................1276
34.11.6UART node, receive mode.............................................................................................1279
34.11.7Use cases and limitations...............................................................................................1282
34.12Functional description..................................................................................................................1283
34.12.18-bit timeout counter......................................................................................................1283
34.12.2Interrupts........................................................................................................................1284
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