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Stratix II Memory Board 2 Rev A User Guide Rev 0.1
Altera Confidential
1
Stratix II™ Memory Board 2 Rev A
User Guide
Rev 0.1
High Speed / End Applications Team
Wednesday, November 03, 2004
Stratix II Memory Board 2 Rev A User Guide Rev 0.1
Altera Confidential
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© 2004 Altera Corporation. All rights reserved. Altera, The Programmable Solutions
Company, the stylized Altera logo, specific device designations, and all other words and
logos that are identified as trademarks and/or service marks are, unless noted otherwise,
the trademarks and service marks of Altera Corporation in the U.S. and other countries.*
All other product or service names are the property of their respective holders. Altera
products are protected under numerous U.S. and foreign patents and pending
applications, maskwork rights, and copyrights. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera’s standard
warranty, but reserves the right to make changes to any products and services at any time
without notice. Altera assumes no responsibility or liability arising out of the application
or use of any information, product, or service described herein except as expressly agreed
to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for
products or services.
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Table of Contents
Stratix II™ Memory Board 2 Rev A............................................................................ 1
User Guide ....................................................................................................................... 1
Rev 1.0............................................................................................................................... 1
High Speed / End Applications Team ........................................................................... 1
1 Introduction................................................................................................................. 4
1.1 Features............................................................................................................... 5
1.2 Documentation.................................................................................................... 5
2 Getting Started ............................................................................................................ 6
2.1 Before You Begin ............................................................................................... 6
2.1.1 Development Board Contents..................................................................... 6
2.1.2 Inspect the Board ........................................................................................ 6
2.1.3 Hardware Requirements.............................................................................. 7
2.1.4 Software Requirements............................................................................... 7
2.1.5 Restore Archived Projects........................................................................... 8
2.1.6 Set Unused Pins in Your Design................................................................. 8
2.1.7 Next Steps................................................................................................... 9
2.2 Board Interfaces.................................................................................................. 9
2.3 Run the Preloaded Diagnostic Tests ................................................................. 10
2.3.1 User I/O Test............................................................................................. 11
2.3.2 Nios Stamp Features Test ......................................................................... 12
2.3.3 DDR2 SDRAM DIMM Test..................................................................... 14
2.3.4 DDR2 SDRAM Devices Test................................................................... 15
2.3.5 QDRII SRAM Device(s) Test................................................................... 16
3 Diagnostic Tests........................................................................................................ 17
3.1 Set up S2MB2 for Individual Diagnostic Tests................................................ 17
3.1.1 Set up the Board........................................................................................ 18
3.1.2 Power up Procedure .................................................................................. 20
3.1.3 Running All Tests at Once........................................................................ 20
3.1.4 User IO Test.............................................................................................. 20
3.1.5 NIOS Stamp Features Test........................................................................ 21
3.1.6 DDR2 SDRAM DIMM............................................................................. 23
3.1.7 DDR2 SDRAM Devices........................................................................... 23
3.1.8 QDRII SRAM Device(s)........................................................................... 23
3.1.9 Downloading Factory Image..................................................................... 23
3.2 Troubleshooting ................................................................................................ 24
3.3 Diagnostic Test Details..................................................................................... 25
3.3.1 User I/O & Nios Features Test.................................................................. 25
3.3.2 DDR2 SDRAM DIMM Test..................................................................... 28
3.3.3 DDR2 SDRAM Devices Test................................................................... 29
3.3.4 QDRII SRAM Device(s) Test................................................................... 29
4 MAX/MAX II Configuration Controller .................................................................. 31
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1 Introduction
This document describes the Diagnostic and Production Test processes and procedures
for revision A of the Stratix II Memory Board 2 (S2MB2). It also covers the hardware
and software requirements for the tests.
The S2MB2 is a demonstration board designed to showcase high-speed memories (DDR2
SDRAM and QDRII SRAM) with Altera’s current high end device, Stratix II, using
Altera developed Intellectual Property (IP). The main function of this board is to provide
in-house hardware verification and demonstration platforms for the Stratix II, DDR2
SDRAM DIMM, DDR2 SDRAM devices, and QDRII SRAM memory controller IP. The
S2MB2 is shown in Figure 1.
For detailed information on the S2MB2 please refer to the S2MB2 board datasheet.
Figure 1. Stratix II Memory Board 2
The development board includes the following items:
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Stratix II Memory Board 2 - The development board is used to demonstrate the Stratix
II FPGA memory interface capabilities using DDR2 SDRAM dual interface memory
module (DIMM) socket, two DDR2 SDRAM devices, and one/two QDRII SRAM
device(s).
Board Design Files – Included with the S2MB2 board are the development board’s
schematic and layout design files, which you can use as a reference to accelerate printed
circuit board (PCB) designs that incorporate the Stratix II device.
Design Examples – Included with the S2MB2 board are a variety of design examples
that are used to test the Stratix II high-speed development board. You can use these
design examples as a reference to develop your custom logic, accelerating the design,
verification, and prototyping cycle.
Demonstrations – The S2MB2 includes device programming files which can be used to
demonstrate DDR2 SDRAM DIMM interface at 267 MHz, DDR2 SDRAM device
interface at 267 MHz, and QDRII device interface at 250 MHz.
Compact Discs (CDs)—The S2MB2 includes CDs that contain the Quartus® II design
software, including a one-year evaluation license; the MegaCore® IP Library, including
OpenCore® Plus free evaluation; the Nios II embedded processor; the board design files,
demonstrations, and documentation.
1.1 Features
• DIMM socket using DDR2 SDRAM running at 267 MHz.
• Two DDR2 SDRAM devices running at 267 MHz.
• One/two QDRII SRAM device(s) running at 250 MHz.
• Two SRAM Memory devices
• One Flash Memory device
• 10/100 Ethernet media access control physical interface (MAC PHY) using an
RJ-45 connector for the cable connection.
1.2 Documentation
The following documents are included on the CD supplied with the S2MB2
Stratix II Memory Board 2 Data Sheet - Describes the specifications for the board and
explains how to use it.
Stratix II Memory Board 2 User Guide (this document) - Describes how to use the
board, including setting up the board, and running the diagnostic tests
.
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Stratix II Memory Board 2 Layout Guidelines - This document provides PCB layout
design guidelines for the board.
2 Getting Started
This section describes how to get started with the board, including describing the board
components, explaining how to set up the board, and describing how to perform the
preloaded diagnostic tests.
This section includes the following chapters:
Section 2.1. Before You Begin
Section 2.2. Board Setup
Section 3.1. Run the Preloaded Diagnostic Tests
2.1 Before You Begin
Before using the board or installing the software, be sure to check the contents and
inspect the board to verify that you received all of the items. If any of these items are
missing, contact Altera before you proceed. You should also verify that your computer
meets the software and system requirements of the board.
2.1.1 Development Board Contents
The Stratix II Memory Board 2 contains the following items:
Stratix II Memory Board 2
USB-Blaster™ download cable
Power supply
S2MB2, Stratix II Edition CD-ROM
MegaCore® IP Library CD-ROM
Nios® II CD-ROM
Quartus® II Development Software CD-ROM (version 4.1 service pack 2)
Stratix II Memory Board 2, Stratix II Edition User Guide (this document)
S2MB2, Stratix II Edition CD-ROM contains all of the supporting files and
documentation, including:
Stratix II Memory Board 2 schematic
Stratix II Memory Board 2 layout file (Allegro format)
Stratix II Memory Board 2 layout guidelines
Stratix II Memory Board 2 test designs
Stratix II Memory Board 2 example designs and demonstrations
2.1.2 Inspect the Board
Place the board on an anti-static surface and inspect it to ensure that it has not been
damaged during shipment. Verify that all components are on the board and appear intact.
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• The board can be damaged without proper anti-static handling. Therefore, anti-
static precautions, such as proper grounding, should be taken before handling the
board.
2.1.3 Hardware Requirements
• PC – A medium performance personal computer with standard features and
Windows XP installed is used as the host system for the test process. It serves as
the user interface for the test process and stores all of the software and files
required for the tests.
• Programming Device – A programming device is required to program/configure
the Altera devices on the S2MB2. A USB-Blaster with a parallel cable interface
is the standard device. The USB Blaster provides a slightly faster download
speed.
• Power supply – The S2MB2 uses an IBM ThinkPad laptop compatible power
supply as the main power source for the board. It produces a 16 volt DC output
and supplies 60W of power.
• RS232 cable – An RS232 serial cable is required for communication between the
host system and the board being tested.
• NIOS Proto1 test card w/ modified resister value – A NIOS Proto 1 test card is
used to help verify the Proto 1 interface. It must have a resistor value modified
before the card is connected to a powered up S2MB2 or the resistor will overheat
and fail. The resistor is R8. The new value needs to be approximately 4-5k Ohms.
• Ethernet connection w/cable – An Ethernet connection and cable is required to
verify the Ethernet port on the S2MB2. As the test is currently configured, the
S2MB2 attempts to use DHCP to acquire an Ethernet address.
• DDR2 SDRAM DIMM – Use a Micron 512 MByte PC4300 267 MHz DDR2
SDRAM module, Micron part number MT9HTF3272AG-53B or compatible part.
2.1.4 Software Requirements
Refer to the Stratix II Memory Board 2 Data Sheet for information on the board
components and their locations.
You should install the following software before you begin using the board.
• Quartus II 4.1 SP2 – Quartus II 4.1 SP2 internal build 208 or greater provides the
programming software used to configure the Altera devices. It is vital to use
Quartus II 4.1 SP2 internal build 208 or greater software for any MAX II
EPM1270 programming. Use of any older version may erase/corrupt the
configuration data and the silicon ID with in the MAX II device. Erasure of the
silicon ID prevents the device from ever being programmed again.
• Board Test System (BTS) code – The BTS code is a collection of TCL scripts,
batch files and compiled C programs used to automate the testing process.
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• .sof files – Several .sof and .pof files are used to configure the Altera devices on
the S2MB2 to run the tests.
• The software on the S2MB2, Stratix II Edition CDROM.
2.1.5 Restore Archived Projects
Altera provides archived Quartus II projects for the designs included in the board. Before
compiling an archived project, you must restore it. To restore a project, perform the
following steps:
1. Choose Restore Archived Project (Project menu).
2. In the Archive name box, type the path and file name of the Quartus II Archive
File (.qar) you wish to restore, or select a QAR File with Browse (...).
3. In the Destination folder box, type or select the path of the folder into which
you wish to restore the contents of the QAR File, or select a folder with Browse
(...).
4. Click Show log to view the Quartus II Archive Log File (.qarlog) for the
project you are restoring from the QAR File.
5. Click OK.
2.1.6 Set Unused Pins in Your Design
When compiling designs, Altera recommends that all unused pins act as tri-stated inputs.
To change this setting in the Quartus II software, perform the following steps:
1. Choose Device (Assignments menu).
2. On the Device page of the Settings dialog box, click Device and Pin Options.
3. In the Device & Pin Options dialog box, click the Unused Pins tab.
4. Under Reserve all unused pins, select As Inputs, tri-stated (Figure 2).
5. Click OK.
6. Click OK.
The Quartus II software default settings configure unused pins as outputs driving ground.
Board components may be damaged by having GND signals driven onto pins that drive
Vcc.
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Figure 2 Device & Pin Options Dialog Box
2.1.7 Next Steps
This user guide contains the following chapters to help you get started working with the
board:
“Board Interfaces” in section 2.2 explains how to setup and configure the Stratix II
Memory Board 2.
“Run the Preloaded Diagnostic Tests” in section 2.3 describes how to set up and run
each preloaded design and the required equipment.
“Set up S2MB2 for Individual Diagnostic Tests” in section 3.1 explains how to run the
production tests.
“Troubleshooting” in section 3.2 describes how to solve problems you may encounter
with the test designs or with setting up the board.
“Diagnostic Test Details” in section 3.3 explains each diagnostic test.
2.2 Board Interfaces
Feature Description
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1 DDR2 SDRAM DIMM Interface
2 DDR2 SDRAM Devices Interface
3 QDRII SRAM Device(s) Interface
4 10/100 Ethernet interface
5 MAX®/MAX II device
6 General purpose interface (user pushbuttons, dipswitches, LEDs, and
displays)
7 RS-232 interface
8 JTAG interface
9 Stratix II configuration settings interface
10 Clock source (crystal oscillators and clock input and output)
11 Stratix II active serial interface
12 Tektronix high-speed differential debug interface
13 Agilent high-speed differential debug interface
14 Stratix II device
15 Power connectors and circuitry
16 Flash Memory device
17 SRAM devices
Table 1 S2MB2 Interfaces
2.3 Run the Preloaded Diagnostic Tests
Each interface on the S2MB2 board has an associated diagnostic test that exercises
the interface at the supported I/O rates. Although the tests are not exhaustive, they
help you confirm that each interface runs according to its intended design. A subset of
the diagnostic tests are loaded into the Stratix II Memory Board 2’s Flash memory. If
the S2MB2 does have preloaded diagnostic tests already in Flash, then at power up
the MAX® or MAX II device checks the MPGM value and uses the Flash memory to
configure the Stratix II device with the desired configuration image. This chapter
describes how to set up and perform these preloaded diagnostic tests, including:
User I/O and Nios® Stamp
DDR2 SDRAM dual interface memory module (DIMM)
DDR2 SDRAM devices
QDRII SRAM device(s)
The following sections describe how to perform each test, including the equipment
you need to perform each test, how to set up the board, and the test procedure. Table
2 shows the switch settings you must make to load the designs on power up. If the
Flash is blank or corrupted, there are instructions on how to program the Flash in
“Downloading Factory Image”, Section 3.1.9.
For more details on these designs, refer to Section 3.3, Diagnostic Test Details.
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Diagnostic Test PageName
MPGM(2) MPGM(1)
MPGM(0)
User I/O and Nios Stamp Safe
(Note 1)
Any Any Any
DDR2 SDRAM DIMM Zero Closed Closed Closed
DDR2 SDRAM Devices One Closed Closed Open
QDRII SRAM Device(s) Two Closed Open Closed
Open – logic 1; Closed – logic 0;
Note 1. Press the SAFEn pushbutton (S2) to load this configuration.
Table 2. Factory-Default Utility DIP Switch (S1) Settings
2.3.1 User I/O Test
The User I/O and Nios Stamp functions are tested using the board test system (BTS)
graphical user interface (GUI). For diagrams of the BTS GUI, and details on this test
refer to section 3.3 Diagnostic Test Details.
2.3.1.1 Required Hardware & Software
In addition to your board, you need the following hardware and software to perform this
test.
Quartus II 4.1 SP2 or later software
Board test system (BTS) files
RS-232 cable
2.3.1.2 Test Setup
Perform the following steps to set up the user I/O test.
1. Move the power switch to the OFF position.
2. Connect one end of the RS-232 cable to port A (J12) of the board, and the other end of
the cable to the COM1 port of the computer.
3. Move the power switch to the ON position.
4. Open the BTS directory in the Production Test files provided with the board, and run
the BTS GUI batch file (bts_test.bat). This file downloads the required Nios code to the
FPGA, and launches the BTS GUI. Wait for the BTS GUI to open. If there is an error in
the setup, the BTS GUI will not start. Please make sure that only one bts_test.bat is
running at a time.
2.3.1.3 Run the User I/O Test
Perform the following steps to execute the User I/O test.
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Figure 5 through Figure 7, show the applicable GUI pages.
1. Choose Open Port > RS232 Com1 (BTS menu) to open the COM1 port.
2. Click the UserIO tab.
3. Click the Enable Polling button.
4. Test the seven-segment display.
a. Use your mouse to slowly move the slider.
b. Verify that the digits displayed on the board’s seven-segment display match the
digits shown in the GUI.
5. Test the User LEDs.
a. Click the LEDs On button. Verify that the User LEDs on the board turn on.
b. Click the LEDs Off button. Verify that the User LEDs on the board turn off.
c. Turn on the LED check boxes one at a time. Verify that the corresponding User
LED on the board turns on.
d. Turn off the LED check boxes one at a time. Verify that the corresponding
User LED on the board turns off.
6. Verify that the DIP switches are operational.
a. Set all of the dipswitches to the open position. Observe the corresponding
switch indicator in the GUI.
b. Set all of the dipswitches to the closed position. Observe the corresponding
switch indicator in the GUI.
7. Test the User pushbuttons.
a. Press the S5, S6, and S7 (PB0, PB1, PB2) pushbuttons. Observe the status in
the GUI.
• Do not press the S3 (SYS_RESETn) or S8 (PB3) pushbuttons as these will
reset the system. If you accidentally press either of these buttons, you will
need to exit the GUI and start over.
2.3.2 Nios Stamp Features Test
The Nios Stamp function, like the user I/O function, is tested using the BTS GUI. For
diagrams of the BTS GUI, and details on this test refer to section 3.3 Diagnostic Test
Details.
The Nios Stamp test tests the on-board SRAM, Flash memory, and Ethernet port. Please
note that the Flash memory needs to be re-imaged if the flash is tested.
Refer to section 3.1.9, Downloading Factory Image for instructions on programming the
Flash.
2.3.2.1 Required Hardware & Software
In addition to your board, you need the following hardware and software to perform this
test.
Quartus II software v. 4.1 service pack 2
Board test system (BTS) files
RS-232 cable
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10/100-Mbit Ethernet cable
2.3.2.2 Test Setup
Perform the following steps to set up the Nios Stamp test.
1. Move the power switch to the OFF position.
2. Connect one end of the RS-232 cable to port A (J12) of the board, and the other end of
the cable to the COM1 port of the computer.
3. Connect one end of the 10/100-Mbit Ethernet cable to the RJ-45 connector (J21), and
the other end of the cable to a network with an available dynamic host configuration
protocol (DHCP) server.
4. Move the power switch to the ON position.
5. Open the BTS directory in the Production Test files provided with the board, and run
the BTS GUI batch file (bts_test.bat). This file downloads the required Nios code to the
FPGA, and launches the BTS GUI. Wait for the BTS GUI to open. If there is an error in
the setup, the BTS GUI will not start. Please make sure that only one bts_test.bat is
running at a time.
2.3.2.3 Run the Nios Stamp Test
Perform the following steps to execute the Nios Stamp test.
1. Choose Open Port > RS232 Com1 (BTS menu) to open the COM1 port.
2. Click the Nios Stamp tab.
3. Click the Start Tests button under SRAM. This runs the “Walking Ones on Address”
and “Walking Ones on Data” tests.
4. Verify that the tests complete without errors. The test results appear in the Nios Stamp
Msgs window, and should read as follows.
Starting Test
Walking Ones on Data
Walking Ones on Address
There were 0 error(s).
Test Complete
5. Click the Start Tests button under Flash. This runs the “Walking Ones on Address”, the
“Walking Ones on Data”, and the “Erase Flash” tests. This test may take 3 to 4 minutes
to complete.
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6. Verify that the tests complete without errors. The test results appear in the Nios Stamp
Msgs window, and should read as follows.
Starting Test
Walking Ones on Data
Starting Flash Erase of sector offset 0
Finished Flash Erase
Walking Ones on Address
Starting Flash Erase
Test Complete
7. Click the Get DHCP address button under Ethernet. If the board is connected to a live
network this test should return an internet protocol (IP) address. The test results appear in
the Nios Stamp Msgs window, and should read as follows:
Getting DHCP Address
DHCP Address obtained. Address is 137.57.185.70.
Note: The IP address returned may be different from the example above.
8. Click the Blink Ethernet LEDs button.
9. Verify that the LEDs on the Ethernet connector blink several times.
10. If the Stratix II high-speed development board is not connected to a live network, the
Ethernet tests cannot work correctly. In this case, look for the following message in the
BTS message window in the bottom of the GUI. It takes about 1 minute before you get
the first timing out message.
[lan91c111] nr_lan91c111_reset: chip id = LAN91C111
[lan91c111] r_lan91c111_detect_phy: found lan83C183 (lan91C111
internal)
[lan91c111] r_lan91c111_init_phy: phy negotiation timed out
[lan91c111] r_lan91c111_init_phy: 10bt
[lan91c111] r_lan91c111_init_phy: half duplex
[dhcp] 1 timing out
[dhcp] 2 timing out…
This finishes the NIOS Stamp section of the tests. This finishes the NIOS Stamp section
of the tests. Exit the GUI.
2.3.3 DDR2 SDRAM DIMM Test
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The DDR2 SDRAM DIMM test uses a hardware state machine included in the DDR2
MegaCore® function, and a DDR2 SDRAM DIMM to test the DDR2 interface. For
further details on this test, refer to “DDR2 SDRAM DIMM Test” in section 3.3.2.
2.3.3.1 Required Hardware
In addition to your board, you need the DDR2 SDRAM DIMM that is included with the
Stratix II high-speed board to perform this test.
1. The board has been tested with the following two DDR2 SDRAM DIMM modules,
and is expected to be compatible with other industry standard DDR2 SDRAM DIMM
modules.
• Micron Technology MT9HTF3272AG-53B
2.3.3.2 Test Setup
Perform the following steps to set up the DDR2 SDRAM DIMM test.
1. Move the power switch to the OFF position.
2. Insert the DDR2 DIMM into J15.
3. Set the switches (MPGM pins) on S1 to the correct values for this test, as shown in
Table 2.
4. Move the power switch to the ON position.
5. Press the SYS_RESETn (S3) pushbutton to reload the FPGA.
6. Confirm that the Stratix II device has finished configuration (the CONF_DONEn LED
(D12) illuminates). The Error LED (D17) will illuminate if there is an error.
2.3.3.3 Run the DDR2 SDRAM DIMM Test
Perform the following steps to execute the DDR2 SDRAM DIMM test.
1. Press the PB3 (S8) pushbutton to reset and run the design.
2. Confirm that LED0 and LED1 are on, and that LED4 and LED5 are blinking. If so, the
test is a success. LED0 turns on to indicate that the test is not failing. LED1 turns on to
indicate that the test is complete.
2.3.4 DDR2 SDRAM Devices Test
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The DDR2 SDRAM Devices test uses a hardware state machine included in the DDR2
MegaCore® function, and a DDR2 SDRAM Devices to test the DDR2 interface. For
further details on this test, refer to “DDR2 SDRAM Devices Test” in section 3.3.3.
2.3.4.1 Required Hardware
1. The board has been tested with the following DDR2 SDRAM devices, and is expected
to be compatible with other industry standard DDR2 SDRAM devices.
• Micron Technology MT47H16M16BG - 37B
• Samsung Semiconductor K4H561638F-TCCC
2.3.4.2 Test Setup
Perform the following steps to set up the DDR2 SDRAM Devices test.
1. Move the power switch to the OFF position.
2. Set the switches (MPGM pins) on S1 to the correct values for this test, as shown in
Table 2.
3. Move the power switch to the ON position.
4. Press the SYS_RESETn (S3) pushbutton to reload the FPGA.
5. Confirm that the Stratix II device has finished configuration (the CONF_DONEn LED
(D12) illuminates). The Error LED (D17) will illuminate if there is an error.
2.3.4.3 Run the DDR2 SDRAM Devices Test
Perform the following steps to execute the DDR2 SDRAM Devices test.
1. Press the PB3 (S8) pushbutton to reset and run the design.
2. Confirm that LED0 and LED1 are on, and that LED4 and LED5 are blinking. If so, the
test is a success. LED0 turns on to indicate that the test is not failing. LED1 turns on to
indicate that the test is complete.
2.3.5 QDRII SRAM Device(s) Test
For further details on this test, refer to “QDRII SRAM Device(s) Test” in section 3.3.4.
2.3.5.1 Test Setup
Perform the following steps to set up the QDRII SRAM Device(s) test.
1. Move the power switch to the OFF position.
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2. Set the switches (MPGM pins) on S1 to the correct values for this test, as shown in
Table 2.
3. Move the power switch to the ON position.
4. Press the SYS_RESETn (S3) pushbutton to reload the FPGA.
5. Confirm that the Stratix II device has finished configuration (the CONF_DONEn LED
(D12) illuminates). The Error LED (D17) will illuminate if there is an error.
2.3.5.2 Run the QDRII SRAM Device(s) Test
Perform the following steps to execute the QDRII SRAM Device(s) test.
1. Press the PB3 (S8) pushbutton to reset and run the design.
2. Confirm that LED0 and LED1 are on, and that LED4 and LED5 are blinking. If so, the
test is a success. LED0 turns on to indicate that the test is not failing. LED1 turns on to
indicate that the test is complete.
3 Diagnostic Tests
The diagnostic tests that follow are for execution of the individual batch files using
the pc to load the files through the JTAG port onto the Stratix II.
The User IO and NIOS stamp functions are exercised using a prototype of the Board
Test System (BTS). This design is the “safe” image that is loaded by pressing the
SAFE button (S2). This loads a NIOS based system design that will communicate
with the host using a RS232 link. The user interface is TCL based. The GUI has
several “pages” for the various features that are tested.
The memory tests are hardware based at this point and are stored as pages in the on-
board flash memory. These are loaded by setting the MPGM DIP switch settings
then pressing SYS_RESETn pushbutton (S3). The memory tests consist of a state
machine that writes PRBS data to the memory device at max speed then reads back
the data and compares it to an expected value. If an error is detected, LED0 (D26)
will turn off indicating a failure. The data is written to the full address range of the
device before it is read back. Each time the full write then read cycle is completed, it
is considered one test. The designs keep track of when the test has completed. Once
completed LED1 (D25) lights up. The DDR2 designs run a infinite number of times
and will not stop unless board is shut down or another memory test is run.
3.1 Set up S2MB2 for Individual Diagnostic Tests
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3.1.1 Set up the Board
S2MB2 requires a number of jumpers, switch settings, and other hardware setup
before testing should begin. See Figure 3 for the location of the switches and
jumpers. See Figure 4 for the location of cables and Proto1 test card. This work
should be performed before applying power.
Set up the DIP switches as shown in Table 3. Set up the S2MB2 jumpers as
shown in Table 5.
Table 3. DIP Switch Settings
DIP Switch Name Setting
S1 – 8 MSEL3 Open
S1 – 7 MSEL2 Closed
S1 – 6 MSEL1 Open
S1 – 5 MSEL0 Open
S1 – 4 RU_N_LU Open
S1 – 3 MPGM2 Closed
S1 – 2 MPGM1 Closed
S1 – 1 MPGM0 Closed
S4 – 1 to 8 USER DIP 0 -7 Closed
Open – logic 1; Closed – logic 0;
Table 4. Other Switch Settings
SW1 POWER OFF
Table 5. Jumper Settings
J10 p1-p2
J11 p1-p2
J14 p1-p2
J16 p1-p2
J26 p1-p2
J27 p1-p2
J28 p1-p2
J34 p1-p2
J36 p1-p2
J39 p1-p2
J40 p1-p3, p2-p4
J41 p1-p2
J46 p2-p3 (for 1.8V)
J47 p1-p2 (for 50ohm)
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Figure 3. S2MB2 Board
• NIOS Proto1 test card w/ modified resister value – A NIOS Proto1 test card is
used to help verify the Proto 1 interface. It must have a resistor value modified
before the card is connected to a powered up S2MB2 or the resistor will overheat
and fail. The resistor is R8. The new value needs to be approximately 4-5k Ohms.
• DDR2 DIMM – Insert the DDR2 DIMM carefully if needed. Try not to flex the
board if possible.
• RS232 Serial Cable – Connect one end of the serial cable to the COM 1 port on
the PC and the other to the upper RS232 connector (RS232 A).
• USB Blaster cable - Connect one end of the USB cable to a USB port on the PC
and the other end to the USB port interface of the USB Blaster cable. Connect the
other end of the USB Blaster cable to the JTAG connector on the S2MB2.
• Ethernet cable – Connect one end of the Ethernet cable to an active Ethernet port,
and the other end to the RJ45 connector on the S2MB2.
SW1
S1
J40, J36
J39, J41
J16, J14
J10, J11
J26, J27
J28
J34
J46, J47
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Figure 4. S2MB2 with Cables
3.1.2 Power up Procedure
Insert the power connector into the socket. A red LED (D8) on the Proto1 test card
should come on. This indicates that power is available to the board.
Move the power switch to the ON position. A bright blue LED (D18) next to the
switch SW1 should light up indicating power being applied to the onboard regulators.
Several LEDs on the S2MB2 and LEDs D1-D5 and D8 on the Proto 1 test card
should come on.
3.1.3 Running All Tests at Once
All of the individual diagnostic tests can be run by executing one file, the
“all_tests_max2.bat.” This .bat file essentially calls each test sequentially.
Press SYS_RESETn (S3) once the all_tests_max2.bat has been executed. After each
test is run, place the board in SAFE mode by pushbutton S2. This sets up the S2MB2
so that the next test file will be executed properly.
3.1.4 User IO Test
Ethernet
JTAG
Power
RS
-
232
Proto1 Card
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