Altera Nios Ethernet Reference guide

Altera
Brand
Altera
Model
Nios Ethernet
Category
Networking
Type
Reference guide
Reference Manual, Cyclone Edition
Nios Development Board
101 Innovation Drive
San Jose, CA 95134
(408) 544-7000
www.altera.com
Document Version: 1.3
Document Date: January 2004
ii Altera Corporation
MNL-NIOSCYCBD-1.3
Copyright Nios Development Board, Cyclone Edition Reference Manual
Copyright © 2004 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo,
specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless
noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or
service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents
and pending applications, mask work rights, and copyrights. Altera warrants performance of its semiconductor
products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make
changes to any products and services at any time without notice. Altera assumes no responsibility or liability
arising out of the application or use of any information, product, or service described herein except as expressly
agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
Altera Corporation iii
About this Manual
This manual provides component details about the Nios development
board, Cyclone edition.
Table 1 shows the reference manual revision history.
How to Find
Information
■ The Adobe Acrobat Find feature allows you to search the contents of
a PDF file. Click the binoculars toolbar icon to open the Find dialog
box.
■ Bookmarks serve as an additional table of contents.
■ Thumbnail icons, which provide miniature previews of each page,
provide a link to the pages.
■ Numerous links, shown in green text, allow you to jump to related
information.
Table 1. Reference Manual Revision History
Date Description
January 2004 Pin table corrections.
July 2003 Reflects new directory structure for SOPC Builder 3.0 and
Nios Development Kit version 3.1.
May 2003 Minor revisions and edits.
March 2003 First publication of a reference manual. This manual is
Cyclone-device specific.
iv Altera Corporation
About this Manual Nios Development Board, Cyclone Edition Reference Manual
How to Contact
Altera
For the most up-to-date information about Altera products, go to the
Altera world-wide web site at http://www.altera.com.
For technical support on this product, go to
http://www.altera.com/mysupport. For additional information about
Altera products, consult the sources shown in Table 2.
Note:
(1) You can also contact your local Altera sales office or sales representative.
Table 2. How to Contact Altera
Information Type USA & Canada All Other Locations
Product literature http://www.altera.com http://www.altera.com
Altera literature services lit_re[email protected]
(1)
lit_req@altera.com
(1)
Non-technical customer
service
(800) 767-3753 (408) 544-7000
(7:30 a.m. to 5:30 p.m.
Pacific Time)
Technical support (800) 800-EPLD (3753)
(7:30 a.m. to 5:30 p.m.
Pacific Time)
(408) 544-7000
(1)
(7:30 a.m. to 5:30 p.m.
Pacific Time)
http://www.altera.com/mysupport/ http://www.altera.com/mysupport/
FTP site ftp.altera.com ftp.altera.com
Altera Corporation v
Nios Development Board, Cyclone Edition Reference Manual About this Manual
Typographic
Conventions
This manual uses the typographic conventions shown in Table 3.
Table 3. Conventions
Visual Cue Meaning
Bold Type with Initial
Capital Letters
Command names, dialog box titles, checkbox options, and dialog box options are
shown in bold, initial capital letters. Example: Save As dialog box.
bold type External timing parameters, directory names, project names, disk drive names,
filenames, filename extensions, and software utility names are shown in bold type.
Examples: f
MAX
, \QuartusII directory, d: drive, chiptrip.gdf file.
Bold italic type
Book titles are shown in bold italic type with initial capital letters. Example:
1999 Device Data Book
.
Italic Type with Initial
Capital Letters
Document titles are shown in italic type with initial capital letters. Example:
AN 75
(High-Speed Board Design).
Italic type
Internal timing parameters and variables are shown in italic type. Examples:
t
PIA
,
n
+ 1.
Variable names are enclosed in angle brackets (< >) and shown in italic type. Example:
<
file name
>, <
project name
>.pof file.
Initial Capital Letters Keyboard keys and menu names are shown with initial capital letters. Examples:
Delete key, the Options menu.
“Subheading Title” References to sections within a document and titles of Quartus II Help topics are
shown in quotation marks. Example: “Configuring a FLEX 10K or FLEX 8000 Device
with the BitBlaster
™
Download Cable.”
Courier type Signal and port names are shown in lowercase Courier type. Examples: data1, tdi,
input. Active-low signals are denoted by suffix n, e.g., resetn.
Anything that must be typed exactly as it appears is shown in Courier type. For
example: c:\quartusII\qdesigns\tutorial\chiptrip.gdf. Also, sections
of an actual file, such as a Report File, references to parts of files (e.g., the AHDL
keyword SUBDESIGN), as well as logic function names (e.g., TRI) are shown in
Courier.
1., 2., 3., and a., b., c.,... Numbered steps are used in a list of items when the sequence of the items is
important, such as the steps listed in a procedure.
■
Bullets are used in a list of items when the sequence of the items is not important.
v The checkmark indicates a procedure that consists of one step only.
1 The hand points to information that requires special attention.
r The angled arrow indicates you should press the Enter key.
f The feet direct you to more information on a particular topic.
Altera Corporation vii
About this Manual ...................................................................................................................................... iii
How to Find Information.............................................................................................................. iii
How to Contact Altera .................................................................................................................. iv
Typographic Conventions .............................................................................................................. v
Board Components .......................................................................................................................................9
Features ............................................................................................................................................. 9
General Description......................................................................................................................... 9
Default Reference Design ....................................................................................................... 9
Restoring the Default Reference Design to the Board ...................................................... 10
Block Diagram........................................................................................................................ 11
Nios Development Board Components...................................................................................... 12
The Cyclone EP1C20 Device ........................................................................................................ 13
Flash Memory Device.................................................................................................................... 13
Compact Flash Connector............................................................................................................. 14
SDRAM Device............................................................................................................................... 16
Dual SRAM Devices ...................................................................................................................... 18
Ethernet MAC/PHY...................................................................................................................... 19
Expansion Prototype Connector (PROTO1) .............................................................................. 19
Expansion Prototype Connector (PROTO2) .............................................................................. 21
Mictor Connector ........................................................................................................................... 23
Serial Port Connectors................................................................................................................... 25
Dual 7-Segment Display ............................................................................................................... 26
Push-Button Switches.................................................................................................................... 26
Individual LEDs............................................................................................................................. 27
Serial Configuration Device (EPCS4).......................................................................................... 27
Serial Flash Connector................................................................................................................... 27
Configuration Controller Device (EPM7128AE) ....................................................................... 28
Reset Distribution .................................................................................................................. 28
Starting Configuration .......................................................................................................... 28
Cyclone Configuration.......................................................................................................... 28
Configuration Data................................................................................................................ 29
Safe and User Configurations .............................................................................................. 30
Using Conventional Flash Memory ............................................................................ 30
The Configuration-Status LEDs........................................................................................... 33
Configuration and Reset Buttons ........................................................................................ 33
SW8 – CPU Reset ........................................................................................................... 34
SW9 – Force Safe ............................................................................................................ 34
SW10 – Reset, Config..................................................................................................... 34
Table of Contents
viii Altera Corporation
Table of Contents Nios Development Board Reference Manual, Cyclone Edition
Power-Supply Circuitry................................................................................................................ 35
Clock Circuitry ............................................................................................................................... 35
JTAG Connections ......................................................................................................................... 36
JTAG to Cyclone Device (J24) .............................................................................................. 36
JTAG to MAX Device (J5) ..................................................................................................... 38
Appendix A: Shared Bus Table .............................................................................................................39
Appendix B: Restore the Factory Configuration ...............................................................................43
Configuring the Cyclone Device.................................................................................................. 43
Reprogramming the Flash Memory............................................................................................ 44
Appendix C: Board Ethernet Connection ............................................................................................45
Connecting the Ethernet Cable ............................................................................................ 45
Connecting the LCD Display ............................................................................................... 46
Obtaining an IP address: DHCP.......................................................................................... 46
IP Addresses for Point–to–Point Connections........................................................... 47
IP Addresses for LAN Connections ............................................................................ 48
Browsing your Board ............................................................................................................ 48
Index ................................................................................................................................................................49
Altera Corporation 9
Features
■ A Cyclone
TM
EP1C20F400C7device
■ 8 Mbytes of flash memory
■ 1 Mbyte of static RAM
■ 16 Mbytes of SDRAM
■ On board logic for configuring the Cyclone device from flash
memory
■ EPCS4 serial configuration device
■ On-board Ethernet MAC/PHY device
■ Two 5-V-tolerant expansion/prototype headers each with access to
41 Cyclone user I/O pins
■ CompactFlash
TM
connector header for Type I Compact Flash (CF)
cards
■ Mictor connector for hardware and software debug
■ Two RS-232 DB9 serial ports
■ Four push-button switches connected to Cyclone user I/O pins
■ Eight LEDs connected to Straix user I/O pins
■ Dual 7-segment LED display
■ JTAG connectors to Altera devices via Altera download cables
■ 50 MHz Oscillator and zero-skew clock distribution circuitry
■ Power-on reset circuitry
General
Description
The Nios Development Board, Cyclone Edition, provides a hardware
platform for developing embedded systems based on Altera Cyclone
devices. The Nios development board features a Cyclone EP1C20F400C7
device with 20,060 logic elements (LEs) and 294 Kbits of on-chip memory.
The Nios development board comes pre-programmed with a 32-bit Nios
processor reference design. Hardware designers can use the reference
design as an example of how to use the features of the Nios development
board. Software designers can use the pre-programmed Nios processor
design on the board to begin prototyping software immediately.
Default Reference Design
When power is applied to the board, the on-board configuration logic
configures the Cyclone FPGA using hardware configuration data stored
in flash. When the device is configured, the Nios processor design in the
FPGA wakes up and begins executing boot code from flash memory.
Board Components
10 Altera Corporation
Board Components Nios Development Board Reference Manual, Cyclone Edition
The default reference design provides facilities to download new, user-
defined software and hardware configuration data to the board from a
host computer. Download methods include a serial cable, a JTAG
download cable, or an Ethernet cable. The GERMS monitor, an Altera-
provided monitor program for the Nios processor, is running on the
Console RS-232 serial port (J19). Simultaneously, a web server program is
running via the ethernet connection.
1 The Ethernet port provides a very fast and easy method to
download hardware and software images to the board via a web
browser on your host computer. For instructions on
communicating with your Nios development board via
Ethernet, see “Appendix C: Board Ethernet Connection” on
page 45.
f
See the Nios Development Kit, Cyclone Edition Getting Started User Guide for
instructions on setting up the Nios development board. See the Nios
Hardware Development Tutorial for instructions on using this pre-loaded
reference design.
Restoring the Default Reference Design to the Board
In the course of development, you may overwrite or erase the flash
memory space containing the default reference design. Altera provides
the flash image for the default reference design, so that you can always
return the board to its default state. These default reference files are
located in the Nios development kit examples directory.
See “Appendix B: Restore the Factory Configuration” on page 43 for more
information.
Altera Corporation 11
Nios Development Board Reference Manual, Cyclone Edition Board Components
Block Diagram
Figure 1 shows a block diagram of the board.
Figure 1. Nios Development Board, Cyclone Edition Block Diagram
16
16 Mbyte SDRAM
Cyclone
EP1C20
Device
JTAG Connector
RS-232
50MHz Oscillator
Proto 1 Expansion
Prototype Header
Dual Seven-Segment Display
27
8 Mbyte Flash Memory
Configuration
Controller
5.0 V Regulators
Vccint (1.5 V)
Vccio (3.3-V)
Mictor Connector
8
Push-button
Switches [4]
4
Proto 2 Expansion
Prototype Header
RS-232
41
User LEDs [8]
1 Mbyte SRAM
Ethernet
MAC/PHY
RJ45
Connector
Compact Flash
Serial Configuration
Device
12 Altera Corporation
Board Components Nios Development Board Reference Manual, Cyclone Edition
Nios
Development
Board
Components
This section contains a brief overview of important components on the
Nios development board (see Figure 2). Links to the component
manufacturers are included when available.
A complete set of schematics, a physical layout database, and GERBER
files for the Nios development board are installed in the documents
directory for the Nios development kit.
Figure 2. Nios Development Board Components
Altera Corporation 13
Nios Development Board Reference Manual, Cyclone Edition Board Components
The Cyclone
EP1C20 Device
U60 is a Cyclone EP1C20F400C7 device in a 400-pin FineLine BGA
®
package. Table 4 lists the Cyclone device features.
The development board provides two separate methods for configuring
the Cyclone device:
1. Using the Quartus II software running on a host computer, a
designer configures the device directly via an Altera download cable
connected to the Cyclone JTAG header (J24).
2. When power is applied to the board, a configuration controller
device (U3) attempts to configure the Cyclone device with hardware
configuration data stored in flash memory. For more information on
the configuration controller, see “Configuration Controller Device
(EPM7128AE)” on page 28.
f
See the Altera Cyclone literature page for Cyclone-related documentation
at www.altera.com/literature/lit-cyc.html including a Cyclone EP1C20
pinout document.
Flash Memory
Device
U5 is an 8 Mbyte AMD AM29LV065D flash memory device connected to
the Cyclone device and can be used for two purposes:
1. A Nios embedded processor implemented on the Cyclone device can
use the flash memory as general-purpose readable memory and non-
volatile storage.
2. The flash memory can hold Cyclone configuration data that is used
by the configuration controller to load the Cyclone device at power-
up. See “Configuration Controller Device (EPM7128AE)” on
page 28. for related information.
Table 4. Cyclone EP1C20 Device Features
Logic Elements 20,060
M4K RAM blocks (128 X 36 bits) 64
Total RAM bits 294,912
PLLs 2
Maximum user I/O pins 301
14 Altera Corporation
Board Components Nios Development Board Reference Manual, Cyclone Edition
Hardware configuration data that implements the Nios reference design
is pre-stored in this flash memory. The pre-loaded Nios reference design,
once loaded, can identify the 8 Mbyte flash memory in its address space
and includes monitor software that can download files (either new
Cyclone configuration data, Nios embedded processor software, or both)
into flash memory. The Nios embedded processor software includes
subroutines for writing and erasing this specific type of AMD flash
memory.
The flash memory device shares address and data connections with the
SRAM chips and the Ethernet MAC/PHY chip. For shared bus
information, see“Appendix A: Shared Bus Table” on page 39.
f
See www.amd.com for detailed information about the flash memory
device.
Compact Flash
Connector
The compact flash connector (CON3) enables hardware designs to access
a compact flash card (see Figure 3). The following two access modes are
supported:
■ ATA (hot swappable mode)
■ IDE (IDE hard disk mode)
Figure 3. Compact Flash Connector
The IDE connection mode includes a power MOSFET which controls
power to the compact flash card. This MOSFET is controllable through an
IO pin on the Cyclone device.
1 The compact flash connector shares several Cyclone I/O pins
with expansion prototype connector header (PROTO1), see
“Expansion Prototype Connector (PROTO1)” on page 19 for
PROTO1 details.
Altera Corporation 15
Nios Development Board Reference Manual, Cyclone Edition Board Components
Table 5 below provides compact flash pin out details
Table 5. Compact Flash (CON3) Pin Table (Part 1 of 2)
Cyclone Device
Pin (U60)
Compact Flash Pin
(CON3)
Compact Flash Function
GND 1 GND
F18 2 D03
E17 3 D04
D17 4 D05
D18 5 D06
C18 6 D07
H20 7 -CE
J15 8 A10
D13 9 -OE
J20 10 A09
H14 11 A08
J14 12 A07
VCC 13 VCC
J17 14 A06
J18 15 A05
K15 16 A04
W18 17 A03
H19 18 A02
H18 19 A01
H17 20 A00
F20 21 D00
F15 22 D01
E19 23 D02
H16 24 WP
GND 25 -CD2
B13 26 -CD1
F17 27 D11
E18 28 D12
F16 29 D13
F19 30 D14
G16 31 D15
U19 32 -CE2
GND 33 -VS1
G19 34 -OIORD
16 Altera Corporation
Board Components Nios Development Board Reference Manual, Cyclone Edition
f
See www.molex.com for more compact flash connector (CON3)
information. See www.compactflash.org for more information on the
compact flash connector.
SDRAM Device
The SDRAM device (U57) is a Micron MT48LC4M32B2 chip with PC100
functionality and self refresh mode. The SDRAM is fully synchronous
with all signals registered on the positive edge of the system clock (clk).
The SDRAM device pins are connected to the Cyclone device (see Table 6).
An SDRAM controller peripheral is included with the Nios development
kit, allowing a Nios processor to view the SDRAM device as a large,
linearly addressable memory.
G20 35 -IOWR
V18 36 -WE
G17 37 RDY/BSY
VCC 38 VCC
GND 39 -CSEL
NC 40 -VS2
RESET_n 41 RESET
G14 42 -WAIT
V19 43 -INPACK
U20 44 -REG
J16 45 BVD2
J19 46 BVD1
C19 47 D081
D19 48 D091
D20 49 D101
GND 50 GND
Table 5. Compact Flash (CON3) Pin Table (Part 2 of 2)
Cyclone Device
Pin (U60)
Compact Flash Pin
(CON3)
Compact Flash Function
Table 6. SDRAM (U57) Pin Table (Part 1 of 3)
Pin Name Pin Number Connects to Cyclone Pin
A0 25 M2
A1 26 M1
A2 27 M6
A3 60 M4
Altera Corporation 17
Nios Development Board Reference Manual, Cyclone Edition Board Components
A4 61 J8
A5 62 J7
A6 63 J6
A7 64 J5
A8 65 J4
A9 66 J3
A10 24 H6
A11 21 H5
BA0 22 H7
BA1 23 H1
DQ0 2 M5
DQ1 4 M3
DQ2 5 M7
DQ3 7 N6
DQ4 8 N1
DQ5 10 N2
DQ6 11 N4
DQ7 13 N3
DQ8 74 N5
DQ9 76 N7
DQ10 77 P7
DQ11 79 P2
DQ12 80 P1
DQ13 82 P6
DQ14 83 P5
DQ15 85 P3
DQ16 31 P4
DQ17 33 R1
DQ18 34 R2
DQ19 36 R6
DQ20 37 R5
DQ21 39 R3
DQ22 40 R4
DQ23 42 T4
DQ24 45 T2
DQ25 47 T3
DQ26 48 U1
Table 6. SDRAM (U57) Pin Table (Part 2 of 3)
Pin Name Pin Number Connects to Cyclone Pin
18 Altera Corporation
Board Components Nios Development Board Reference Manual, Cyclone Edition
f
See www.micron.com for detailed SDRAM information.
Dual SRAM
Devices
U35 and U36 are two (512 Kbyte x 16-bit) asynchronous SRAM devices.
They are connected to the Cyclone device so they can be used by a Nios
embedded processor as general-purpose memory. The two 16-bit devices
can be used in parallel to implement a 32-bit wide memory subsystem.
The pre-loaded Nios reference design identifies these SRAM devices in its
address space as a contiguous 1Mbyte, 32-bit-wide, zero-wait-state main
memory.
The SRAM devices share address and data connections with the flash
memory and the Ethernet MAC/PHY device. For shared bus information,
see “Appendix A: Shared Bus Table” on page 39.
f
See www.idt.com for detailed information about the SRAM devices.
Ethernet
MAC/PHY
The LAN91C111 (U4) is a mixed signal analog/digital device that
implements protocols at 10Mbps and 100 Mbps. The control pins of U4 are
connected to the Cyclone device so that Nios systems can access Ethernet
via the RJ-45 connector (RJ1). See Figure 4 on page 19. The Nios
development kit includes hardware and software components that allow
Nios processor systems to communicate with the LAN91C111 Ethernet
device.
DQ27 50 U4
DQ28 51 U2
DQ29 53 U3
DQ30 54 V3
DQ31 56 V2
DQM0 16 J2
DQM1 71 J1
DQM2 28 H4
DQM3 59 H3
RAS_N 19 H2
CAS_N 18 G3
CKE 67 G7
CS_N 20 G6
WE_N 17 G4
CLK 68 L13
Table 6. SDRAM (U57) Pin Table (Part 3 of 3)
Pin Name Pin Number Connects to Cyclone Pin
Altera Corporation 19
Nios Development Board Reference Manual, Cyclone Edition Board Components
Figure 4. Ethernet MAC/PHY Device
The Ethernet MAC/PHY device share address and data connections with
the flash memory and the SRAM chips. For shared bus information, see
“Appendix A: Shared Bus Table” on page 39.
f
See www.smsc.com for detailed information about the LAN91C111
device. See the Plugs Ethernet Library Reference Manual for details on
accessing the MAC/PHY device in Nios software.
Expansion
Prototype
Connector
(PROTO1)
The PROTO1 expansion prototype connectors share Cyclone IO pins with
the compact flash connector. Designs may use either the PROTO1
connectors or the compact flash.
Headers J11, J12, and J13 collectively form the standard-footprint,
mechanically-stable connection that can be used (for example) as an
interface to a special-function daughter card.
1 See the Altera web site for a list of available expansion daughter
cards that can be used with the Nios development board at
www.altera.com/devkits.
The expansion prototype connector interface includes:
■ 41 I/O pins for prototyping. All 41 I/O pins connect to user I/O pins
on the Cyclone device. Each signal passes through analog switches
(U19, U20, U21, U22 and U25) to protect the Cyclone device from 5-V
logic levels. These analog switches are permanently enabled.
■ A buffered, zero-skew copy of the on-board OSC output from U2.
■ A buffered, zero-skew copy of the Cyclone's phase-locked loop
(PLL)-output from U60.
■ A logic-negative power-on reset signal
■ Five regulated 3.3-V power-supply pins (2A total max load for both
PROTO1 & PROTO2)
■ One regulated 5-V power-supply pin (1A total max load for both
PROTO1 & PROTO2)
■ Numerous ground connections
The output logic level on the expansion prototype connector pins is 3.3V.
The power supply included wit the Nios development kit cannot supply
the maximum load current specified above.
20 Altera Corporation
Board Components Nios Development Board Reference Manual, Cyclone Edition
Figure 5, Figure 6 on page 20 and Figure 7 on page 21 show connections
from the PROTO1 expansion headers to the Cyclone device. Unless
otherwise noted, labels indicate Cyclone device pin numbers.
Figure 5. Expansion Prototype Connector - J11
Figure 6. Expansion Prototype Connector - J12
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Altera Nios Ethernet Reference guide

Altera
Brand
Altera
Model
Nios Ethernet
Category
Networking
Type
Reference guide
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