Digi NET 50 Microprocessor User manual

Type
User manual

This manual is also suitable for

NET+50 Hardware Reference
90000281_C
Part number/version: 90000281_C
Release date: March 2006
www.digi.com
NET+50 Hardware Reference
Digi International
11001 Bren Road East
Minnetonka, MN 55343 U.S.A.
United States: +1 877 912-3444
Other locations: +1 952 912-3444
www.digi.com/support
www.digi.com
©2001-2006 Digi International Inc.
Printed in the United States of America. All rights reserved.
Digi, Digi International, the Digi logo, the Making Device Networking Easy logo, NetSilicon, a Digi
International Company, NET+, NET+OS and NET+Works are trademarks or registered trademarks of Digi
International, Inc. in the United States and other countries worldwide. All other trademarks are the
property of their respective owners.
Information in this document is subject to change without notice and does not represent a committment
on the part of Digi International.
Digi provides this document “as is,” without warranty of any kind, either expressed or implied, including,
but not limited to, the implied warranties of, fitness or merchantability for a particular purpose. Digi may
make improvements and/or changes in this manual or in the product(s) and/or the program(s) described
in this manual at any time.
This product could include technical inaccuracies or typographical errors. Changes are made periodically
to the information herein; these changes may be incorporated in new editions of the publication.
Contents
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Chapter 1: About the NET+50.................................................1
Introduction .............................................................................. 2
ARM7TDMI................................................................................. 2
The NET+50............................................................................... 2
Hardware design .................................................................. 3
Device modules ................................................................... 3
Chapter 2:
NET+50 Features ...................................................5
NET+50 chip key features .............................................................. 6
Chapter 3:
NET+50 Chip Package ..........................................9
NET+50 chip pinouts.................................................................... 10
Table Information and Tables ................................................. 12
System bus interface ............................................................ 13
Chip select controller ........................................................... 16
Ethernet interface............................................................... 16
MIC interface ..................................................................... 17
UARTS-SPI-GPIO .................................................................. 19
Clock generation/system reset ................................................ 20
JTAG port for ARM core......................................................... 21
Power supply ..................................................................... 21
Signal description summary ........................................................... 22
System bus interface ............................................................ 23
Chip select controller ........................................................... 24
Ethernet MII....................................................................... 24
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MIC interface ..................................................................... 25
GPIO (PORTA/B/C) .............................................................. 29
Clock generation and reset..................................................... 30
Test support ...................................................................... 31
ARM debugger .................................................................... 32
Power .............................................................................. 33
Packaging ................................................................................ 34
NET+50 PQFP package .......................................................... 34
BGA package...................................................................... 36
Chapter 4:
Working with the CPU..........................................39
Thumb concept ......................................................................... 40
Working with ARM exceptions ........................................................ 40
Exceptions ........................................................................ 41
Exception priorities.............................................................. 42
Exception vector table.......................................................... 43
Entering and exiting an exception (software action) ...................... 44
Exception entry / exit summary............................................... 45
Hardware interrupts............................................................. 46
Chapter 5:
BBus Module ...........................................................49
BBus functionality ...................................................................... 50
Cycles and BBus arbitration ........................................................... 50
Order of arbitration ............................................................. 50
Address decoding ....................................................................... 51
Chapter 6:
The GEN Module ....................................................53
Module configuration................................................................... 54
GEN module hardware initialization ................................................. 55
NET+50 bootstrap initialization................................................ 55
System registers ........................................................................ 57
System Control register......................................................... 57
System Status register .......................................................... 62
PLL ........................................................................................ 64
Timing Registers ........................................................................ 64
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Software Service register....................................................... 65
Timer Control registers ......................................................... 65
Timer Status register............................................................ 67
General Purpose I/O (GPIO) Registers............................................... 68
PORTA Register................................................................... 68
PORTB Register................................................................... 73
PORTC register ................................................................... 79
Interrupt generation and control..................................................... 86
NET+50 internal clock generation.................................................... 88
System clock generation........................................................ 89
Internal XTAL clock reference ................................................. 90
Reset circuit ............................................................................. 93
Powerup reset.................................................................... 93
External reset .................................................................... 94
Watch-Dog reset ................................................................. 94
ENI reset .......................................................................... 94
Software reset.................................................................... 94
Reset conditions ................................................................. 94
PLLTest Mode............................................................................ 95
Chapter 7:
Cache ....................................................................... 99
CBUS and BBus system buses.........................................................100
BIU and cache controller ......................................................100
Cache ....................................................................................101
Cache control registers ........................................................102
Cache operation ................................................................102
Cache line fill ...................................................................102
Cache line replacement .......................................................103
Cache line locking ..............................................................103
32-bit pre-fetch .................................................................103
Cache initialization.............................................................103
Cache Control registers...............................................................104
Register and bit definitions ...................................................104
Cache RAM ..............................................................................106
Cache TAG format .....................................................................107
Cache TAG format and definitions ...........................................108
vi      
Chapter 8: Memory Controller Module................................ 111
MEM module features .................................................................112
Memory control signals ........................................................112
Configuration registers ...............................................................113
Registers .........................................................................113
Memory Module Control register (MMCR) ...................................114
Memory control signals ...............................................................126
Data bus (D31:0) ................................................................127
Address bus (A27:0) ............................................................127
Chip selects/RAS (CSx*/RAS)..................................................128
Setting the Chip Select address range.......................................128
CS0* boot configuration........................................................131
Column address strobes (CAS) ................................................132
Read/Write (R/W*) .............................................................133
Output enable (OE*)............................................................133
Write enable (WE*) .............................................................133
Byte enable (BEx*)..............................................................134
Transfer Acknowledge (TA*) ..................................................135
Transfer Error Acknowledge (TEA*) ..........................................135
Basic configurations ...................................................................136
Static RAM .......................................................................136
Fast page and EDO DRAM ......................................................138
SDRAM ............................................................................147
NET+50 SDRAM interconnect .........................................................155
SDRAM x16 bursting considerations ..........................................156
x32 SDRAM configuration ......................................................156
x16 SDRAM configuration ......................................................157
WAIT configuration ....................................................................159
Burst terminate solution..............................................................159
Chapter 9:
DMA Controller Module ..................................... 163
DMA transfers ..........................................................................164
Fly-by operation ................................................................164
Memory-to-memory operation ................................................164
DMA module ............................................................................165
DMA controller assignments..........................................................166
      vii
DMA Channel.....................................................................167
DMA buffer descriptor ................................................................169
Source buffer pointer ..........................................................171
Buffer length ....................................................................171
Destination address pointer ...................................................172
DMA channel configuration...........................................................172
DMA registers...........................................................................174
DMA buffer descriptor pointer ................................................175
DMA Control register and bit definition .....................................175
DMA Status/Interrupt Enable register and bit definition .................180
Ethernet receiver considerations ...................................................182
External peripheral DMA support....................................................183
Signal description...............................................................183
External DMA configuration ...................................................185
Fly-by mode .....................................................................186
Memory-to-memory mode .....................................................187
DMA controller reset ..................................................................188
Chapter 10:
Ethernet Controller Module ............................189
Ethernet (EFE) front-end module ...................................................190
Media access controller (MAC) module.............................................191
Ethernet controller configuration...................................................192
Ethernet Registers.....................................................................194
Ethernet General Control register and bit definitions ....................195
Ethernet General Status register and bit definitions......................200
Ethernet FIFO Data register ...................................................204
Ethernet Transmit Status register and bit definitions ....................205
Ethernet Receive Status register and bit definitions......................208
MAC registers...........................................................................211
MAC Configuration register and bit definitions ............................211
MAC Test register and bit definitions........................................213
PCS registers ...........................................................................214
PCS Configuration register and bit definitions .............................214
PCS Test register................................................................216
STL registers............................................................................216
STL Configuration register and bit definitions .............................217
viii      
STL Test register and bit definitions.........................................218
Transmit Control registers ...........................................................219
Inter-Packet Gap (IPG) registers .............................................219
Collision Window/Collision Retry register ..................................225
“Simulation” registers .........................................................226
Receive Control registers.............................................................229
Receive Byte Counter (RBCT) .................................................229
Receive Counter Decodes (ECRDC)...........................................229
Test Operate Receive Counters (RECTCL) ..................................230
PCS Control registers..................................................................231
Link Fail Counter (LFCT).......................................................231
10 MB Jabber Counter (JBCT).................................................231
10 MB Loss of Carrier Counter (DTLB) .......................................232
Ethernet MII interface signals........................................................233
MII Control registers...................................................................235
MII Command register and bit definitions...................................235
MII Address register and bit definitions .....................................236
MII Write Data register and bit definition...................................236
MII Read Data register and bit definition ...................................237
MII Indicators register and bit definitions...................................237
Statistics monitoring ..................................................................238
Error Statistics registers .......................................................239
Station Address registers/multicast hash table ...................................241
Station Address Filter register and bit definitions.........................242
Station Address register and bit definitions ................................243
Multicast hash table entries and bit definitions ...........................244
Chapter 11:
Serial Controller Module................................. 251
Features.................................................................................252
Bit-rate generator .....................................................................254
Serial protocols ........................................................................254
UART mode ......................................................................254
HDLC mode ......................................................................255
SPI Mode..........................................................................257
General purpose I/O configurations ................................................268
Serial port performance ..............................................................271
      ix
Configuration...........................................................................272
Serial controller register diagrams..................................................273
Serial Channel registers ..............................................................278
Serial Channel Control Register A ............................................278
Serial Channel Control Register B ............................................283
Serial Channel Status Register A .............................................288
Serial Channel Bit-Rate registers.............................................296
Serial Channel FIFO registers .................................................302
Receive Gap Timer registers.........................................................302
Receive Buffer Timer register and bit definitions .........................304
Receive Character Timer register and bit definitions.....................305
Receive Match registers ..............................................................306
Receive Match register and bit definitions .................................306
Receive Match MASK register and bit definitions ..........................307
Control Register C (HDLC)............................................................308
Status Register B (HDLC) .............................................................309
Status Register B and bit definitions.........................................310
Status Register C (HDLC) .............................................................313
Status Register C and bit definitions ........................................313
FIFO Data Register LAST (HDLC).....................................................315
Chapter 12:
MIC Controller Module.....................................317
MIC controller modes of operation..................................................318
MIC modes of operation........................................................319
MIC controller configuration ..................................................320
MIC module interrupts .........................................................321
MIC module hardware initialization..........................................321
GPIO mode..............................................................................322
GPIO function configurations .................................................323
Examples using PORTF .........................................................325
PORTD register ..................................................................327
PORTF register ..................................................................330
PORTG register..................................................................333
PORTH register ..................................................................335
IEEE 1284 host interface (4-port) module .........................................338
IEEE 1284 signal cross reference .............................................341
x      
IEEE 1284 port multiplexing...................................................342
IEEE 1284 mode configuration ................................................342
IEEE negotiation.................................................................343
IEEE 1284 forward compatibility mode......................................343
IEEE 1284 nibble mode.........................................................344
IEEE 1284 byte mode ...........................................................345
IEEE 1284 forward ECP mode .................................................346
IEEE 1284 reverse ECP mode ..................................................348
IEEE 1284 EPP mode ............................................................350
IEEE 1284 Configuration registers ............................................354
IEEE 1284 Port Control registers and bit definitions ......................354
IEEE 1284 Channel Data registers ............................................359
IEEE 1284 strobe pulse width .................................................360
IEEE 1284 external loopback mode ..........................................361
ENI mode overview ....................................................................361
ENI host interface...............................................................362
Signal descriptions..............................................................364
ENI shared RAM mode .................................................................369
Memory map.....................................................................369
Shared RAM ......................................................................370
Shared register ..................................................................371
Clear interrupts .................................................................376
Address interrupts ..............................................................376
ENI FIFO mode module................................................................378
FIFO Data register ..............................................................380
FIFO Mask/Status register and bit definition ...............................382
ENI mode registers ....................................................................387
General Control register and bit definitions................................387
General Status register and bit definitions .................................391
ENI mode FIFO Data register ..................................................393
ENI Control register and bit definitions .....................................394
ENI Pulsed Interrupt register and bit definition............................401
ENI Shared RAM Address register and bit definitions......................401
Chapter 13:
Timing .................................................................. 405
Thermal considerations...............................................................406
Absolute maximum ratings ...........................................................407
      xi
DC characteristics .....................................................................407
AC characteristics .....................................................................409
Output pad timing ..............................................................409
Clock relationships .............................................................411
RESET* timing ...................................................................411
SRAM timing ............................................................................412
SRAM Sync Read (WAIT = 2) ...................................................413
SRAM Sync Write (WAIT = 2)...................................................414
SRAM Sync Burst Read (2-111) (WAIT = 0, BCYC = 00).....................415
SRAM Sync Burst Read (4-222) (WAIT = 2, BCYC = 01).....................416
SRAM Sync Burst Write (4-222) (WAIT = 2, BCYC = 01)....................417
SRAM Async Read (WAIT = 2) ..................................................418
SRAM Async Write (WAIT = 2) .................................................419
SRAM Async Burst Read (WAIT = 2, BCYC = 01).............................420
SRAM Async Burst Write (WAIT = 2, BCYC = 01) ............................421
Fast Page and EDO DRAM Timing ....................................................422
Fast Page and EDO DRAM Read ...............................................423
Fast Page and EDO DRAM Write...............................................424
Fast Page and EDO DRAM Burst Read ........................................425
Fast Page and EDO DRAM Burst Write .......................................427
Fast Page and EDO DRAM Refresh (RCYC = 0) ..............................429
Fast Page and EDO DRAM Refresh (RCYC = 1) ..............................429
Fast Page and EDO DRAM Refresh (RCYC = 2) ..............................430
Fast Page and EDO DRAM Refresh (RCYC = 3) ..............................430
SDRAM timing...........................................................................431
SDRAM Read (CAS Latency = 1) ...............................................432
SDRAM Read (CAS Latency = 2) ...............................................433
SDRAM Write (CAS Latency = 2)...............................................434
SDRAM Burst Read (CAS Latency = 1) ........................................435
SDRAM Burst Read (CAS Latency = 2) ........................................436
SDRAM Burst Write (CAS Latency = 2) .......................................437
SDRAM Refresh Command .....................................................438
SDRAM Load-Mode Command .................................................439
External DMA timing...................................................................440
External Fly-by DMA ............................................................441
External Memory-to-Memory DMA............................................443
SPI timing ...............................................................................445
xii      
SPI Master mode 0 and 1 (two-byte transfer) ..............................445
SPI Slave mode 0 and 1 ........................................................446
MIC timing ..............................................................................448
ENI Shared RAM and Register Cycle timing .................................450
ENI Single Direction DMA timing..............................................451
ENI Dual Direction DMA timing................................................452
Ethernet timing ........................................................................453
Ethernet timing diagram.......................................................454
Ethernet Receive Clock Idle...................................................454
External Ethernet CAM Filtering..............................................455
JTAG timing ............................................................................455
1284 Port Multiplexing timing .......................................................456
1284 Compatibility mode timing ....................................................457
Forward ECP mode timing............................................................459
Crystal oscillator specifications .....................................................460
Appendix A: ARM Exceptions
................................................ 461
About ARM exceptions ................................................................462
Reset exception .................................................................462
Undefined exception ...........................................................462
SWI exception ...................................................................463
Abort exception .................................................................463
IRQ exception ...................................................................464
FIRQ exception ..................................................................464
Index
Using This Guide
      xiii
Review this section for basic information about the guide you are using, as
well as general support and contact information.
About this guide
This guide provides information about the Digi NET+50 32-bit networked
microprocessor. The NET+50 are part of the Digi NET+ARM line of SoC (System-
on-Chip) products, and support any type of high-bandwidth applications in
Intelligent Networked Devices.
The NET+ARM chip is part of the NET+Works integrated product family, which
includes the NET+OS network software suite.
Who should read this guide
This guide is for hardware developers, system software developers, and
applications programmers who want to use the NET+50 for development.
To complete the tasks described in this guide, you must:
Understand the basics of hardware and software design, operating
systems, and microprocessor design.
Understand the NET+50 architecture.
Using This Guide
xiv       
NET+50 Hardware Reference
What’s in this guide
This table shows where you can find specific information in this guide:
To read about See
The NET+50 chip Chapter 1, "About the NET+50"
NET+50 key features Chapter 2, "NET+50 Features"
NET+50 PQFP/BGA pin/ball grid array
assignments and packaging
Chapter 3, "NET+50 Chip Package"
NET+50 CPU and the ARM Thumb concept Chapter 4, "Working with the CPU"
BBus functionality Chapter 5, "BBus Module"
General (GEN) module functionality Chapter 6, "The GEN Module"
ARM7TDMI stand-alone core and instruction/data
cache, write protection, and pre-fetch control
Chapter 7, "Cache"
How the NET+50 can be configured to interface
with different types of memory devices
Chapter 8, "Memory Controller Module"
DMA controller, supported DMA channels, and
internal and externalDMA transfers
Chapter 9, "DMA Controller Module"
Ethernet controller module Chapter 10, "Ethernet Controller Module"
Serial channel A and serial channel B Chapter 11, "Serial Controller Module"
Multi interface controller (MIC) Chapter 12, "MIC Controller Module"
NET+50 timing information and diagrams Chapter 13, "Timing"
ARM exceptions Appendix A, "ARM Exceptions"
www.digi.com
       xv
Conventions used in this guide
This table describes the typographic conventions used in this guide:
Related documentation
NET+50/20M Jumpers and Components provides a hardware description of
the NET+Works Development Board
, and includes information about
jumpers, connectors, switches, and interface configuration as well as
development board diagrams.
Review the documentation CD-ROM that came with your development kit
for information on third-party products and other components.
Refer to the NET+OS software documentation for information appropriate to
the chip you are using.
Documentation updates
Digi occasionally provides documentation updates on the Web site (www.digi.com/
support).
Be aware that if you see differences between the documentation you received in your
package and the documentation on the Web site, the Web site content is the latest
version.
This convention Is used for
italic type Emphasis, new terms, variables, and document titles.
monospaced type
Filenames, pathnames, and code examples.
xvi       
NET+50 Hardware Reference
Customer support
To get help with a question or technical problem with this product, or to make
comments and recommendations about our products or documentation, use the
contact information listed in this table:
For Contact information
Technical support United States: +1 877 912-3444
Other locations: +1 952 912-3444
www.digi.com/support
www.digi.com
       1
About the NET+50
CHAPTER 1
The Digi NET+50 is a system-on-a-chip ASIC designed for use in intelligent network
devices and Internet appliances. The NET+50 consists of a 208 plastic-quad-flat-pack
(PQFP) package and a 208 ball-grid-array (BGA) package. The NET+50 is a high-
performance, highly-integrated 32-bit chip.
Introduction
2       
Net+50 Hardware Reference
Introduction
The NET+50 supports almost any networking scenario, with a 10/100 BaseT Ethernet
MAC with MII interface and two independent serial ports, each of which can run in
UART, HDLC, or SPI modes. The CPU is an ARM7TDMI 32-bit RISC processor core with a
rich complement of support peripherals, including memory controllers for various
types of memory (including flash, SDRAM, and EEPROM), programmable timers, and a
10-channel DMA controller.
The NET+50 provides all tools required for any embedded networking application.
ARM7TDMI
The heart of the NET+50 hardware is provided by the ARM7TDMI. The ARM7TDMI is a
member of the ARM Ltd. family of general purpose 32-bit microprocessors, which
offer high-performance while maintaining very low power-consumption and size.
The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles.
Compared with Complex Instruction Set Computers (CISC) architecture, the RISC
instruction set, and related decoding and execution mechanisms, is simpler and more
streamlined. This simplicity results in a high instruction throughput and impressive
real-time interrupt response, as well as a small, cost-effective circuit. The RISC
architecture is conducive to pipelining, which allows the instruction fetch, decode,
and execution units to operate simultaneously.
The NET+50
The NET+50 can be used in any embedded environment requiring networking services
in an Ethernet LAN. The NET+50 contains an ARM RISC processor, 10/100 Ethernet
MAC, serial ports, IEEE 1284 parallel ports, memory controllers, and parallel I/O. The
NET+50 chip can interface with another processor using a RAM or shared RAM
interface.
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Digi NET 50 Microprocessor User manual

Type
User manual
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