AE TECHRON MULTI-AMP CONFIGURATION GUIDE
97-8002465-B_06-24-2020 Information subject to change
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List of Figures
Figure 1.1 – Maximum Continuous Output in 2100 or 7000-Series Multi-amp Systems .................................. 4
Figure 3.1 – Two in Series: Single-Ended vs. Differential....................................................................................... 7
Figure 3.2 – SIM-BNC-OPTOC card jumper locations ............................................................................................. 7
Figure 3.3 – Older SIM-BNC-OPTOC card jumper locations ................................................................................... 8
Figure 3.4 – Input Connectors Wiring Diagram ...................................................................................................... 8
Figure 3.5 – 2105/7212/7224 Amplifier Access Panel Screw Locations .......................................................... 9
Figure 3.6 – Master/Follower Jumper Locations .................................................................................................. 10
Figure 3.7 – 2105/7212/7224 Output Terminal Resistor ................................................................................. 10
Figure 3.8 – 2110/2120/7548/7796 Output Terminal Resistor ..................................................................... 10
Figure 3.9 – Terminating the Amplifier Input ........................................................................................................ 11
Figure 3.10 – Verifying DC Offset .......................................................................................................................... 11
Figure 3.11 – Verifying Amp Gain .......................................................................................................................... 12
Figure 3.12 – Verifying System Gain ..................................................................................................................... 13
Figure 3.13 – Two Amplifiers in Series – Differential Configuration ................................................................... 14
Figure 3.14 – Terminating the Amplifier Input ...................................................................................................... 15
Figure 3.15 – Verifying DC Offset .......................................................................................................................... 15
Figure 3.16 – Verifying Amp Gain .......................................................................................................................... 16
Figure 3.17 – Verifying System Gain ..................................................................................................................... 17
Figure 3.18 – Two Amplifiers in Series – Single-Ended Configuration ................................................................ 17
Figure 3.19 – Three Amplifiers in Series – Single-Ended Configuration ............................................................. 18
Figure 4.1 – 2105/7224 Ballast Resistor Mounting ........................................................................................... 19
Figure 4.2 – 2120/7796 Ballast Resistor Mounting ........................................................................................... 19
Figure 4.3 – 2105/7224 Ballast Resistor Connected to Output Terminal ......................................................... 20
Figure 4.4 – 2120/7796 Ballast Resistors Connected to Output Terminal ....................................................... 20
Figure 4.5 – Gain Control Connection on Main Board......................................................................................... 20
Figure 4.6 – Gain Control Pin Settings .................................................................................................................. 20
Figure 4.7 – Connecting for Balancing (Four in Parallel shown).......................................................................... 21
Figure 4.8 – Terminating the Amplifier Input ........................................................................................................ 22
Figure 4.9 – Main Board Balancing Control Locations ......................................................................................... 22
Figure 4.10 – Wiring and Test Points for DC Offset .............................................................................................. 23
Figure 4.11 – Wiring the Paralleled Input Wire ..................................................................................................... 23
Figure 4.12 – Optional BNC Parallel Input Wiring (Three in Parallel shown) ..................................................... 23
Figure 4.13 – Wiring and Test Points for Amp Gain ............................................................................................. 24
Figure 4.14 – Wiring and Test Points for Gain Matching ..................................................................................... 25
Figure 4.15 – Two Amplifiers Paralleled ............................................................................................................... 27
Figure 4.16 – Three Amplifiers Paralleled ............................................................................................................. 27
Figure 4.17 – Four Amplifiers Paralleled ............................................................................................................... 28
Figure A-1 – Wire Current-Carrying Capacity Chart ............................................................................................... 29
Figure B-1 – Critical Wire Lengths in Parallel Systems ......................................................................................... 30
Figure C-1 – Output Cables constructed for use in a Two-in-Parallel System .................................................... 31
Figure D-1 – DB-25 Cable Wiring for a Four-in-Parallel System ........................................................................... 31
Figure E-1 – 2105/7212/7224 Access Panel Screw Locations ........................................................................ 31
Figure E-2 – Master/Follower Jumper Locations .................................................................................................. 31
Figure E-3 – 2105/7212/7224 Output Terminal Resistor ................................................................................. 31
Figure E-4 – 2110/2120/7548/7796 Output Terminal Resistor...................................................................... 31
Figure E-5 – SIM-BNC-OPTOC, Factory Default Settings ....................................................................................... 31
Figure E-6 – SIM-BNC-OPTOC, Factory Default Settings for older input card version ........................................ 31