Analog Devices EVAL-ADAQ4003FMCZ User manual

Analog Devices
Brand
Analog Devices
Model
EVAL-ADAQ4003FMCZ
Type
User manual
EVAL-ADAQ4003FMCZ Evaluation Board User Guide
UG-1533
One Technology Way • P. O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com
Evaluating the ADAQ4003 18-Bit, 2 MSPS, µModule Data Acquisition Solution
PLEASE SEE THE LAST PAGE FOR AN IMPORTANT
WARNING AND LEGAL TERMS AND CONDITIONS.
Rev. 0 | Page 1 of 31
FEATURES
Fully featured Pmod evaluation board with a Pmod to
FMC interposer board
Versatile analog signal conditioning circuitry
On-board reference and ADC drivers
PC software for control and data analysis of time and
frequency domain
System demonstration platform compatible (EVAL-SDP-CH1Z)
EVALUATION BOARD KIT CONTENTS
EV-ADAQ4003PMDZ Pmod evaluation board
EVAL-PMD-IB1Z Pmod to FMC interposer board
EQUIPMENT NEEDED
PC running Windows® 10 or higher
EVAL-SDP-CH1Z (SDP-H1) controller board
Precision signal source
Cable (SMB input to evaluation board)
Standard USB A to Mini-B USB cable
Band-pass filter suitable for 18-bit testing (value based on
signal frequency)
SOFTWARE NEEDED
ADAQ400x evaluation software
GENERAL DESCRIPTION
The ADAQ4003 µModule® data acquisition system evaluation kit
(EVAL-ADAQ4003FMCZ) contains the EV-ADAQ4003PMDZ
peripheral module (Pmod) board and the EVA L -PMD-IB1Z
Pmod to field programmable grid array (FPGA) mezzanine
card (FMC) interposer board that interfaces with the system
demonstration controller board (EVA L-SDP-CH1Z) via a 160-pin
FMC connector as shown in Figure 1.
The ADAQ4003 µModule combines multiple common signal
processing and conditioning blocks into a single device that
includes a low noise, fully differential analog-to-digital converter
(ADC) driver, a stable reference buffer, a high resolution, 18-bit,
2 MSPS successive approximation register (SAR) ADC, and the
critical passive components necessary for optimum performance.
The EV-ADAQ4003PMDZ on-board components include the
following:
• The ADR4550 high precision, buffered band gap, 5.0 V
voltage reference (see Figure 33
)
• An optional ADA4898-1 high voltage, low noise,
low distortion, unity-gain stable, high speed op amp
(see Figure 34)
• An optional AD8251 programmable gain in-amp (see
Figure 34)
• The LT5400-4 quad matched, low drift, resistor network.
Note that J1 and J2 on the EV-ADAQ4003PMDZ provide low
noise analog signal sources.
For full details on the ADAQ4003, see the ADAQ4003 data
sheet, which must be consulted in conjunction with this user
guide when using the E VA L -ADAQ4003FMCZ.
UG-1533 EVAL-ADAQ4003FMCZ Evaluation Board User Guide
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TABLE OF CONTENTS
Features .............................................................................................. 1
Evaluation Board Kit Contents ....................................................... 1
Equipment Needed ........................................................................... 1
Software Needed ............................................................................... 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
EVA L-ADAQ4003FMCZ Evaluation Board Kit Photograph ...... 3
Evaluation Board Hardware ............................................................ 4
Setting Up the EVA L-ADAQ4003FMCZ Evaluation Kit ......... 4
EVA L-SDP-CH1Z (SDP-H1) Board .......................................... 4
Power Supplies .............................................................................. 5
Analog Inputs ................................................................................ 6
Link Configuration for Different Gain Options ...................... 7
Evaluation Board Software .............................................................. 8
Installing the Software ................................................................. 8
EV-ADAQ4003PMDZ Operation and Connection Sequence
....................................................................................................... 10
Running the ADAQ400x Evaluation Board Software with the
Hardware Connected ................................................................. 10
Software Operation ........................................................................ 11
Description of the User Panel ................................................... 11
Waveform Capture ..................................................................... 14
Histogram .................................................................................... 15
FFT Capture ................................................................................ 16
INL_DNL Capture Linearity Testing ....................................... 17
Summary Tab .............................................................................. 18
Troubleshooting .............................................................................. 19
ADAQ400x Evaluation Board Software Troubleshooting .... 19
Hardware Throubleshooting .................................................... 19
Evaluation Board Schematics and Silkscreens ............................ 20
EV-ADAQ4003PMDZ .............................................................. 20
EVA L-PMD-IB1Z....................................................................... 24
Ordering Information .................................................................... 29
Bill of Materials ........................................................................... 29
REVISION HISTORY
9/2020—Revision 0: Initial Version
EVAL-ADAQ4003FMCZ Evaluation Board User Guide UG-1533
Rev. 0 | Page 3 of 31
EVAL-ADAQ4003FMCZ EVALUATION BOARD KIT PHOTOGRAPH
20211-001
EV-ADAQ4003PMDZ
EVAL-PMD-IB1Z
EVAL-SDP-CH1Z
Figure 1.
UG-1533 EVAL-ADAQ4003FMCZ Evaluation Board User Guide
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EVALUATION BOARD HARDWARE
SETTING UP THE EVAL-ADAQ4003FMCZ
EVALUATION KIT
Figure 2 shows the simplified EV-ADAQ4003PMDZ block
diagram. Figure 33 to Figure 34 show the EV-ADAQ4003PMDZ
board schematics, which consists of the ADAQ4003 µModule
(U5), the ADR4550 (U1), the ADA4898-1 (U4 and U7), the
AD8251 (A1), the ADP5070 (U3), the LT3032 (U2), and the
LT3023 (U6). The EV-ADAQ4003PMDZ is a flexible design
that enables the user to select components in addition to
operate from an adjustable bench top power supply.
EVAL-SDP-CH1Z (SDP-H1) BOARD
The EV-ADAQ4003PMDZ evaluation kit uses a serial port
interface (SPI) and requires the system demonstration platform
(SDP-H1) to capture the data via a graphic user interface (GUI)
(see Figure 1). The SDP-H1 requires power from a 12 V wall
adapter. The SDP-H1 has a Xilinx® Spartan®-6 and an ADSP-BF527
processor with connectivity to the PC through a USB 2.0 high
speed port.
The SDP-H1 has an FMC low pin count connector with full
differential low voltage differential signaling (LVDS) and
singled-ended, low voltage, complementary metal-oxide
semiconductor (CMOS) support. The SDP-H1 also has a
120-pin connector that exposes the Blackfin® processor
peripherals. This connector provides a configurable serial,
parallel I
2
C and SPI and general-purpose input/output (GPIO)
communication lines to the attached daughter board.
–15V
–15V
+15V
EVAL-SDP-CH1Z
160-PIN
FMC CONNECTOR
12V
12V
WALL WART
USB PORT
POWER
SUPPLY
CIRCUITRY
ADSP-BF527
SPARTAN-6
FPGA
XC6SLX25
FMC TO PMOD
INTERPOSER
BOARD
EVAL-PMD-IB1Z
EVALUATION BOARD FOR THE µMODULE DATAACQUISITION SYSTEM
IN+
OUT+
ADAQ4003
SCK
SDO
CNV
VIO
SDI
REFVDD
–15V
+15V
+15V
+15V
+15.5V
–15.5V
VIN+
VIN–
ADA4898-1
ADA4898-1
GND
ADR4550
SPI
INTERFACE
+3.3V
LT3032
LT3023
ADP5070
VS–
VS+
OUT–
R1K1+
R1K+
R1K–
R1K1–
IN–
+1.8V
+5.5V
–15V
GND
(OPTIONAL)
+15V
EVAL-ADAQ4003FMCZ
20211-002
Figure 2. Simplified Evaluation Board Block Diagram
EVAL-ADAQ4003FMCZ Evaluation Board User Guide UG-1533
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POWER SUPPLIES
The system demonstration platform board (SDP-H1) supplies
3.3 V to power the rails for the different components on the
EVA L-ADAQ4003FMCZ.
The ADAQ4003 uses four power supply pins: the ADC driver
positive supply (VS+), the ADC driver negative supply (VS−),
the core ADC supply (VDD), and the digital input and output
interface supply (VIO). The VIO pin allows the direct interface
with any logic c between 1.8 V and 5.5 V. To reduce the number
of supplies required, VIO and VDD can be tied together for an
1.8 V operation. A combination of the ADP5070 (dual, high
performance dc-to-dc switching regulator), the LT3032 (dual,
low noise, positive and negative low dropout voltage linear
regulator), and the LT3023 (dual, micropower, low noise, low
dropout regulator) can generate independently regulated
positive and negative rails for all four power supply pins,
including ±15 V rails for any additional signal conditioning.
Table 1. Default Power Supplies Available on the EV-
ADAQ4003PMDZ
Power Supply (V) Function Components Used
+5.5 Reference rail ADP5070, LT3032, LT3023
±15 Amplifier rails ADP5070, LT3032
+1.8, +3.3, or +5.5 µModule rails ADP5070, LT3032, LT3023
Each supply is decoupled at the EV-ADAQ4003PMDZ entrance
and device connection. A single, on-board ground plane
minimizes the effect of the high frequency noise interference.
In addition, the EV-ADAQ4003PMDZ can be powered from a
benchtop power supply of ±15.5 V. The +15.5V, −15.5V, and
GND test points are available on board to support this function.
When bench power is used, the on-board power supplies are no
longer required, and the link between the output pin of the
ADP5070 must be removed, that is, uninstall R20 and R22.
Take the following steps to set up the EV-ADAQ4003PMDZ
when using a benchtop power supply of ±15.5 V:
1. Connect the EV-ADAQ4003PMDZ board to EVA L-PMD-
IB1Z interposer board at the P1 header (see Figure 1).
2. Connect the EVA L-PMD-IB1Z interposer board to the
SDP-H1 board via the 160-pin FMC connector.
3. Connect the USB and a 12 V power adaptor to the SDP-H1
board. Ensure that the software and drivers are installed.
4. Connect the +15.5 V and −15.5 V bench supplies to the
+15.5V and −15.5V test points on the EV-ADAQ4003PMDZ
(see Figure 3). Connect the bench supply ground to the
GND test point as shown in Figure 3.
5. Power up the benchtop supply. The +15.5 V supply rail
draws approximately 25 mA, and the −15.5 V supply rail
draws approximately 20 mA.
The EV-ADAQ4003PMDZ is now ready to use. See the
Evaluation Board Software section for details on using the
ADAQ400x evaluation board software. Note that by default, the
EV-ADAQ4003PMDZ is setup to accept a differential input at
J1 and J2 with a 20 V range.
202
1
1-102
–15.5V
+15.5V
GND
Figure 3. EV-ADAQ4003PMDZ External Supply Connections
UG-1533 EVAL-ADAQ4003FMCZ Evaluation Board User Guide
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ANALOG INPUTS
The analog inputs of the EV-ADAQ4003PMDZ, J1 and J2, are
Subminiature Version B (SMB) connectors. These inputs are
fed to the ADA4898-1. J1 and J2 are buffered with dedicated
amplifier circuitry, U4 and U7, as shown in Figure 34. The
circuit enables different configurations, input range scaling,
filtering, amplifiers and supplies, and the addition of a dc
component. The analog input amplifiers are set as unity-gain
buffers at the factory.
The analog inputs are fully differential by default. If a single-ended
bipolar input is desired, such as ±10 V, t h e EV-ADAQ4003PMDZ
can be configured for single-ended to differential conversion
by changing JP6 to Position 2 and Position 3 and by applying the
single-ended input at Connector J1 (see Table 2).
For dynamic performance, a fast Fourier transform (FFT) test
can be performed by applying a low distortion ac source. For
low frequency testing, the audio precision source, such as the
SYS-2700 series, can be used directly with the evaluation board.
Different precision sources can be used with additional filtering.
Table 2. Jumper Details with Factory Default Setting
Link Default Function Comment
JP1 Not populated Gain options Fully differential or single-ended configuration.
JP2 B1 and B2, A1 and A2 µModule input
The ADAQ4003 has a gain of 0.454 (20 V range). See the
ADAQ4003 data sheet for other gains.
JP3 B1 and B2, A1 and A2 µModule input
The ADAQ4003 has a gain of 0.454 (20 V range). See the
ADAQ4003 data sheet for other gains.
JP4 Pin A to Pin COM Synchronize the switching frequency to CNV
To set the switching frequency to 1.2 MHz, pull the
SYNC/FREQ pin of the ADP5070 low or Pin B to Pin COM.
JP5 Pin A to Pin COM Op amp or in-amp Connect the J1 input to the ADA4898-1 op amp.
JP6 Pin A to Pin COM Op amp or in-amp Connect the J2 input to the ADA4898-1 op amp.
JP6 Pin A to Pin COM Single-ended or differential input
Differential input by default. Connect Pin B to COM for a
single-ended input and connect JP7 to Pin B to Pin COM.
JP7 Pin B to Pin COM Op amp or in-amp
Connect the ADA4898-1 op amp to the ADAQ4003
µModule.
JP8 Pin B to Pin COM Amplifier or in-amp Connect Pin A to Pin COM to the output of the AD8251.
JP9 Pin B to Pin COM Gain setting pin (LSB)
Refer to the AD8251 data sheet for the truth table logic
levels for transparent gain mode.
JP10 Pin B to Pin COM Gain setting pin (MSB)
Refer to the AD8251 data sheet for the truth table logic
levels for transparent gain mode.
JP11 Pin A to Pin COM Power Differential amplifier positive supply. Tied to ground.
JP12 Pin A to Pin COM Differential amplifier power mode Differential amplifier positive supply. Tied to ground.
JP13 Pin A to Pin COM Differential amplifier power down Full power mode. See the ADAQ4003 data sheet.
JP14 Pin A to Pin COM Reference buffer power down Powered up. See the ADAQ4003 data sheet.
JP15 Pin A to Pin COM Differential amplifier power down Powered up. See the ADAQ4003 data sheet.
EVAL-ADAQ4003FMCZ Evaluation Board User Guide UG-1533
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LINK CONFIGURATION FOR DIFFERENT GAIN
OPTIONS
Multiple link options must be set correctly for appropriate gain
configuration of the ADAQ4003. Table 3 details the different
gain positions for the links of the EV-ADAQ4003PMDZ.
B1
JP2
A1
B2 A2
B1
JP3
A1
B2
A2
20211-104
Figure 4. Gain = 0.454
B1
JP2
A1
B2 A2
B1
JP3
A1
B2 A2
20211-105
Figure 5. Gain = 0.9
B1
JP2
A1
B2
A2
B1
JP3
A1
B2 A2
20211-106
Figure 6. Gain = 1
Figure 7. Gain = 1.9
Table 3. The Different Gain Positions Available for the Links of the EV-ADAQ4003PMDZ
Gain Input Range (V) Input Signal on Pins Test Conditions
0.454 ±11 R1K1− and R1K1+
For JP2, tie A1 to A2 and tie B1 to B2, and for JP3, tie A1 to A2 and tie B1 to
B2 (see Figure 4).
0.9 ±5.5 R1K1− and R1K1+ For JP2, tie B1 to B2, and for JP3, tie B1 to B2 (see Figure 5).
1 ±5 R1K− and R1K+ For JP2, tie A2 to B1, and for JP3, tie A1 to B2 (see Figure 6).
1.9 ±2.6 R1K1−, R1K−, R1K1+, and R1K+ For JP2, tie B1 to A2 and B2, and for JP3, tie B2 to A1 and B1 (see Figure 7).
UG-1533 EVAL-ADAQ4003FMCZ Evaluation Board User Guide
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EVALUATION BOARD SOFTWARE
INSTALLING THE SOFTWARE
To install the software required to evaluate the EV-
ADAQ4003PMDZ, take the following steps:
1. Download the ADAQ400x evaluation board software.
2. Double-click the setup.exe file to open the software
installation window (see Figure 8).
202
11-208
Figure 8. ADAQ400X Evaluation Software Install Window
3. Choose the folder location for installation and click
Next>>. The default folder is shown in Figure 9.
202
11-209
Figure 9. Destination Directory
4. Accept the ADAQ400x evaluation board software license
agreement and click Next>>.
20211-210
Figure 10. License Agreement
5. Click Next>> again to install the software (see Figure 11).
20211-211
Figure 11. Start Installation
6. The pop-up window shown in Figure 12 opens and
displays the installation progress bar.
202
11-212
Figure 12. Overall Progress Bar
EVAL-ADAQ4003FMCZ Evaluation Board User Guide UG-1533
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7. Click Next>> to complete the installation and to launch the
SDP-H1 driver installation (see Figure 13 and Figure 14).
These drivers must be installed for the evaluation board
to function correctly.
20211-213
Figure 13. Installation Complete
20211-009
Figure 14. Beginning of SDP-H1 Driver Installation
8. The ADI SDP Drivers 2.4.0.268 Setup Wizard opens, or
the latest version (see Figure 15). Click Next> to install the
ADI SDP drivers.
20211-215
Figure 15. ADI SDP Drivers Setup Wizard
9. Installing the ADI SDP Drivers 2.4.0.268 Setup requires
the user to accept the license agreement that appears in
Figure 16. Read the agreement and then click I Agree to
proceed.
202
1
1-216
Figure 16. ADI SDP Drivers 2.4.0.268 Setup License Agreement
10. Choose the installation location and click Install. The
default folder is shown in Figure 17.
20211-217
Figure 17. Choose Install Location Window
11. The installation then begins, and a progress bar displays
(see Figure 18).
20211-218
Figure 18. Installing Bar
UG-1533 EVAL-ADAQ4003FMCZ Evaluation Board User Guide
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12. Click Close to complete the installation (see Figure 19).
20211-219
Figure 19. Installation Complete Window
When the SDP-H1 board is plugged in for the first time, allow the
Found New Hardware Wizard to run. Users can verify that the
drivers and the EV-ADAQ4003PMDZ are connected correctly by
going to the Device Manager on the PC. Analog Devices
System Development Platform (32MB) should appear under
the ADI Development To ols dropdown list (see Figure 20).
20211-014
Figure 20. Device Manager
EV-ADAQ4003PMDZ OPERATION
AND CONNECTION SEQUENCE
The following is the EV-ADAQ4003PMDZ operation and
connection sequence:
1. Connect the SDP-H1 to the EVA L-PMD-IB1Z with the
FMC connector, P2, and connect the EV-ADAQ4003PMDZ
to the EVA L -PMD-IB1Z as shown in Figure 2. The
ADAQ400x evaluation board software is configured to find
the EV-ADAQ4003PMDZ using the SDP-H1 connector.
2. Power the EV-ADAQ4003PMDZ with the appropriate
supply as described in the Setting Up the E VAL -
ADAQ4003FMCZ Evaluation Kit section.
3. Connect to the PC using the USB cable.
4. Launch the ADAQ400x evaluation board software. Click
Start > All Programs > Analog Devices\ADAQ400X
Evaluation Software\EVA L -ADAQ400X.
5. Apply the signal source and capture the data.
RUNNING THE ADAQ400x EVALUATION BOARD
SOFTWARE WITH THE HARDWARE CONNECTED
To run the ADAQ400x evaluation board software, take the
following steps:
1. Click Start > All Programs > Analog Devices >
ADAQ400X Evaluati o n S o f t w a re > E VA L-ADAQ400X.
To uninstall the ADAQ400x evaluation board software,
click Start > Control Panel > Programs and Features >
Analog Devices ADAQ400X Evaluation Software.
2. The ADAQ400x evaluation board software automatically
discovers the connected hardware. Therefore, when no
hardware is connected, the ADAQ400x evaluation board
software displays a connectivity error (see Figure 21).
20211-015
Figure 21. SDP-H1 Board Not Detected
3. Connect the EV-ADAQ4003PMDZ to the SDP-H1 and the
SDP-H1 to the USB port of the PC, wait for a few seconds,
click Rescan, and then follow the on screen instructions.
4. If users click Cancel, the message shown in Figure 22 appears.
2021
1-016
Figure 22. SDP-H1 Board Not Connected to the USB Port Error
5. When the ADAQ400x evaluation board software connects to
the EV-ADAQ4003PMDZ the message in Figure 23 displays.
20211-017
Figure 23. Software Connecting to SDP-H1 Board
6. When the EV-ADAQ4003PMDZ is correctly detected, the
software panel opens.
EVAL-ADAQ4003FMCZ Evaluation Board User Guide UG-1533
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SOFTWARE OPERATION
When the ADAQ400x evaluation board software detects the generic attached to the PC, the window in Figure 24 opens.
9
10
11
12
13
14
15
7
6
8
2
1
4
3
5
20211-018
Figure 24. Setup Screen
DESCRIPTION OF THE USER PANEL
The following describes the user panel shown in Figure 24.
The File menu (Label 1 in Figure 24) contains the following
options:
• Save Captured Data, which allows the user to save the
current captured data for later analysis. The file format is
.csv. The user is prompted to choose or enter the path of
the file in the Save As pop-up (see Figure 25). Save the file
to an appropriate folder location.
• Load Captured Data, which prompts a Load File pop-up to
open that prompts the user to load previously captured data
in .csv format for analysis.
• Take Screenshot, which allows the user to save the current
screen capture as a .jpg.
• Print Screenshot, which allows the user to save the current
screen capture as a .pdf.
• Exit, which stops running the application software.
20211-019
Figure 25. Save As Dialog Box
The Edit menu (Label 1 in Figure 24) provides the option to
reset the software to the initial state (Reinitialize to Default
Values).
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The Help menu (Label 1 in Figure 24) offers information about the
• Analog Devi ces Website
• User Guide
• Context Help
• About
When hardware is connected to the USB port, the software
automatically detects the connected device and displays the
information (see Label 2 in Figure 24).
The Oversampling Ratio box (Label 3 in Figure 24) sets the
oversampling ratio applied to the captured data. After this
control is set to any value other than None, the software sums
up the consecutive conversion results together to increase the
effective resolution. The number of conversions summed
together is set by the Oversampling Ratio box. Oversampling
by a factor of four provides one additional bit of resolution, or
a 6 dB increase in dynamic range, or in other words, ΔDR =
10 × log10(OSR) in dB (see Figure 26).
The Throughput box is Label 4 in Figure 24. The default
throughput (sampling frequency) is 1.75 KSPS. The user can
adjust the throughput to a minimum of 10 kSPS. If the user
enters a value larger than the ability of the existing device, the
software reverts to the maximum throughput.
The Voltage Reference dropdown menu is Label 5 in Figure 24. By
default, this reference is 5 V (ADR4550 on-board reference). The
minimum and maximum voltage calculations are based on this
reference voltage. If the user changes the reference voltage, this
input must be changed accordingly.
Click Single Capture to perform a single capture, and click and
Continuous Capture to perform a continuous stream capture
from the µModule (see Label 6 in Figure 24).
Select Samples to analyze data using the number of samples
(see Label 7 in Figure 24). The maximum number of samples the
software can support is 524,288.
The five capture tabs (see Label 8 in Figure 24
) display the data
in different formats, which include the following:
• Waveform
• Histogram
• FFT
• INL_DNL
• Summary
20211-130
Figure 26. FFT with Oversampling, OSR = 256, Inputs Shorted
EVAL-ADAQ4003FMCZ Evaluation Board User Guide UG-1533
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Click Enable Status Bits to enable the content of the status header
(see Label 9 in Figure 24). Status bits can be clocked out at the
end of the conversion data using six extra clocks when enabled.
Click Span Compression to enable the µModule span
compression feature (see Label 10 in Figure 24). In single-supply
applications, the use of span compression increases the
headroom and footroom available to the ADC driver by
reducing the input range 10% from the top and bottom of the
range while still accessing all available µModule codes.
Click High-Z Mode to enable the internal high-Z mode (see
Label 11 in Figure 24). Enabling this mode allows the low input
current for the µModule and improves total harmonic
distortion (THD) performance.
Click Normal Mode to toggle to Turbo Mode to enable this
mode and run the µModule at a full throughput of 2 MSPS (see
Label 12 in Figure 24).
Click Read Register to enable features such as span
compression, high-Z mode, turbo mode, an overvoltage
condition (a sticky bit), and the status bits (see Label 13 in
Figure 24).
Click Enable Status Bits (see Label 9 in Figure 24) to enable the
six status bits. The content of the six bits is updated and displayed
in the Status Header section (see Label 14 in Figure 24) after
clicking Single Capture or Continuous Capture (see Label 6 in
Figure 24). Note that the overvoltage clamp flag status bit
updates on a per conversion basis.
When the Busy indicator is lit, the user must wait until the
software completes the data analysis (see Label 15 in Figure 24).
To exit the software, select File > Exit.
Within any of the chart panels, the tools shown in Table 4
allow
the user to control the different chart displays.
Table 4. Graphical User Interface (GUI) Tools
Symbol Description
This tool controls the cursor, if present.
This tool zooms in and out.
This tool is used for panning.
The ADAQ400x evaluation board software allows the user to
export the raw data or image. Right click any of the five capture
tabs (Waveform, Histogram, FFT, INL_DNL, and Summary) to
open the window shown in Figure 27. The user can either
export raw data to Excel or save an image as a .BMP, .EPS, or
.EMF format.
20211-020
Figure 27. Export Raw Data or Image
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WAVEFORM CAPTURE
Figure 28 shows the waveform capture. The input signal is a
1 kHz sine wave. The waveform analysis reports the amplitudes
recorded from the captured signal in addition to the frequency of
the signal tone.
20211-021
Figure 28. Waveform Tab
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HISTOGRAM
AC Testing
The ac testing histogram tests the µModule for the code
distribution of the ac input and computes the mean, minimum,
and maximum amplitude and the LSB size of the converter.
Raw data is captured and passed to the PC for statistical
computations. To perform a histogram test, click the Histogram
tab and click Single Capture or Continuous Capture. Note that
an ac histogram needs a signal source applied to the J1 and J2
input connectors on the EV-ADAQ4003PMDZ. Figure 29 shows
the histogram for a 1 kHz sine wave applied to the input of the
EV-ADAQ4003PMDZ.
DC Testing
More commonly, the histogram is used for dc testing where
the user tests the µModule for the code distribution for dc input,
computes the mean and standard deviation, or transition noise,
of the converter, and displays the results. Raw data is captured
and passed to the PC for statistical computations. To perform a
histogram test, click the Histogram tab and click Single Capture
or Continuous Capture. To test various dc values, apply a source to
the J1 and J2 input connectors on the EV-ADAQ4003PMDZ.
20211-022
Figure 29. Histogram Tab, Histogram Captured for Sine Wave
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FFT CAPTURE
The traditional ac characteristics of the converter can be
displayed in the FFT tab. The FFT tab displays signal-to-noise
ratio (SNR), signal-to-noise-and-distortion ratio (SINAD),
THD, and spurious-free dynamic range (SFDR) data. The data
can also be displayed in the time domain. To perform an ac test,
apply a sinusoidal signal to the EV-ADAQ4003PMDZ at
the SMB inputs, J1 and J2. Low distortion, better than 100 dB,
is required for true evaluation of the device. To achieve low
distortion, the input signal can be filtered from the ac source.
A band-pass filter can be used, but the center frequency must
match the test frequency of interest. Furthermore, if using a low
frequency band-pass filter when the full-scale input range is
more than a few volts peak-to-peak, use the on-board amplifiers to
amplify the signal, thus preventing the filter from distorting the
input signal.
Figure 30 displays the histogram of the captured data that includes
the following:
• Spectrum information
• Fundamental frequency and amplitude in addition to the
second to fifth harmonics
• Performance data (SNR, Dynamic Range, THD, SINAD,
and noise performance)
2021
1-023
Figure 30. FFT Tab (ADAQ4003 Running in Turbo Mode)
EVAL-ADAQ4003FMCZ Evaluation Board User Guide UG-1533
Rev. 0 | Page 17 of 31
INL_DNL CAPTURE LINEARITY TESTING
The INL_DNL tab displays linearity analysis (see Figure 31).
INL is the deviation of each individual code from a line drawn
from negative full scale through positive full scale. The point
used as negative full scale occurs ½ LSB before the first code
transition. Positive full scale is defined as a level 1½ LSB beyond
the last code transition. The deviation is measured from the
middle of each code to the true straight line.
In an ideal ADC, code transitions are 1 LSB apart. DNL is the
maximum deviation from this ideal value. DNL is often specified in
terms of resolution for which no missing codes are guaranteed.
To perform a linearity test, apply a sinusoidal signal with 0.5 dB
above full scale to the EV-ADAQ4003PMDZ board at the J1
and J2 SMB inputs. Set the number of hits per code and adjust
to the desired accuracy. Using a large number of hits per code
results in a significant test time. Figure 31 displays captured
data that includes ±INL and ±DNL positions.
20211-130
Figure 31. INL and DNL Testing
UG-1533 EVAL-ADAQ4003FMCZ Evaluation Board User Guide
Rev. 0 | Page 18 of 31
SUMMARY TAB
The Summary tab captures the window information and displays the captured information in one panel with a synopsis of the
information including key performance parameters, such as SNR and THD.
20211-024
Figure 32. Summary Tab, Shows All Captured Windows
EVAL-ADAQ4003FMCZ Evaluation Board User Guide UG-1533
Rev. 0 | Page 19 of 31
TROUBLESHOOTING
ADAQ400x EVALUATION BOARD SOFTWARE
TROUBLESHOOTING
To troubleshoot the ADAQ400x evaluation board software, take
the following steps:
1. Install the software before connecting the hardware to the PC.
2. Allow the install to fully complete (the software is a two-
part installation). A restart is recommended after
installation is finished.
3. When the user first plugs in the SDP-H1 board via the USB
cable provided, allow the Found New Hardware Wizard
to run, which may take a little time. However, allow this
wizard to run before starting the software.
4. If the EV-ADAQ4003PMDZ does not appear to be
functioning, ensure that the EV-ADAQ4003PMDZ
is connected to the SDP-H1 board and that the EV-
ADAQ4003PMDZ is recognized in the Device Manager, as
shown in Figure 20.
5. If connected to a slower USB port where the SDP-H1 cannot
read as quickly as it needs to, a timeout error may result. In
this case, it is advised not to read continuously or to lower
the number of samples taken.
HARDWARE THROUBLESHOOTING
To troubleshoot the hardware, take the following steps:
1. Check that the power is applied within the power ranges
described in the Setting Up the EVA L-ADAQ4003FMCZ
Evaluation Kit section.
2. Using a voltmeter, measure the voltage present at each of
the test points: +15V, − 1 5 V, −VS, and VIN (3.3 V). Note
that the SDP-H1 board LED1 must be lit.
3. Launch the ADAQ400x evaluation board software and
read the data. If nothing happens, exit the software.
4. Power down the EV-ADAQ4003PMDZ and relaunch the
software.
5. When no data is read back, confirm that the EV-
ADAQ4003PMDZ is connected to the SDP-H1 board and
that the EV-ADAQ4003PMDZ is recognized in the Device
Manager, as shown in
Figure 20.
6. When the user is working with the software in standalone
or offline mode (no hardware connected) and later chooses
to connect hardware, close and relaunch the software.
UG-1533 EVAL-ADAQ4003FMCZ Evaluation Board User Guide
Rev. 0 | Page 20 of 31
EVALUATION BOARD SCHEMATICS AND SILKSCREENS
EV-ADAQ4003PMDZ
20211-025
3.3V
VOLTAGE REFERENCE
R10
C53
C52
E1
R17
R21 R18
R8
C23
C19
R6
JP4
R26
R27
C7
C16
C8
C25 C24
12
10
1
7
13
14
PAD2
9
6
PAD1
5
4
3
11
2
8
U2
GND
R28
C30
C29
R33R34
R31R32
C26
C28
C27
R30
R29
U6
14
12
2
18
20
8
4
3
16
17
15
19
PAD
1
11
5
9
7
10
6
13
U3
R12
R24
R15
1
+15.5V
C20
R20
C15
L5
R16
R25
1
–15.5V
C21
R22
C14
C9
R9
C10
C11
R11
D1
L2
C3
C2
R5
R4
R2
R3
C1
1
VIN
C12
R13
R14
L4
C4
D2
L1
6
2
8
7
5
3
1
4
U1
R23
C22
C17
R19
C6C5
R7
C18
C13
0.0033µF
22µH
80.6kΩ
LT3032IDE#PBF
P5P5V
2.7kΩ
ADJ1 ADJ2
ADJ2
P1P8V
DNI
DNI
0Ω
TBD0603
TBD0603
P15P5V
N15P5V
0Ω
0Ω
0Ω
P5P5V
P1P8V
VREF
1µF
TBD0603
DNI
0Ω
10µF
P5P5V
0.1µF
WHT
22µH
42.2kΩ
0.1µF
N15V
10µF
WHT
VIN
1µF
CNV
42.2kΩ
0
680nH
11.5Ω
DFLS240-7
1µF
680nH
11.5Ω
DFLS240-7
0Ω
10µF
WHT
WHT
54.9kΩ
1µF
0.01µF
200kΩ
ADJ1
0Ω
0Ω
0.01µF
200kΩ
698kΩ
95.3kΩ
LT3023IDD#PBF
P15V
N15V
0.01µF
0.01µF
0Ω
61.9kΩ
42.2kΩ
42.2kΩ
22µF
600Ω AT 100MHz
22µF
3PIN_JUMPER
P15V
0.0047µF
ADP5070ACPZ-R7
0Ω
ADR4550BRZ
P15V
0Ω
N15V
N15P5V
P15V
61.9kΩ
2.2µF
2.2µF
2.2µF
2.2µF
4.7µF
4.7µF
4.7µF
698kΩ
698kΩ
4.7µF
P15P5V
3.3kΩ 60.4kΩ
0.039µF
10µF
10µF
1µF
100kΩ
0.022µF
PAD
OUT2
SHDN2_N
IN
SHDN1_N
OUT1
BYP1
ADJ1
GND
ADJ2
BYP2
PAD
SW2
PVIN2
PVINSYS
PVIN1
VREG
AGND
VREF
FB2
COMP2
EN2
SS
EN1
COMP1
FB1
SLEW
SEQ
SYNC/FREQ
INBK
SW1
PGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGNDAGND
AGND
AGND
NC
NC
NC
NC
VIN
GND
TP
VOUT
AGND
B
COM
A
AGND
INN
INP
NC
SHDNP_N
BYPN
SHDNN_N
INN
ADJN/NC
OUTN
INN
GND
BYPP
ADJP/NC
OUTP
AGND
Figure 33. EV-ADAQ4003PMDZ Power Supplies and Voltage Reference
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Analog Devices EVAL-ADAQ4003FMCZ User manual

Analog Devices
Brand
Analog Devices
Model
EVAL-ADAQ4003FMCZ
Type
User manual
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