Hynix HMT351U7CFR8A-PBT0 Datasheet

Rev. 1.1 / Jul. 2013 1

240pin DDR3L SDRAM Unbuffered DIMM

* SK hynix Semiconductor reserves the right to change products or specifications without notice.

DDR3L SDRAM

Unbuffered DIMMs

Based on 2Gb C-Die

HMT325U7CFR8A

HMT351U7CFR8A

Rev. 1.1 / Jul. 2013 2

Revision History

Revision No. History Draft Date Remark

0.1 Initial Release Aug. 2011

0.2 Added Speed Bin Table Notes Sep. 2011

0.3 JEDEC Spec Updated Mar. 2012

1.0

Module Dimension Updated Jul. 2012

1.1

Changed module maximum thickness

to reflect the measured maximum

Jul. 2013

Rev. 1.1 / Jul. 2013 3

Description

SK hynix Unbuffered DDR3L SDRAM DIMMs (Unbuffered Double Data Rate Synchronous DRAM Dual In-

Line Memory Modules) are low power, high-speed operation memory modules that use DDR3L SDRAM

devices. These Unbuffered SDRAM DIMMs are intended for use as main memory when installed in systems

such as PCs and workstations.



Feature

• Power Supply: VDD=1.35V (1.283V to 1.45V)

• VDDQ=1.35V (1.283 to 1.45V)

• VDDSPD=3.0V to 3.6V

• Backward Compatible with 1.5V DDR3 Memory module

• 8 internal banks

• Data transfer rates: PC3-12800,PC3-10600

• Bi-directional Differential Data Strobe

• 8 bit pre-fetch

• Burst Length (BL) switch on-the-fly: BL 8 or BC (Burst Chop) 4

• Supports ECC error correction and detection

• On Die Termination (ODT) supported

• Temperature sensor with integrated SPD (Serial Presence Detect) EEPROM

• This product is in Compliance with the RoHS directive

Ordering Information

Part Number Density Organization Component Composition

# of

ranks

FDHS

HMT325U7CFR8A-H9/PB 2GB 256Mx72 256Mx8(H5TC2G83CFR)*9 1 X

HMT351U7CFR8A-H9/PB 4GB 512Mx72 256Mx8(H5TC2G83CFR)*18 2 X

Rev. 1.1 / Jul. 2013 4

Key Parameters

*SK hynix DRAM devices support optional downbinning to CL9 and CL7. SPD setting is programmed to match

Speed Grade

Address Table

MT/s Grade

tCK

(ns)

CAS

Latency

(tCK)

tRCD

(ns)

tRP

(ns)

tRAS

(ns)

tRC

(ns)

CL-tRCD-tRP

DDR3-1066 -G7 1.875 7 13.125 13.125 37.5 50.625 7-7-7

DDR3L-1333 -H9 1.5 9

13.5

(13.125)*

13.5

(13.125)*

36

49.5

(49.125)*

9-9-9

DDR3L-1600 -PB 1.25 11

13.75

(13.125)*

13.75

(13.125)*

35

48.75

(48.125)*

11-11-11

Grade

Frequency [MHz]

Remark

CL6 CL7 CL8 CL9 CL10 CL11

-G7 800 1066 1066

-H9 800 1066 1066 1333 1333

-PB 800 1066 1066 1333 1333 1600

2GB(1Rx8) 4GB(2Rx8)

Refresh Method 8K/64ms 8K/64ms

Row Address A0-A14 A0-A14

Column Address A0-A9 A0-A9

Bank Address BA0-BA2 BA0-BA2

Page Size 1KB 1KB

Rev. 1.1 / Jul. 2013 5

Pin Descriptions

Pin Name Description Pin Name Description

A0–A15 SDRAM address bus SCL

I

2

C serial bus clock for EEPROM

BA0–BA2 SDRAM bank select SDA

I

2

C serial bus data line for EEPROM

RAS SDRAM row address strobe SA0–SA2

I

2

C slave address select for EEPROM

CAS SDRAM column address strobe

V

DD

*

SDRAM core power supply

WE

SDRAM write enable

V

DDQ

*

SDRAM I/O Driver power supply

S0–S1 DIMM Rank Select Lines VREFDQ SDRAM I/O reference supply

CKE0–CKE1 SDRAM clock enable lines V

REFCA

SDRAM command/address reference

supply

ODT0–ODT1 On-die termination control lines V

SS Power supply return (ground)

DQ0–DQ63 DIMM memory data bus V

DDSPD Serial EEPROM positive power supply

CB0–CB7 DIMM ECC check bits NC Spare pins (no connect)

DQS0–DQS8

SDRAM data strobes

(positive line of differential pair)

TEST

Memory bus analysis tools

(unused on memory DIMMS)

DQS

0–DQS8

SDRAM data strobes

(negative line of differential pair)

RESET Set DRAMs to Known State

DM0–DM8

SDRAM data masks/high data strobes

(x8-based x72 DIMMs)

V

TT

SDRAM I/O termination supply

CK0–CK1

SDRAM clocks

(positive line of differential pair)

RSVD Reserved for future use

CK

0–CK1

SDRAM clocks

(negative line of differential pair)

- -

*The V

DD and VDDQ pins are tied common to a single power-plane on these designs

Rev. 1.1 / Jul. 2013 6

Input/Output Functional Descriptions

Symbol Type Polarity Function

CK0–CK1

CK

0–CK1

SSTL

Differential

crossing

CK and CK

are differential clock inputs. All the DDR3L SDRAM addr/cntl

inputs are sampled on the crossing of positive edge of CK and negative

edge of CK

. Output (read) data is reference to the crossing of CK and CK

(Both directions of crossing).

CKE0–CKE1 SSTL Active High

Activates the SDRAM CK signal when high and deactivates the CK signal

when low. By deactivating the clocks, CKE low initiates the Power Down

mode, or the Self Refresh mode.

S

0–S1SSTLActive Low

Enables the associated SDRAM command decoder when low and disables

the command decoder when high. When the command decoder is dis-

abled, new commands are ignored but previous operations continue. This

signal provides for external rank selection on systems with multiple ranks.

RAS

, CAS, WE SSTL Active Low RAS, CAS, and WE (ALONG WITH S) define the command being entered.

ODT0–ODT1 SSTL Active High

When high, termination resistance is enabled for all DQ, DQS, DQS and DM

pins, assuming this function is enabled in the Mode Register 1 (MR1).

V

REFDQ Supply Reference voltage for SSTL15 I/O inputs.

V

REFCA Supply Reference voltage for SSTL 15 command/address inputs.

V

DDQ Supply

Power supply for the DDR3L SDRAM output buffers to provide improved

noise immunity. For all current DDR3L unbuffered DIMM designs, VDDQ

shares the same power plane as V

DD pins.

BA0–BA2 SSTL — Selects which SDRAM bank of eight is activated.

A0–A15 SSTL —

During a Bank Activate command cycle, Address input defines the row

address (RA0–RA15).

During a Read or Write command cycle, Address input defines the column

address. In addition to the column address, AP is used to invoke autopre-

charge operation at the end of the burst read or write cycle. If AP is high,

autoprecharge is selected and BA0, BA1, BA2 defines the bank to be pre-

charged. If AP is low, autoprecharge is disabled. During a Precharge com-

mand cycle, AP is used in conjunction with BA0, BA1, BA2 to control which

bank(s) to precharge. If AP is high, all banks will be precharged regardless

of the state of BA0, BA1 or BA2. If AP is low, BA0, BA1 and BA2 are used to

define which bank to precharge. A12(BC

) is sampled during READ and

WRITE commands to determine if burst chop (on-the-fly) will be per-

formed (HIGH, no burst chop; LOW, burst chopped).

DQ0–DQ63,

CB0–CB7

SSTL — Data and Check Bit Input/Output pins.

DM0–DM8 SSTL Active High

DM is an input mask signal for write data. Input data is masked when DM

is sampled High coincident with that input data during a write access. DM

is sampled on both edges of DQS. Although DM pins are input only, the DM

loading matches the DQ and DQS loading.

V

DD, VSS Supply

Power and ground for the DDR3 SDRAM input buffers, and core logic. V

DD

and V

DDQ pins are tied to VDD/VDDQ planes on these modules.

Rev. 1.1 / Jul. 2013 7

DQS0–DQS8

DQS

0–DQS8

SSTL

Differential

crossing

Data strobe for input and output data.

SA0–SA2 —

These signals are tied at the system planar to either V

SS or VDDSPD to con-

figure the serial SPD EEPROM address range.

SDA —

This bidirectional pin is used to transfer data into or out of the SPD

EEPROM. An external resistor may be connected from the SDA bus line to

V

DDSPD to act as a pullup on the system board.

SCL —

This signal is used to clock data into and out of the SPD EEPROM. An

external resistor may be connected from the SCL bus time to V

DDSPD to act

as a pullup on the system board.

VDDSPD Supply

Power supply for SPD EEPROM. This supply is separate from the V

DD/VDDQ

power plane. EEPROM supply is operable from 3.0V to 3.6V.

Symbol Type Polarity Function

Rev. 1.1 / Jul. 2013 8

Pin Assignments

Front Side(left 1–60) Back Side(right 121–180) Front Side(left 61–120) Back Side(right 181–240)

#

x72

ECC

#

x72

ECC

#

x72

ECC

#

x72

ECC

1V

REFDQ 121

V

SS

61 A2 181 A1

2

V

SS

122 DQ4 62 VDD 182 VDD

3 DQ0 123 DQ5 63 CK1 183 VDD

4DQ1124

V

SS

64 CK1184CK0

5

V

SS

125 DM0 65 VDD 185 CK0

6DQS

0126 NC 66 VDD 186 VDD

7DQS0127

V

SS

67 VREFCA 187 EVENT

8

V

SS

128 DQ6 68 NC 188 A0

9 DQ2 129 DQ7 69 VDD 189 VDD

10 DQ3 130

V

SS

70 A10 190

BA1

2

11

V

SS

131 DQ12 71

BA0

2

191 VDD

12 DQ8 132 DQ13 72 VDD 192 RAS

13 DQ9 133

V

SS

73 WE 193 S0

14

V

SS

134 DM1 74 CAS 194 VDD

15 DQS1135 NC 75 VDD 195 ODT0

16 DQS1 136

V

SS

76 S1 196 A13

17

V

SS

137 DQ14 77 ODT1 197 VDD

18 DQ10 138 DQ15 78 VDD 198 NC

19 DQ11 139

V

SS

79 NC 199

V

SS

20

V

SS

140 DQ20 80

V

SS

200 DQ36

21 DQ16 141 DQ21 81 DQ32 201 DQ37

22 DQ17 142

V

SS

82 DQ33 202

V

SS

23

V

SS

143 DM2 83

V

SS

203 DM4

24 DQS

2144 NC 84 DQS4204 NC

25 DQS2 145

V

SS

85 DQS4 205

V

SS

26

V

SS

146 DQ22 86

V

SS

206 DQ38

27 DQ18 147 DQ23 87 DQ34 207 DQ39

28 DQ19 148

V

SS

88 DQ35 208

V

SS

29

V

SS

149 DQ28 89

V

SS

209 DQ44

30 DQ24 150 DQ29 90 DQ40 210 DQ45

NC = No Connect; RFU = Reserved Future Use

1. NC pins should not be connected to anything on the DIMM, including bussing within the NC group.

2. Address pins A3–A8 and BA0 and BA1 can be mirrored or not mirrored.

Rev. 1.1 / Jul. 2013 9

31 DQ25 151

V

SS

91 DQ41 211

V

SS

32

V

SS

152 DM3 92

V

SS

212 DM5

33 DQS3153 NC 93 DQS5213 NC

34 DQS3 154

V

SS

94 DQS5 214

V

SS

35

V

SS

155 DQ30 95

V

SS

215 DQ46

36 DQ26 156 DQ31 96 DQ42 216 DQ47

37 DQ27 157

V

SS

97 DQ43 217

V

SS

38

V

SS

158 CB4 98

V

SS

218 DQ52

39 CB0 159 CB5 99 DQ48 219 DQ53

40 CB1 160

V

SS

100 DQ49 220

V

SS

41

V

SS

161 DM8 101

V

SS

221 DM6

42 DQS8 162 NC 102 DQS6222 NC

43 DQS8 163

V

SS

103 DQS6 223

V

SS

44

V

SS

164 CB6 104

V

SS

224 DQ54

45 CB2 165 CB7 105 DQ50 225 DQ55

46 CB3 166

V

SS

106 DQ51 226

V

SS

47

V

SS

167 NC 107

V

SS

227 DQ60

48 NC 168 Reset 108 DQ56 228 DQ61

KEY KEY 109 DQ57 229

V

SS

49 NC 169 CKE1/NC 110

V

SS

230 DM7

50 CKE0 170 V

DD 111 DQS7231 NC

51 VDD 171 NC 112 DQS7 232

V

SS

52 BA2 172 A14 113

V

SS

233 DQ62

53 NC 173 V

DD 114 DQ58 234 DQ63

54 V

DD 174 A12 115 DQ59 235

V

SS

55 All 175 A9 116

V

SS

236 VDDSPD

56

A7

2

176 VDD 117 SA0 237 SA1

57 V

DD 177

A8

2

118 SCL 238 SDA

58

A5

2

178

A6

2

119

SA2

239

V

SS

59

A4

2

179 VDD 120 VTT 240 VTT

60 VDD 180

A3

2

Front Side(left 1–60) Back Side(right 121–180) Front Side(left 61–120) Back Side(right 181–240)

#

x72

ECC

#

x72

ECC

#

x72

ECC

#

x72

ECC

NC = No Connect; RFU = Reserved Future Use

1. NC pins should not be connected to anything on the DIMM, including bussing within the NC group.

2. Address pins A3–A8 and BA0 and BA1 can be mirrored or not mirrored.

Rev. 1.1 / Jul. 2013 10

On DIMM Thermal Sensor

The DDR3L SDRAM DIMM temperature is monitored by integrated thermal sensor. The integrated thermal

sensor comply with JEDEC “TSE2002av, Serial Presence Detect with Temperature Sensor”.

Connection of Thermal Sensor

Temperature-to-Digital Conversion Performance

Parameter Condition Min Typ Max Unit

Temperature Sensor Accuracy (Grade B)

Active Range,

75°C < T

A

< 95°C

- ± 0.5 ± 1.0 °C

Monitor Range,

40°C < T

A

< 125°C

- ± 1.0 ± 2.0 °C

-20°C < T

A

< 125°C

- ± 2.0 ± 3.0 °C

Resolution 0.25

°C

EVENT

SCL

SDA

SA0

SA1

SA2

EVENT

SCL

SDA

SA0

SA1

SA2

SPD with

Integrated

TS

Rev. 1.1 / Jul. 2013 11

Functional Block Diagram

2GB, 256Mx72 Module(1Rank of x8)

DQ4

DQ5

DQ6

DQ7

DQ0

DQ1

DQ2

DQ3

DM

I/O 0

I/O 1

I/O 2

I/O 3

D0

DM0

I/O 4

I/O 5

I/O 6

I/O 7

DQ12

DQ13

DQ14

DQ8

DQ9

DQ10

DQ11

DM

I/O 0

I/O 1

I/O 2

I/O 3

D1

I/O 4

I/O 5

I/O 6

DM1

DQ20

DQ21

DQ22

DQ23

DQ16

DQ17

DQ18

DQ19

DM

I/O 0

I/O 1

I/O 2

I/O 3

D2

I/O 4

I/O 5

I/O 6

I/O 7

DM2

DQ28

DQ29

DQ30

DQ31

DQ24

DQ25

DQ26

DQ27

DM

I/O 0

I/O 1

I/O 2

I/O 3

D3

I/O 4

I/O 5

I/O 6

I/O 7

DM3

DQ36

DQ37

DQ38

DQ39

DQ32

DQ33

DQ34

DQ35

DM

I/O 0

I/O 1

I/O 2

I/O 3

D4

DM4

I/O 4

I/O 5

I/O 6

I/O 7

DQ44

DQ45

DQ46

DQ47

DQ40

DQ41

DQ42

DQ43

DM

I/O 0

I/O 1

I/O 2

I/O 3

D5

I/O 4

I/O 5

I/O 6

I/O 7

DM5

DQ52

DQ53

DQ54

DQ55

DQ48

DQ49

DQ50

DQ51

DM

I/O 0

I/O 1

I/O 2

I/O 3

D6

I/O 4

I/O 5

I/O 6

I/O 7

DQ60

DQ61

DQ62

DQ63

DQ56

DQ57

DQ58

DQ59

DM

I/O 0

I/O 1

I/O 2

I/O 3

D7

I/O 4

I/O 5

I/O 6

I/O 7

DM7

A0

SPD(TS integrated)

A1

SA0 SA1

SDA

S0

CS

DQS0

DQS

DQS4

DQS1

DQS5

DQS

DQS2

DQS

DQS3

DQS

DM6

DQS6

DQS7

DQ15

I/O 7

CB4

CB5

CB6

CB7

CB0

CB1

CB2

CB3

DM

I/O 0

I/O 1

I/O 2

I/O 3

D8

I/O 4

I/O 5

I/O 6

I/O 7

CS

DQS8

DM8

DQS

SCL

EVENT

DQS0

DQS

DQS4

DQS1

DQS

DQS2

DQS

DQS3

DQS

DQS8

DQS

DQS5

DQS

6

DQS

DQS7

DQS

SA2

A2

ZQ

EVENT

A0–A15 A0–A15: SDRAMs D0–D8

RAS

RAS: SDRAMs D0–D8

CAS

CAS: SDRAMs D0–D8

CKE0 CKE: SDRAMs D0–D8

WE

WE: SDRAMs D0–D8

BA0–BA2 BA0–BA2: SDRAMs D0–D8

VSS

D0–D8

VDD/VDDQ

D0–D8

V

REF

DQ

SPD

VDDSPD

ODT0 ODT: SDRAMs D0–D8

CK0 CK: SDRAMs D0–D8

VREFCA

D0–D8

CK0CK: SDRAMs D0–D8

RESET RESET: SDRAMs D0-D8

Notes:

1. DQ-to-I/O wiring is shown as recom-

mended but may be changed.

2. DQ/DQS/DQS

/ODT/DM/CKE/S rela-

tionships must be maintained as

shown.

3. DQ,CB,DM,DQS/DQS

resistors;Refer

to associated topology diagram.

4. Refer to the appropriate clock wiring

topology under the DIMM wiring

details section of this document.

5. For each DRAM, a unique ZQ resistor

is connected to ground.The ZQ resis-

tor is 240ohm+-1%

6. One SPD exists per module.

Rev. 1.1 / Jul. 2013 12

4GB, 512Mx72 Module(2Rank of x8)

DQ4

DQ5

DQ6

DQ7

DQ0

DQ1

DQ2

DQ3

I/O 1

I/O 2

I/O 3

D0

D9

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQ12

DQ13

DQ14

DQ8

DQ9

DQ10

DQ11

I/O 0

I/O 1

I/O 2

I/O 3

D1

D10

I/O 4

I/O 5

I/O 6

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

DQ20

DQ21

DQ22

DQ23

DQ16

DQ17

DQ18

DQ19

I/O 0

I/O 1

I/O 2

I/O 3

D2

D11

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQ28

DQ29

DQ30

DQ31

DQ24

DQ25

DQ26

DQ27

I/O 0

I/O 1

I/O 2

I/O 3

D3

D12

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQ36

DQ37

DQ38

DQ39

DQ32

DQ33

DQ34

DQ35

I/O 0

I/O 1

I/O 2

I/O 3

D4

D13

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQ44

DQ45

DQ46

DQ47

DQ40

DQ41

DQ42

DQ43

I/O 0

I/O 1

I/O 2

I/O 3

D5

D14

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQ52

DQ53

DQ54

DQ55

DQ48

DQ49

DQ50

DQ51

I/O 0

I/O 1

I/O 2

I/O 3

D6

D15

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQ60

DQ61

DQ62

DQ63

DQ56

DQ57

DQ58

DQ59

I/O 0

I/O 1

I/O 2

I/O 3

D7

D16

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

A0–A15 A0-A15: SDRAMs D0–D17

RAS

RAS: SDRAMs D0–D17

CAS

CAS: SDRAMs D0–D17

WE

WE: SDRAMs D0–D17

CKE1 CKE: SDRAMs D9–D17

BA0–BA2 BA0-BA2: SDRAMs D0–D17

DQ15

I/O 7

CB4

CB5

CB6

CB7

CB0

CB1

CB2

CB3

I/O 0

I/O 1

I/O 2

I/O 3

D8

D17

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS8

DM8

Vss

D0–D17

V

DD

/V

DD

Q

D0–D17

V

REF

DQ

SPD

V

DDSPD

DM CS DQS DQS DM

CS

DQS DQS

DM CS DQS DQS DM

CS

DQS DQS

DM CS DQS DQS DM

CS

DQS DQS DM CS DQS DQS DM

CS

DQS DQS

DM CS DQS DQS DM

CS

DQS DQS DM CS DQS DQS DM

CS

DQS DQS

DM CS DQS DQS DM

CS

DQS DQS DM CS DQS DQS DM

CS

DQS DQS

DM CS DQS DQS DM

CS

DQS DQS

I/O 0

DM0

DM4

S0

S

1

DQS0 DQS4

DM1 DM5

DQS1

DQS5

DQS1DQS5

DM2

DQS2

DM6

DQS6

DQS

2

DM3

DM7

DQS3

DQS7

DQS

3

DQS

7

DQS6

DQS8

ODT0 ODT: SDRAMs D0–D8

ODT1 ODT: SDRAMs D9–D17

CKE0 CKE: SDRAMs D0–D8

CK0 CK: SDRAMs D0–D8

CK0CK: SDRAMs D0–D8

D0–D17

V

REF

CA

CK1 CK: SDRAMs D9–D17

CK1CK: SDRAMs D9–D17

ZQ

ZQ ZQ

RESET RESET: SDRAMs D0-D17

Notes:

1. DQ-to-I/O wiring is shown as recom-

mended but may be changed.

2. DQ/DQS/DQS/ODT/DM/CKE/S relation-

ships must be maintained as shown.

3. DQ,CB,DM/DQS/DQS resistors;Refer to

associated topology diagram.

4. Refer to Section 3.1 of this document for

details on address mirroring.

5. For each DRAM, a unique ZQ resistor is

connected to ground.The ZQ resistor is

240ohm+-1%

6. One SPD exists per module.

A0

SPD(TS integrated)

A1

SA0 SA1

SDA

SCL

EVENT

SA2

A2

EVENT

Rev. 1.1 / Jul. 2013 13

Absolute Maximum Ratings

Absolute Maximum DC Ratings

Notes:

1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at these or any other conditions above

those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rat

-

ing conditions for extended periods may affect reliability.

2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement

conditions, please refer to JESD51-2 standard.

3. VDD and VDDQ must be within 300mV of each other at all times; and VREF must not be greater than

0.6XVDDQ,When VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV.



DRAM Component Operating Temperature Range

Notes:

1. Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM. For mea-

surement conditions, please refer to the JEDEC document JESD51-2.

2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. Dur-

ing operation, the DRAM case temperature must be maintained between 0 - 85

o

C under all operating conditions.

3. Some applications require operation of the DRAM in the Extended Temperature Range between 85

o

C and 95

o

C

case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply:

a. Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9 µs. It

is also possible to specify a component with 1X refresh (tREFI to 7.8µs) in the Extended Temperature Range.

Please refer to the DIMM SPD for option availability

b. If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to use the

Manual Self-Refresh mode with Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7 = 1b).

DDR3 SDRAMs support Extended Temperature Range and please refer to component datasheet and/or the

DIMM SPD for tFEFI requirements in the Extended Temperature Range.

Absolute Maximum DC Ratings

Symbol Parameter Rating Units Notes

VDD

Voltage on VDD pin relative to Vss

- 0.4 V ~ 1.8 V V 1, 3

VDDQ

Voltage on VDDQ pin relative to Vss

- 0.4 V ~ 1.8 V V 1, 3

V

IN

, V

OUT

Voltage on any pin relative to Vss

- 0.4 V ~ 1.8 V V 1

T

STG

Storage Temperature

-55 to +100

o

C1, 2

Temperature Range

Symbol Parameter Rating Units Notes

T

OPER

Normal Operating Temperature Range

0 to 85

o

C 1,2

Extended Temperature Range

85 to 95

o

C1,3

Symbol Parameter

Rating

Units Notes

Min. Typ. Max.

Supply Voltage

Supply Voltage for Output

1. If minimum limit is exceeded, input levels sh

all be governed by DDR3L specifications.

2. Under 1.5V operation, this DDR3L device operates to the

DDR3 specifications under the same speed timings as

defined for this device.

3. Once initialized for DDR3 operation, DDR3L operation may only b

e used if the device is in reset while VDD and

VDDQ are changed for DDR3L operation (see Figure 0).

Rev. 1.1 / Jul. 2013 14

AC & DC Operating Conditions

Recommended DC Operating Conditions

Recommended DC Operating Conditions - DDR3L (1.35V) operation

Symbol Parameter

Rating

Units Notes

Min. Typ. Max.

VDD

Supply Voltage

1.283 1.35 1.45 V 1,2,3,4

VDDQ

Supply Voltage for Output

1.283 1.35 1.45 V 1,2,3,4

Notes:

1. Maximum DC value may not be greater than 1.425V. The DC value is the linear average of VDD/VDDQ (t) over a

very long period of time (e.g., 1 sec).

2. If maximum limit is exceeded, input levels shall be governed by DDR3 specifications.

3. Under these supply voltages, the device operates to this DDR3L specification.

4. Once initialized for DDR3L operation, DDR3 operation may only be used if the device is in reset while VDD and

VDDQ are changed for DDR3 operation (see Figure 0).

Recommended DC Operating Conditions - - DDR3 (1.5V) operation

VDD 1.425 1.5 1.575 V 1,2,3

VDDQ 1.425 1.5 1.575 V 1,2,3

No

tes:

Rev. 1.1 / Jul. 2013 15

Figure 0 - VDD/VDDQ Voltage Switch Between DDR3L and DDR3

NOTE 1: From time point “Td” until “Tk” NOP or DES commands must be applied

between MRS and ZQCL commands.

Ta

CK,CK#

RESET#

Tb Tc Td Te Tf Tg Th Ti Tj Tk

MRS1) 1)MRS MRS

CKE

DON’T CARE

READ MRS

T = 500us

COMMAND

ODT

BA

RTT

MR3 MR1 MR0READ MR2

READ Static LOW in case RTT_Nom is enabled at time Tg, otherwise static HIGH or LOW

VDD, VDDQ (DDR3)

VDD, VDDQ (DDR3L)

ZQCL VALID

VALID

Tmin = 200us

Tmin = 10ns

tCKSRX

Tmin = 10ns

tIS

tIS tIS

tXPR tMRD tMRD tMRD tMOD tZQinit

tDLLK

TIME BREAK

Rev. 1.1 / Jul. 2013 16

AC & DC Input Measurement Levels

AC and DC Logic Input Levels for Single-Ended Signals

AC and DC Input Levels for Single-Ended Command and Address Signals

Notes:

1. For input only pins except RESET, Vref = VrefCA (DC).

2. Refer to "Overshoot and Undershoot Specifications" on page 29.

3. The ac peak noise on V

Ref

may not allow V

Ref

to deviate from V

RefCA(DC)

by more than +/-1% VDD (for refer-

ence: approx. +/- 13.5 mV).

4. For reference: approx. VDD/2 +/- 13.5 mV

5. These levels apply for 1.35 volt (see table above) operation only. If the device is operated at 1.5V (table "Single

Ended AC and DC Input Levels for DQ and DM" on page 17), the respective levels in JESD79-3 (VIH/L.CA(DC100),

VIH/L.CA(AC175), VIH/L.CA(AC150), VIH/L.CA(AC135), VIH/L.CA(AC125) etc.) apply. The 1.5V levels (VIH/

L.CA(DC100), VIH/L.CA(AC175), VIH/L.CA(AC150), VIH/L.CA(AC135), VIH/L.CA(AC125) etc.) do not apply when

the device is operated in the 1.35 voltage range.

Single Ended AC and DC Input Levels for Command and Address

Symbol Parameter

DDR3L-800/1066 DDR3L-1333/1600

Unit Notes

Min Max Min Max

VIH.CA(DC90) DC input logic high Vref + 0.09 VDD Vref + 0.09 VDD V 1

VIL.CA(DC90) DC input logic low VSS Vref - 0.09 VSS Vref - 0.09 V 1

VIH.CA(AC160) AC input logic high Vref + 0.160 Note2 Vref + 0.160 Note2 V 1,2,5

VIL.CA(AC160) AC input logic low Note2 Vref - 0.160 Note2 Vref - 0.160 V 1,2,5

VIH.CA(AC135) AC Input logic high Vref + 0.135 Note2 Vref + 0.135 Note2 V 1,2,5

VIL.CA(AC135) AC input logic low Note2 Vref - 0.135 Note2 Vref - 0.135 V 1,2,5

VIH.CA(AC125)AC Input logic high----V1,2,5

VIL.CA(AC125)AC input logic low----V1,2,5

V

RefCA(DC

)

Reference Voltage for

ADD, CMD inputs

0.49 * VDD 0.51 * VDD 0.49 * VDD 0.51 * VDD V 3,4

Rev. 1.1 / Jul. 2013 17

AC and DC Input Levels for Single-Ended Signals

DDR3 SDRAM will support two Vih/Vil AC levels for DDR3-800 and DDR3-1066s specified in table below.

DDR3 SDRAM will also support corresponding tDS values (Table 43 and Table 50 in “DDR3L Device Opera-

tion”) as well as derating tables Table 46 in “DDR3L Device Operation” depending on Vih/Vil AC levels.

Notes:

1. Vref = VrefDQ (DC).

2. Refer to "Overshoot and Undershoot Specifications" on page 29.

3. The ac peak noise on V

Ref

may not allow V

Ref

to deviate from V

RefDQ(DC)

by more than +/-1% VDD (for reference:

approx. +/- 13.5 mV). 4. For reference: approx. VDD/2 +/- 13.5 mV

4. For reference: approx. VDD/2 +/- 13.5 mV

5. These levels apply for 1.35 volt (table "Single Ended AC and DC Input Levels for Command and Address" on

page 16) operation only. If the device is operated at 1.5V (table above), the respective levels in JESD79-3 (VIH/

L.DQ(DC100), VIH/L.DQ(AC175), VIH/L.DQ(AC150), VIH/L.DQ(AC135) etc.) apply. The 1.5V levels (VIH/

L.DQ(DC100), VIH/L.DQ(AC175), VIH/L.DQ(AC150), VIH/L.DQ(AC135) etc.) do not apply when the device is

operated in the 1.35 voltage range.

Single Ended AC and DC Input Levels for DQ and DM

Symbol Parameter

DDR3L-800/1066 DDR3L-1333/1600

Unit Notes

Min Max Min Max

VIH.DQ(DC90) DC input logic high Vref + 0.09 VDD Vref + 0.09 VDD V 1

VIL.DQ(DC90) DC input logic low VSS Vref - 0.09 VSS Vref - 0.09 V 1

VIH.DQ(AC160) AC input logic high Vref + 0.160 Note2 - - V 1, 2, 5

VIL.DQ(AC160) AC input logic low Note2 Vref - 0.160 - - V 1, 2, 5

VIH.DQ(AC135) AC Input logic high Vref + 0.135 Note2 Vref + 0.135 Note2 V 1, 2, 5

VIL.DQ(AC135) AC input logic low Note2 Vref - 0.135 Note2 Vref - 0.135 V 1, 2, 5

VIH.DQ(AC130) AC Input logic high - - - - V 1, 2, 5

VIL.DQ(AC130) AC input logic low - - - - V 1, 2, 5

V

RefDQ(DC

)

Reference Voltage

for DQ, DM inputs

0.49 * VDD 0.51 * VDD 0.49 * VDD 0.51 * VDD V 3, 4

Rev. 1.1 / Jul. 2013 18

Vref Tolerances

The dc-tolerance limits and ac-noise limits for the reference voltages

VRefCA

and V

RefDQ

are illustrated in

figure below. It shows a valid reference voltage V

Ref

(t) as a function of time. (V

Ref

stands for V

RefCA

and

V

RefDQ

likewise).

V

Ref

(DC) is the linear average of V

Ref

(t) over a very long period of time (e.g. 1 sec). This average has to

meet the min/max requirements in the table "Differential Input Slew Rate Definition" on page 24. Further-

more V

Ref

(t) may temporarily deviate from V

Ref (DC)

by no more than +/- 1% VDD.

Illustration of V

Ref(DC)

tolerance and V

Ref

ac-noise limits

The voltage levels for setup and hold time measurements V

IH(AC)

, V

IH(DC)

, V

IL(AC)

, and V

IL(DC)

are depen-

dent on V

Ref

.

“V

Ref

” shall be understood as V

Ref(DC)

, as defined in figure above.

This clarifies that dc-variations of V

Ref

affect the absolute voltage a signal has to reach to achieve a valid

high or low level and therefore the time to which setup and hold is measured. System timing and voltage

budgets need to account for V

Ref(DC)

deviations from the optimum position within the data-eye of the input

signals.

This also clarifies that the DRAM setup/hold specification and derating values need to include time and

voltage associated with V

Ref

ac-noise. Timing and voltage effects due to ac-noise on V

Ref

up to the speci-

fied limit (+/- 1% of VDD) are included in DRAM timings and their associated deratings.

VDD

VSS

VDD/2

V

Ref(DC)

V

Ref

ac-noise

voltage

time

V

Ref(DC)max

V

Ref(DC)min

V

Ref

(t)

Rev. 1.1 / Jul. 2013 19

AC and DC Logic Input Levels for Differential Signals

Differential signal definition

Definition of differential ac-swing and “time above ac-level” t

DVAC

time

Differential Input Voltage(i.e.DQS - DQS#, CK - CK#)

V

IL.DIFF.AC.MAX

V

IL.DIFF.MAX

0

V

IL.DIFF.MIN

V

IL.DIFF.AC.MIN

t

DVAC

half cycle

t

DVAC

Rev. 1.1 / Jul. 2013 20

Differential swing requirements for clock (CK - CK) and strobe (DQS-DQS)

Notes:

1. Used to define a differential signal slew-rate.

2. For CK - CK use VIH/VIL (ac) of AADD/CMD and VREFCA; for DQS - DQS, DQSL, DQSL, DQSU, DQSU use VIH/VIL

(ac) of DQs and VREFDQ; if a reduced ac-high or ac-low levels is used for a signal group, then the reduced level

applies also here.

3. These values are not defined; however, the single-ended signals Ck, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU

need to be within the respective limits (VIH (dc) max, VIL (dc) min) for single-ended signals as well as the limita-

tions for overshoot and undershoot.Refer to "" on page 28.

note : Rising input signal shall become equal to or greater than VIH(ac) level and Falling input signal shall become

equal to or less than VIL(ac) level.

Differential AC and DC Input Levels

Symbol Parameter

DDR3L-800, 1066, 1333, & 1600

Unit Notes

Min Max

V

IHdiff

Differential input high + 0.180 Note 3 V 1

V

ILdiff

Differential input logic low Note 3 - 0.180 V 1

V

IHdiff (ac)

Differential input high ac 2 x (VIH (ac) - Vref) Note 3 V 2

V

ILdiff (ac)

Differential input low ac Note 3 2 x (VIL (ac) - Vref) V 2

Allowed time before ringback (tDVAC) for CK - CK and DQS - DQS

Slew Rate [V/ns]

DDR3L-800/1066/1333/1600

tDVAC [ps]

@ |VIH/Ldiff (ac)| = 320mV

tDVAC [ps]

@ |VIH/Ldiff (ac)| = 270mV

min max min max

> 4.0 189 - 201 -

4.0 189 - 201 -

3.0 162 - 179 -

2.0 109 - 134

1.8 91 - 119 -

1.6 69 - 100 -

1.4 40 - 76 -

1.2 note - 44 -

1.0 note - note -

< 1.0 note - note -

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Hynix HMT351U7CFR8A-PBT0 Datasheet

Hynix HMT351U7CFR8A-PBT0 Datasheet

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