NXP S08JS Reference guide

Type
Reference guide
HCS08
Microcontrollers
freescale.com
MC9S08JS16
MC9S08JS8
MC9S08JS16L
MC9S08JS8L
Reference Manual
MC9S08JS16RM
Rev. 4
4/2009
Related Documentation:
MC9S08JS16 (Data Sheet)
Contains pin assignments and diagrams, all electrical
specifications, and mechanical drawing outlines.
Find the most current versions of all documents at:
http://www.freescale.com
8-Bit HCS08 Central Processor Unit (CPU)
48 MHz HCS08 CPU (central processor
unit)
24 MHz internal bus frequency
HC08 instruction set with added BGND
instruction
Support for up to 32 interrupt/reset sources
Memory Options
Up to 16 KB of on-chip in-circuit
programmable flash memory with block
protection and security options
Up to 512 bytes of on-chip RAM
256 bytes of USB RAM
Clock Source Options
Clock source options include crystal,
resonator, external clock
MCG (multi-purpose clock generator) —
PLL and FLL; internal reference clock with
trim adjustment
System Protection
Optional computer operating properly
(COP) reset with option to run from
independent 1 kHz internal clock source or
the bus clock
Low-voltage detection
Illegal opcode detection with reset
Illegal address detection with reset
Power-Saving Modes
Wait plus two stops
USB Bootload
Mass erase entire flash array
Partial erase flash array — erase all flash
blocks except for the first 1 KB of flash
Program flash
Peripherals
USB — USB 2.0 full-speed (12 Mbps) with
dedicated on-chip 3.3 V regulator and
transceiver; supports endpoint 0 and up to 6
additional endpoints
SPI — One 8- or 16-bit selectable serial
peripheral interface module with a receive
data buffer hardware match function
SCI — One serial communication interface
module with optional 13-bit break. Full
duplex non-return to zero (NRZ); LIN
master extended break generation; LIN
slave extended break detection; wakeup on
active edge
MTIM — One 8-bit modulo counter with
8-bit prescaler and overflow interrupt
TPM — One 2-channel 16-bit
timer/pulse-width modulator (TPM)
module: selectable input capture, output
compare, and edge-aligned PWM capability
on each channel. Timer module may be
configured for buffered, centered PWM
(CPWM) on all channels
KBI — 8-pin keyboard interrupt module
RTC — Real-time counter with binary- or
decimal-based prescaler
CRC — Hardware CRC generator circuit
using 16-bit shift register; CRC16-CCITT
compliancy with x
16
+x
12
+x5+1 polynomial
Input/Output
Software selectable pullups on ports when
used as inputs
Software selectable slew rate control on
ports when used as outputs
Software selectable drive strength on ports
when used as outputs
Master reset pin and power-on reset (POR)
Internal pullup on RESET, IRQ, and
BKGD/MS pins to reduce customer system
cost
Package Options
24-pin quad flat no-lead (QFN)
20-pin small outline IC package (SOIC)
MC9S08JS16 Features
MC9S08JS16 MCU Series Reference Manual
Covers: MC9S08JS16
MC9S08JS8
MC9S08JS16L
MC9S08JS8L
MC9S08JS16RM
Rev. 4
4/2009
MC9S08JS16 MCU Series Reference Manual, Rev. 4
6 Freescale Semiconductor
Revision History
To provide the most up-to-date information, the revision of our documents on the World Wide Web will
be the most current. Your printed copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://freescale.com
The following revision history table summarizes changes contained in this document.
Revision
Number
Revision
Date
Description of Changes
1 8/27/2008 Initial public release.
2 12/17/2008 Changed the content of register at address 0xFFAE and 0xFFAF in Ta bl e 4 - 4 and added the
description of factory trim value before this table.
Deleted duplicated information in KBI Features section.
Changed the default of PTASE/PTBSE registers after reset to 0.
3 3/6/2009 Updated Figure 4-4 and Figure 4-5.
4 4/24/2009 Added MC9S08JS16L and MC9S08JS8L information.
This product incorporates SuperFlash
®
technology licensed from SST.
Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
© Freescale Semiconductor, Inc., 2008-2009. All rights reserved.
MC9S08JS16 MCU Series Reference Manual, Rev. 4
Freescale Semiconductor 7
List of Chapters
Chapter Number Title Page
Chapter 1 Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Chapter 2 Pins and Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Chapter 3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Chapter 4 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Chapter 5 Resets, Interrupts, and System Configuration . . . . . . . . . . . . . . .63
Chapter 6 Parallel Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Chapter 7 Central Processor Unit (S08CPUV2) . . . . . . . . . . . . . . . . . . . . . . . 87
Chapter 8 Keyboard Interrupt (S08KBIV2) . . . . . . . . . . . . . . . . . . . . . . . . . .107
Chapter 9 Multi-Purpose Clock Generator (S08MCGV1) . . . . . . . . . . . . . . .115
Chapter 10 Modulo Timer (S08MTIMV1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Chapter 11 Real-Time Counter (S08RTCV1) . . . . . . . . . . . . . . . . . . . . . . . . . 157
Chapter 12 Serial Communications Interface (S08SCIV4). . . . . . . . . . . . . . 167
Chapter 13 16-Bit Serial Peripheral Interface (S08SPI16V1) . . . . . . . . . . . .187
Chapter 14 Timer/Pulse-Width Modulator (S08TPMV3) . . . . . . . . . . . . . . . . 215
Chapter 15 Universal Serial Bus Device Controller (S08USBV1) . . . . . . . .243
Chapter 16 Cyclic Redundancy Check Generator (S08CRCV2) . . . . . . . . .275
Chapter 17 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283
MC9S08JS16 MCU Series Reference Manual, Rev. 4
Freescale Semiconductor 9
Contents
Section Number Title Page
Chapter 1
Device Overview
1.1 Introduction .....................................................................................................................................17
1.2 MCU Block Diagram ......................................................................................................................18
1.3 System Clock Distribution ..............................................................................................................19
Chapter 2
Pins and Connections
2.1 Introduction .....................................................................................................................................21
2.2 Device Pin Assignment ..................................................................................................................21
2.3 Recommended System Connections ...............................................................................................22
2.3.1 Power (V
DD
, V
SS
, V
SSOSC
, V
USB33
) ................................................................................24
2.3.2 Oscillator (XTAL, EXTAL) ..............................................................................................24
2.3.3 RESET Pin ........................................................................................................................24
2.3.4 Background/Mode Select (BKGD/MS) ............................................................................25
2.3.5 Bootloader Mode Select (BLMS) .....................................................................................26
2.3.6 USB Data Pins (USBDP, USBDN) ...................................................................................26
2.3.7 General-Purpose I/O and Peripheral Ports ........................................................................26
Chapter 3
Modes of Operation
3.1 Introduction .....................................................................................................................................29
3.2 Features ...........................................................................................................................................29
3.3 Run Mode ........................................................................................................................................29
3.4 Active Background Mode ...............................................................................................................29
3.5 Wait Mode .......................................................................................................................................30
3.6 Stop Modes ......................................................................................................................................31
3.6.1 Stop3 Mode .......................................................................................................................31
3.6.2 Stop2 Mode .......................................................................................................................32
3.6.3 On-Chip Peripheral Modules in Stop Modes ....................................................................33
Chapter 4
Memory
4.1 MC9S08JS16 Series Memory Map .................................................................................................35
4.1.1 Reset and Interrupt Vector Assignments ...........................................................................36
4.2 Register Addresses and Bit Assignments ........................................................................................37
4.3 RAM (System RAM) ......................................................................................................................43
4.4 USB RAM .......................................................................................................................................44
4.5 Bootloader ROM .............................................................................................................................44
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10 Freescale Semiconductor
4.5.1 External Signal Description ..............................................................................................44
4.5.2 Modes of Operation ..........................................................................................................45
4.5.3 Flash Memory Map ...........................................................................................................46
4.5.4 Bootloader Operation ........................................................................................................47
4.6 Flash Memory .................................................................................................................................50
4.6.1 Features .............................................................................................................................50
4.6.2 Program and Erase Time ...................................................................................................50
4.6.3 Program and Erase Command Execution .........................................................................51
4.6.4 Burst Program Execution ..................................................................................................52
4.6.5 Access Errors ....................................................................................................................54
4.6.6 Flash Block Protection ......................................................................................................54
4.6.7 Flash Block Protection Disabled .......................................................................................55
4.6.8 Vector Redirection ............................................................................................................55
4.7 Security ............................................................................................................................................55
4.8 Flash Registers and Control Bits .....................................................................................................57
4.8.1 Flash Clock Divider Register (FCDIV) ............................................................................57
4.8.2 Flash Options Register (FOPT and NVOPT) ....................................................................58
4.8.3 Flash Configuration Register (FCNFG) ...........................................................................59
4.8.4 Flash Protection Register (FPROT and NVPROT) ..........................................................59
4.8.5 Flash Status Register (FSTAT) ..........................................................................................60
4.8.6 Flash Command Register (FCMD) ...................................................................................61
Chapter 5
Resets, Interrupts, and System Configuration
5.1 Introduction .....................................................................................................................................63
5.2 Features ...........................................................................................................................................63
5.3 MCU Reset ......................................................................................................................................63
5.4 Computer Operating Properly (COP) Watchdog .............................................................................64
5.5 Interrupts .........................................................................................................................................65
5.5.1 Interrupt Stack Frame .......................................................................................................66
5.5.2 External Interrupt Request (IRQ) Pin ...............................................................................66
5.5.3 Interrupt Vectors, Sources, and Local Masks ...................................................................67
5.6 Low-Voltage Detect (LVD) System ................................................................................................69
5.6.1 Power-On Reset Operation ...............................................................................................69
5.6.2 Low-Voltage Detection (LVD) Reset Operation ...............................................................69
5.6.3 Low-Voltage Warning (LVW) Interrupt Operation ...........................................................69
5.7 Reset, Interrupt, and System Control Registers and Control Bits ...................................................70
5.7.1 Interrupt Pin Request Status and Control Register (IRQSC) ............................................70
5.7.2 System Reset Status Register (SRS) .................................................................................71
5.7.3 System Background Debug Force Reset Register (SBDFR) ............................................72
5.7.4 System Options Register 1 (SOPT1) ................................................................................73
5.7.5 System Options Register 2 (SOPT2) ................................................................................74
5.7.6 Flash Protection Defeat Register (FPROTD) ...................................................................75
5.7.7 SIGNATURE Register (SIGNATURE) ............................................................................75
5.7.8 System Device Identification Register (SDIDH, SDIDL) ................................................76
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Freescale Semiconductor 11
5.7.9 System Power Management Status and Control 1 Register (SPMSC1) ...........................77
5.7.10 System Power Management Status and Control 2 Register (SPMSC2) ...........................78
Chapter 6
Parallel Input/Output
6.1 Introduction .....................................................................................................................................79
6.2 Port Data and Data Direction ..........................................................................................................79
6.3 Pin Control ......................................................................................................................................80
6.3.1 Internal Pullup Enable ......................................................................................................81
6.3.2 Output Slew Rate Control Enable .....................................................................................81
6.3.3 Output Drive Strength Select ............................................................................................81
6.4 Pin Behavior in Stop Modes ............................................................................................................81
6.5 Parallel I/O and Pin Control Registers ............................................................................................81
6.5.1 Port A I/O Registers (PTAD and PTADD) ........................................................................82
6.5.2 Port A Pin Control Registers (PTAPE, PTASE, PTADS) .................................................82
6.5.3 Port B I/O Registers (PTBD and PTBDD) ........................................................................84
6.5.4 Port B Pin Control Registers (PTBPE, PTBSE, PTBDS) .................................................84
Chapter 7
Central Processor Unit (S08CPUV2)
7.1 Introduction .....................................................................................................................................87
7.1.1 Features .............................................................................................................................87
7.2 Programmers Model and CPU Registers .......................................................................................88
7.2.1 Accumulator (A) ...............................................................................................................88
7.2.2 Index Register (H:X) ........................................................................................................88
7.2.3 Stack Pointer (SP) .............................................................................................................89
7.2.4 Program Counter (PC) ......................................................................................................89
7.2.5 Condition Code Register (CCR) .......................................................................................89
7.3 Addressing Modes ...........................................................................................................................91
7.3.1 Inherent Addressing Mode (INH) .....................................................................................91
7.3.2 Relative Addressing Mode (REL) ....................................................................................91
7.3.3 Immediate Addressing Mode (IMM) ................................................................................91
7.3.4 Direct Addressing Mode (DIR) ........................................................................................91
7.3.5 Extended Addressing Mode (EXT) ..................................................................................92
7.3.6 Indexed Addressing Mode ................................................................................................92
7.4 Special Operations ...........................................................................................................................93
7.4.1 Reset Sequence .................................................................................................................93
7.4.2 Interrupt Sequence ............................................................................................................93
7.4.3 Wait Mode Operation ........................................................................................................94
7.4.4 Stop Mode Operation ........................................................................................................94
7.4.5 BGND Instruction .............................................................................................................95
7.5 HCS08 Instruction Set Summary ....................................................................................................96
MC9S08JS16 MCU Series Reference Manual, Rev. 4
12 Freescale Semiconductor
Chapter 8
Keyboard Interrupt (S08KBIV2)
8.1 Introduction ...................................................................................................................................107
8.1.1 Features ...........................................................................................................................109
8.1.2 Modes of Operation ........................................................................................................109
8.1.3 Block Diagram ................................................................................................................109
8.2 External Signal Description ..........................................................................................................110
8.3 Register Definition ........................................................................................................................110
8.3.1 KBI Status and Control Register (KBISC) .....................................................................110
8.3.2 KBI Pin Enable Register (KBIPE) .................................................................................. 111
8.3.3 KBI Edge Select Register (KBIES) ................................................................................111
8.4 Functional Description ..................................................................................................................112
8.4.1 Edge Only Sensitivity .....................................................................................................112
8.4.2 Edge and Level Sensitivity .............................................................................................112
8.4.3 KBI Pullup/Pulldown Resistors ......................................................................................113
8.4.4 KBI Initialization ............................................................................................................113
Chapter 9
Multi-Purpose Clock Generator (S08MCGV1)
9.1 Introduction ...................................................................................................................................115
9.1.1 Features ...........................................................................................................................117
9.1.2 Modes of Operation ........................................................................................................119
9.2 External Signal Description ..........................................................................................................119
9.3 Register Definition ........................................................................................................................120
9.3.1 MCG Control Register 1 (MCGC1) ...............................................................................120
9.3.2 MCG Control Register 2 (MCGC2) ...............................................................................121
9.3.3 MCG Trim Register (MCGTRM) ...................................................................................122
9.3.4 MCG Status and Control Register (MCGSC) .................................................................123
9.3.5 MCG Control Register 3 (MCGC3) ...............................................................................124
9.4 Functional Description ..................................................................................................................126
9.4.1 Operational Modes ..........................................................................................................126
9.4.2 Mode Switching ..............................................................................................................130
9.4.3 Bus Frequency Divider ...................................................................................................131
9.4.4 Low Power Bit Usage .....................................................................................................131
9.4.5 Internal Reference Clock ................................................................................................131
9.4.6 External Reference Clock ...............................................................................................131
9.4.7 Fixed Frequency Clock ...................................................................................................132
9.5 Initialization / Application Information ........................................................................................132
9.5.1 MCG Module Initialization Sequence ............................................................................132
9.5.2 MCG Mode Switching ....................................................................................................133
9.5.3 Calibrating the Internal Reference Clock (IRC) .............................................................144
Chapter 10
Modulo Timer (S08MTIMV1)
10.1 Introduction ...................................................................................................................................147
MC9S08JS16 MCU Series Reference Manual, Rev. 4
Freescale Semiconductor 13
10.1.1 MTIM Configuration Information ..................................................................................147
10.1.2 Features ...........................................................................................................................149
10.1.3 Modes of Operation ........................................................................................................149
10.1.4 Block Diagram ................................................................................................................150
10.2 External Signal Description ..........................................................................................................150
10.3 Register Definition ........................................................................................................................150
10.3.1 MTIM Status and Control Register (MTIMSC) .............................................................152
10.3.2 MTIM Clock Configuration Register (MTIMCLK) .......................................................153
10.3.3 MTIM Counter Register (MTIMCNT) ...........................................................................154
10.3.4 MTIM Modulo Register (MTIMMOD) ..........................................................................154
10.4 Functional Description ..................................................................................................................155
10.4.1 MTIM Operation Example .............................................................................................156
Chapter 11
Real-Time Counter (S08RTCV1)
11.1 Introduction ...................................................................................................................................157
11.1.1 Features ...........................................................................................................................159
11.1.2 Modes of Operation ........................................................................................................159
11.1.3 Block Diagram ................................................................................................................160
11.2 External Signal Description ..........................................................................................................160
11.3 Register Definition ........................................................................................................................160
11.3.1 RTC Status and Control Register (RTCSC) ....................................................................161
11.3.2 RTC Counter Register (RTCCNT) ..................................................................................162
11.3.3 RTC Modulo Register (RTCMOD) ................................................................................162
11.4 Functional Description ..................................................................................................................162
11.4.1 RTC Operation Example .................................................................................................163
11.5 Initialization/Application Information ..........................................................................................164
Chapter 12
Serial Communications Interface (S08SCIV4)
12.1 Introduction ...................................................................................................................................167
12.1.1 Features ...........................................................................................................................169
12.1.2 Modes of Operation ........................................................................................................169
12.1.3 Block Diagram ................................................................................................................169
12.2 Register Definition ........................................................................................................................172
12.2.1 SCI Baud Rate Registers (SCIBDH, SCIBDL) ..............................................................172
12.2.2 SCI Control Register 1 (SCIC1) .....................................................................................173
12.2.3 SCI Control Register 2 (SCIC2) .....................................................................................174
12.2.4 SCI Status Register 1 (SCIS1) ........................................................................................175
12.2.5 SCI Status Register 2 (SCIS2) ........................................................................................177
12.2.6 SCI Control Register 3 (SCIC3) .....................................................................................178
12.2.7 SCI Data Register (SCID) ...............................................................................................179
12.3 Functional Description ..................................................................................................................179
12.3.1 Baud Rate Generation .....................................................................................................179
12.3.2 Transmitter Functional Description ................................................................................180
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14 Freescale Semiconductor
12.3.3 Receiver Functional Description ....................................................................................181
12.3.4 Interrupts and Status Flags ..............................................................................................183
12.3.5 Additional SCI Functions ...............................................................................................184
Chapter 13
16-Bit Serial Peripheral Interface (S08SPI16V1)
13.1 Introduction ...................................................................................................................................187
13.1.1 SPI Port Configuration Information ...............................................................................187
13.1.2 Features ...........................................................................................................................190
13.1.3 Modes of Operation ........................................................................................................190
13.1.4 Block Diagrams ..............................................................................................................190
13.2 External Signal Description ..........................................................................................................192
13.2.1 SPSCK — SPI Serial Clock ............................................................................................193
13.2.2 MOSI — Master Data Out, Slave Data In ......................................................................193
13.2.3 MISO — Master Data In, Slave Data Out ......................................................................193
13.2.4 SS — Slave Select ..........................................................................................................193
13.3 Register Definition ........................................................................................................................193
13.3.1 SPI Control Register 1 (SPIC1) ......................................................................................193
13.3.2 SPI Control Register 2 (SPIC2) ......................................................................................195
13.3.3 SPI Baud Rate Register (SPIBR) ....................................................................................196
13.3.4 SPI Status Register (SPIS) ..............................................................................................197
13.3.5 SPI Data Registers (SPIDH:SPIDL) ...............................................................................198
13.3.6 SPI Match Registers (SPIMH:SPIML) ...........................................................................199
13.4 Functional Description ..................................................................................................................199
13.4.1 General ............................................................................................................................199
13.4.2 Master Mode ...................................................................................................................200
13.4.3 Slave Mode .....................................................................................................................201
13.4.4 Data Transmission Length ..............................................................................................202
13.4.5 SPI Clock Formats ..........................................................................................................203
13.4.6 SPI Baud Rate Generation ..............................................................................................205
13.4.7 Special Features ..............................................................................................................205
13.4.8 Error Conditions .............................................................................................................207
13.4.9 Low Power Mode Options ..............................................................................................207
13.4.10SPI Interrupts ..................................................................................................................209
13.5 Initialization/Application Information ..........................................................................................210
13.5.1 SPI Module Initialization Example .................................................................................210
Chapter 14
Timer/Pulse-Width Modulator (S08TPMV3)
14.1 Introduction ...................................................................................................................................215
14.2 Features .........................................................................................................................................215
14.3 TPMV3 Differences from Previous Versions ................................................................................217
14.3.1 Migrating from TPMV1 ..................................................................................................219
14.3.2 Features ...........................................................................................................................220
14.3.3 Modes of Operation ........................................................................................................220
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Freescale Semiconductor 15
14.3.4 Block Diagram ................................................................................................................221
14.4 Signal Description .........................................................................................................................223
14.4.1 Detailed Signal Descriptions ..........................................................................................223
14.5 Register Definition ........................................................................................................................227
14.5.1 TPM Status and Control Register (TPMSC) ..................................................................227
14.5.2 TPM-Counter Registers (TPMCNTH:TPMCNTL) ........................................................228
14.5.3 TPM Counter Modulo Registers (TPMMODH:TPMMODL) ........................................229
14.5.4 TPM Channel n Status and Control Register (TPMCnSC) ............................................230
14.5.5 TPM Channel Value Registers (TPMCnVH:TPMCnVL) ..............................................231
14.6 Functional Description ..................................................................................................................233
14.6.1 Counter ............................................................................................................................233
14.6.2 Channel Mode Selection .................................................................................................235
14.7 Reset Overview .............................................................................................................................238
14.7.1 General ............................................................................................................................238
14.7.2 Description of Reset Operation .......................................................................................238
14.8 Interrupts .......................................................................................................................................238
14.8.1 General ............................................................................................................................238
14.8.2 Description of Interrupt Operation .................................................................................239
Chapter 15
Universal Serial Bus Device Controller (S08USBV1)
15.1 Introduction ...................................................................................................................................243
15.1.1 Clocking Requirements ...................................................................................................243
15.1.2 Current Consumption in USB Suspend ..........................................................................243
15.1.3 3.3 V Regulator ...............................................................................................................243
15.1.4 Features ...........................................................................................................................246
15.1.5 Modes of Operation ........................................................................................................246
15.1.6 Block Diagram ................................................................................................................247
15.2 External Signal Description ..........................................................................................................248
15.2.1 USBDP ............................................................................................................................248
15.2.2 USBDN ...........................................................................................................................248
15.2.3 V
USB33 ............................................................................................................................................................. 248
15.3 Register Definition ........................................................................................................................248
15.3.1 USB Control Register 0 (USBCTL0) .............................................................................249
15.3.2 Peripheral ID Register (PERID) .....................................................................................249
15.3.3 Peripheral ID Complement Register (IDCOMP) ............................................................250
15.3.4 Peripheral Revision Register (REV) ...............................................................................250
15.3.5 Interrupt Status Register (INTSTAT) ..............................................................................251
15.3.6 Interrupt Enable Register (INTENB) ..............................................................................252
15.3.7 Error Interrupt Status Register (ERRSTAT) ...................................................................253
15.3.8 Error Interrupt Enable Register (ERRENB) ...................................................................254
15.3.9 Status Register (STAT) ....................................................................................................255
15.3.10Control Register (CTL) ...................................................................................................256
15.3.11Address Register (ADDR) ..............................................................................................257
15.3.12Frame Number Register (FRMNUML, FRMNUMH) ...................................................257
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16 Freescale Semiconductor
15.3.13Endpoint Control Register (EPCTLn, n=0-6) .................................................................258
15.4 Functional Description ..................................................................................................................259
15.4.1 Block Descriptions ..........................................................................................................259
15.4.2 Buffer Descriptor Table (BDT) .......................................................................................264
15.4.3 USB Transactions ...........................................................................................................267
15.4.4 USB Packet Processing ...................................................................................................269
15.4.5 Start of Frame Processing ...............................................................................................270
15.4.6 Suspend/Resume .............................................................................................................271
15.4.7 Resets ..............................................................................................................................272
15.4.8 Interrupts .........................................................................................................................273
Chapter 16
Cyclic Redundancy Check Generator (S08CRCV2)
16.1 Introduction ...................................................................................................................................275
16.1.1 Features ...........................................................................................................................277
16.1.2 Modes of Operation ........................................................................................................277
16.1.3 Block Diagram ................................................................................................................278
16.2 External Signal Description ..........................................................................................................278
16.3 Register Definition .......................................................................................................................278
16.3.1 Memory Map ..................................................................................................................278
16.3.2 Register Descriptions ......................................................................................................279
16.4 Functional Description ..................................................................................................................280
16.4.1 ITU-T (CCITT) Recommendations & Expected CRC Results ......................................280
16.5 Initialization Information ..............................................................................................................281
Chapter 17
Development Support
17.1 Introduction ...................................................................................................................................283
17.1.1 Features ...........................................................................................................................284
17.2 Background Debug Controller (BDC) ..........................................................................................284
17.2.1 BKGD Pin Description ...................................................................................................285
17.2.2 Communication Details ..................................................................................................286
17.2.3 BDC Commands .............................................................................................................289
17.2.4 BDC Hardware Breakpoint .............................................................................................292
17.3 On-Chip Debug System (DBG) ....................................................................................................293
17.3.1 Comparators A and B .....................................................................................................293
17.3.2 Bus Capture Information and FIFO Operation ...............................................................293
17.3.3 Change-of-Flow Information ..........................................................................................294
17.3.4 Tag vs. Force Breakpoints and Triggers .........................................................................294
17.3.5 Trigger Modes .................................................................................................................295
17.3.6 Hardware Breakpoints ....................................................................................................297
17.4 Register Definition ........................................................................................................................297
17.4.1 BDC Registers and Control Bits .....................................................................................297
17.4.2 System Background Debug Force Reset Register (SBDFR) ..........................................299
17.4.3 DBG Registers and Control Bits .....................................................................................300
MC9S08JS16 MCU Series Reference Manual, Rev. 4
Freescale Semiconductor 17
Chapter 1
Device Overview
1.1 Introduction
MC9S08JS16 series MCUs are members of the low-cost, high-performance HCS08 family of 8-bit
microcontroller units (MCUs). All MCUs in the family use the enhanced HCS08 core and are available
with a variety of modules, memory sizes, memory types, and package types.
NOTE
The only difference between MC9S08JS16/MC9S08JS8 and
MC9S08JS16L/MC9S08JS8L is that MC9S08JS16 and MC9S08JS8
support USB bootloader function with voltage above 3.9 V while
MC9S08JS16L and MC9S08JS8L support USB bootloader function at
3.3 V.
Disable internal USB voltage regulator and apply 3.3 V to the V
USB33
pin
when using MC9S08JS16L and MC9S08JS8L for the USB bootloader
function.
Table 1-1 summarizes the peripheral availability per package type for the devices available in the
MC9S08JS16 series.
Table 1-1. MC9S08JS16 Series Features by MCU and Package
Feature MC9S08JS8/MC9S08JS8L MC9S08JS16/MC9S08JS16L
Package 24-pin QFN 20-pin SOIC 24-pin QFN 20-pin SOIC
Flash size (bytes) 8,192 16,384
RAM size (bytes) 512 512
USB RAM (bytes) 256 256
IRQ yes yes
KBI 8 8
SCI yes yes
SPI yes yes
MTIM yes yes
TPM channels 2 2
USB yes yes
CRC yes yes
I/O pins 14 (2 output only) 14 (2 output only)
Chapter 1 Device Overview
MC9S08JS16 MCU Series Reference Manual, Rev. 4
18 Freescale Semiconductor
1.2 MCU Block Diagram
The block diagram in Figure 1-1 shows the structure of the MC9S08JS16 series MCU.
Figure 1-1. MC9S08JS16 Series Block Diagram
V
SS
V
DD
PORT B
8-BIT KEYBOARD
INTERRUPT MODULE (KBI)
USER FLASH (IN BYTES)
USER RAM (IN BYTES)
ON-CHIP ICE AND
DEBUG MODULE (DBG)
HCS08 CORE
CPU
NOTES:
1. Port pins are software configurable with pullup device if input port.
2. Pin contains software configurable pullup/pulldown device if IRQ is enabled (IRQPE = 1).
Pulldown is enabled if rising edge detect is selected (IRQEDG = 1).
3. IRQ does not have a clamp diode to V
DD
. IRQ must not be driven above V
DD
.
4. RESET
contains integrated pullup device if PTB1 enabled as reset pin function (RSTPE = 1).
5. Pin contains integrated pullup device.
6. When pin functions as KBI (KBIPEn = 1) and associated pin is configured to enable the pullup
device, KBEDGn can be used to reconfigure the pullup as a pulldown device.
PTA2/KBIP2/MOSI
PORT A
HCS08 SYSTEM CONTROL
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
VOLTAGE
REGULATOR
COP IRQ LVD
LOW-POWER OSCILLATOR
MULTI-PURPOSE CLOCK
GENERATOR (MCG)
RESET
2-CHANNEL TIMER/PWM
MODULE (TPM)
PTA3/KBIP3/SPSCK
BKGD/MS
IRQ
KBIPx
TCLK
TPMCH0
TPMCH1
EXTAL
XTAL
USB
USB ENDPOINT
MODULE
RAM
FULL SPEED
USB
TRANSCEIVER
USBDP
USBDN
PTA6/KBIP6/RxD
PTA7/KBIP7/TxD
REAL-TIME COUNTER
(RTC)
PTA4/KBIP4/SS
PTA5/KBIP5/TPMCH1
8
SYSTEM
USB 3.3 V VOLTAGE REGULATOR
V
USB33
512
MC9S08JS16 = 16,384
V
SSOSC
PTA0/KBIP0/TPMCH0
PTA1/KBIP1/MISO
PTB3/BLMS
PTB2/BKGD/MS
PTB0/IRQ/TCLK
PTB1/RESET
PTB5/EXTAL
PTB4/XTAL
SERIAL PERIPHERAL
INTERFACE MODULE (SPI)
SPSCK
SS
MISO
MOSI
8-/16-BIT
8-BIT MODULO TIMER
MODULE (MTIM)
INTERFACE MODULE (SCI)
SERIAL COMMUNICATIONS
RxD
TxD
BDC
Bootloader ROM (IN BYTES)
4096
16-BIT Cyclic Redundancy
MODULE (CRC)
Check Generator
MC9S08JS8L = 8,192
MC9S08JS16L = 16,384
MC9S08JS8 = 8,192
Chapter 1 Device Overview
MC9S08JS16 MCU Series Reference Manual, Rev. 4
Freescale Semiconductor 19
Table 1-2 lists the functional versions of the on-chip modules.
1.3 System Clock Distribution
TCLK — External input clock source for TPM and MTIM and is referenced as TPMCLK in Chapter 14,
“Timer/Pulse-Width Modulator (S08TPMV3).”
Figure 1-2. System Clock Distribution Diagram
The MCG supplies the following clock sources:
Table 1-2. Versions of On-Chip Modules
Module Version
Central Processing Unit (CPU) 2
Keyboard Interrupt (KBI) 2
Multi-Purpose Clock Generator (MCG) 1
Real-Time Counter (RTC) 1
Serial Communications Interface (SCI) 4
Serial Peripheral Interface (SPI16) 1
Modulo Timer (MTIM) 1
Timer Pulse-Width Modulator (TPM) 3
Universal Serial Bus (USB) 1
Cyclic Redundancy Check Generator (CRC) 2
Debug Module (DBG) 2
TPM
BDC
CPU
RAM FLASH
2
MCG
MCGOUT
÷2
BUSCLK
MCGLCLK
MCGERCLK
COP
1
The fixed frequency clock (FFCLK) is internally synchronized to the bus clock and must not exceed one half of the
bus clock frequency.
2
Flash and EEPROM have frequency requirements for program and erase operation. See MC9S08JS16 Series
Data Sheet for details.
XOSC
EXTAL XTAL
FFCLK
1
MCGFFCLK
RTC
1 kHz
LPO
TCLK
MCGIRCLK
÷2
USB
USB RAM
SCI
ROM
MTIM
SPI
CRC
Chapter 1 Device Overview
MC9S08JS16 MCU Series Reference Manual, Rev. 4
20 Freescale Semiconductor
MCGOUT — This clock source is used as the CPU, USB RAM and USB module clock, and is
divided by two to generate the peripheral bus clock (BUSCLK). Control bits in the MCG control
registers determine which of the three clock sources is connected:
Internal reference clock
External reference clock
Frequency-locked loop (FLL) or phase-locked loop (PLL) output
See Chapter 9, “Multi-Purpose Clock Generator (S08MCGV1),” for details on configuring the
MCGOUT clock.
MCGLCLK — This clock source is derived from the digitally controlled oscillator (DCO) of the
MCG. Development tools can select this internal self-clocked source to speed up BDC
communications in systems where the bus clock is slow.
MCGIRCLK — This is the internal reference clock and can be selected as the real-time counter
(RTC) clock source. Chapter 9, “Multi-Purpose Clock Generator (S08MCGV1),” explains the
MCGIRCLK in more detail. See Chapter 11, “Real-Time Counter (S08RTCV1),” for more
information regarding the use of MCGIRCLK.
MCGERCLK — This is the external reference clock and can be selected as the clock source of
RTC module. Section 9.4.6, “External Reference Clock,” explains the MCGERCLK in more
detail. See Chapter 11, “Real-Time Counter (S08RTCV1),” for more information regarding the use
of MCGERCLK with this module.
MCGFFCLK — This clock source is divided by two to generate FFCLK after being synchronized
to the BUSCLK. It can be selected as clock source for the TPM or MTIM modules. The frequency
of the MCGFFCLK is determined by the settings of the MCG. See Section 9.4.7, “Fixed Frequency
Clock,” for details.
LPO clock — This clock is generated from an internal low power oscillator that is completely
independent of the MCG module. The LPO clock can be selected as the clock source to the RTC
or COP modules. See Chapter 11, “Real-Time Counter (S08RTCV1),” and Section 5.4, “Computer
Operating Properly (COP) Watchdog,” for details on using the LPO clock with these modules.
TCLK — TCLK is the optional external clock source for the TPM or MTIM modules. The TCLK
must be limited to 1/4th the frequency of the BUSCLK for synchronization. See Chapter 14,
“Timer/Pulse-Width Modulator (S08TPMV3),” for more details.
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NXP S08JS Reference guide

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Reference guide

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