[AKD55XX-A]
<KM117902> 2015/09
GENERAL DESCRIPTION
The AKD55XX-A is an evaluation board for AK55XX, which is 32bit, 8k – 768kHz, 2ch/4ch/6ch/8ch
ADC.
2ch ADC: AK5552, AK5572 4ch ADC: AK5534, AK5554, AK5574
6ch ADC: AK5536, AK5556, AK5576 8ch ADC: AK5538, AK5558, AK5578
The AKD55XX-A is includes the analog input circuit and also has a digital interface transmitter .
Further, the AKD55XX-A can achieve the interface with digital audio systems via BNC-connector.
Ordering guide
AKD55XX-A -- Evaluation board for AK55XX
FUNCTION
DIT with BNC or Optical digital output.
ADC 8ch input is possible.
BNC connector for an external clock input.
AK4118A
(DIT)
AIN1
AIN2
Clock
Generator
+VOP
Input
Buffer
AK55XX
-VOP
TVDD
Regulators
5V
+15V
-15V
AVDD
3.3V
BNC_TX
(OUT)
DSP Data
10pin Header
AIN3
AIN4
Input
Buffer
AIN5
AIN6
Input
Buffer
AIN7
AIN8
Input
Buffer
ｷｬﾉﾝｺﾈｸﾀ
(IN)
OPT_TX
(OUT)
1.8V
VDD18
Figure 1. AKD55XX-A Block Diagram
* Circuit diagram and PCB layout are attached at the end of this manual.
AK55XX Evaluation Board Rev.2
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Evaluation Board Diagram
Board Diagram
J1001 J1002 J1000
SW804
SW800
U6
J300
J302
J303
J301
SW803
SW801
PORT801
PORT700
T1 T2
J1005
J1004
T3
J1006
J1007 J1008 J1003
J1009
J201
J203
J200
J202
J400
J402
J403
J401
J500
J502
J501
J503
T4 T5
SW802 SW805
J600
PORT600
PORT802
PORT803
PORT804
PORT800
J800
SW600
U1
AKD55XX-A-MAIN
AKD55XX-A-SUB
Figure 2. AKD55XX-A Board Diagram
*AKD55XX-A-MAIN: Main Board, AKD55XX-A-SUB: Sub Board
Description
(1) U1 ( AK55XX )
32bit,8k - 768kHz,2ch/4ch/6ch/8ch A/D Converter.
(2) J200,J201,J300,J301,J400,J401,J500,J501 ( Analog data )
Cannon connector : Differential Analog Input
(3) J202,J203,J302,J303,J402,J403,J502,J503 ( Analog data )
BNC Connector : Single-ended Analog Input.
(4) J600 / PORT600 ( Digital data )
BNC Connector / Optical Connector: Digital Output.
(5) J1000, J1001, J1002,J1003,J1004,J1005,J1006,J1007,J1008,J1009 ( Power supply )
Power Supply Connector.
(6) PORT800,PORT801 ( pin header )
Pin header for evaluation (MCLK, BICK, LRCK, SDTO1, SDTO2, SDTO3, SDTO4, TDMIN).
(7) PORT802,PORT803,PORT804 ( pin header )
Pin header for evaluation (DCLK, DSDOL1/R1, DSDOL2/R2, DSDOL3/R3, DSDOL4/R4).
(8) U2 ( AK4118A )
AK4118A has DIT. Transports output data from AK55XX.
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(9) SW800 ( Toggle switch )
Toggle type-switch PDN for AK55XX.
“H” : PDN = High
“L” : PDN = Low
(10) SW801 ( Toggle switch )
Toggle type-switch PDN for AK4118A.
“H” : PDN = High
“L” : PDN = Low
(11) SW802,SW803,SW803,SW805 ( Dip switch)
DIP type-switch for AK55XX.
“H” : Digital signal = High
“L” : Digital Signal = Low
(12) SW600 ( Dip switch (Dual In-line Package switch)
DIP type-switch for AK4118A.
“H” : Digital signal = High
“L” : Digital Signal = Low
(13) J800 ( MCLK external input )
BNC Connector : External Clock Input (MCLK).
(14) T1, T2, T3, T4, T5
Regulator for AK55XX, AK4118A, Logic Circuit.
T1 : Regulated AVDD, VBIAS (5.0V) from +15V.
T2 : Regulated VCC1, VCC2 (5.0V) from +15V.
T3 : Regulated TVDD (3.3V) from +5V.
T4 : Regulated TVDD, VDD18 (1.8V) from +5V
T5 : Regulated D33V (3.3V) from +5V.
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Evaluation Board Manual
Operation sequence
[1] Power supply line settings
[2] Jumped pins settings
[3] DIP switches settings
[4] Toggle switches settings
[5] Register control (Serial control)
[6] Evaluation modes
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[1] Power supply line settings
(1-1) Power supply settings : Used the regulator (T1,T2,T3,T4,T5) <Default>
Set up the power supplied lines :
* Each supply line should be distributed from the power supply unit.
Name Color Setting (Typ) Function Comments Default Settings
J1000 +15V Green +15V Regulator and Op-amp
power supply
Should always be connected +15V
J1001 -15V Blue -15V Regulator and Op-amp
power supply
Should always be connected -15V
J1004 AVDD Red +5.0V AK55XX AVDD 5.0V regulator is used,
R1007=short by default.
When jack is used,
R1008=short.
REG :
(R1007 = short)
J1005 VBIAS Red +5.0V Referential Voltage
source for Op-amp
5.0V regulator is used,
R1009=short by default.
When jack is used,
R1010=short.
REG :
(R1009 = short)
J1009 VCC Red +5.0V 3.3V Regulator power
supply
5.0V regulator is used,
R1011=short by default.
When jack is used,
R1012=short.
REG :
(R1011 = short)
J1006 TVDD Orange +1.8 / +3.3V/ AK4558 TVDD, Logic
IC power supply
3.3V regulator is used,
JP1000=3.3V and
JP1001=REG by default.
When 1.8V regulator is used,
JP1000=1.8V and
JP1001=REG.
When jack is used,
JP1012=JACK short.
REG (3.3V) :
(JP1000=3.3V and
JP1001=REG)
J1007 VDD18 Orange +1.8V AK55XX VDD18 LDO of AK55XX is used,
JP1002=open by default.
When 1.8V regulator is used,
JP1002=REG.
When jack is used,
JP1002=JACK.
Open :
(JP1002=open)
J1008 D3.3V Orange +3.3V AK4118A 3.3V VDD,
Logic IC power supply
3.3V regulator is used,
JP1003=REG by default.
When jack is used,
JP1003=JACK.
REG :
(JP1003=REG)
J1002 AVSS Black 0V Analog ground Should always be connected 0V
J1003 DVSS Black 0V Digital ground Should always be connected 0V
Table 1-1. Power supply line setting ( default : used the regulator )
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(1-2) About jumper for power supply :
The roles of the jumper or the short resistance for each power supply supplied from the regulator are as follows.
Connection of the jumper for power supply :
Name Function Comments Default Settings
R1007
R1008
AVDD1 Select regulator power supply
or jack for AVDD1
AVDD for AK55XX:
R1007=short : 5.0V regulator is used. (default)
R1008=short : Jack is used.
REG :
R1007=short
R1008=open
R1009
R1010
VBIAS Select regulator power supply
or jack for VBIAS
VBIAS for Op-amp Referential Voltage source:
R1009=short : 5.0V regulator is used. (default)
R1010=short : Jack is used.
REG :
R1009=short
R1010=open
R1011
R1012
VCC1,
VCC2
Select regulator power supply
or jack for 5.0V Regulator
power supply
VCC1, VCC2 for 5.0V Regulator power supply:
R1011=short : 5.0V regulator is used. (default)
R1012=short : Jack is used.
REG :
R1011=short
R1012=open
JP1000 TVDD-VSEL Select regulator power supply
3.3V or 1.8V for TVDD
TVDD for AK55XX and Logic IC:
JP1000=3.3V : 3.3V regulator is used. (default)
JP1000=1.8V : 1.8V regulator is used.
3.3V :
JP1000=3.3V
JP1001 TVDD-SEL Select regulator power supply
or jack for TVDD
TVDD for AK55XX and Logic IC:
JP1001=REG : Regulator is used. (default)
JP1001=JACK: Jack is used.
REG :
JP1001=REG
JP1002 VDD18-SEL Select External power supply or
LDO power supply of AK55XX
for VDD18
VDD18 selector for AK55XX:
JP1002=REG : External Power supply of 1.8V regulator is
used.
JP1002=JACK : External Power supply of Jack is used.
JP1002=open : LDO of AK55XX is used. (default)
LDO of AK55XX
:
JP1002=open
JP1003 D33V-SEL Select regulator power supply
or jack for D33V
D33V for AK4118A and Logic IC:
JP1003=REG : 3.3V regulator is used. (default)
JP1003=JACK : Jack is used.
REG :
JP1003=REG
JP1004 VSS-SEL Select connection / separation
between analog ground and
digital ground.
Analog ground / digital ground short or open:
JP1004=open: Separate analog ground AVSS from digital
ground DVSS.
JP1004=short: Connect analog ground AVSS to digital
ground DVSS. (default)
Short :
JP1004=short
Table 1-2. Jumper for power supply
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[2] Jumped pins settings
No Names Default Functions
1 JP600 TXDATA-SEL COAX Select COAX / Optical Connector for TX data of AK4118A.
COAX: COAX for TX data of AK4118A. (default)
OPT: Optical for TX data of AK4118A.
2 PORT805 BICK-SEL DIT Select input / output to AK55XX (U1) BICK
DIT: BICK-AK4118A-T (default)
PORT: Pin Header PORT800-BICK
GND: Connected to DVSS
Open: No signal
3 PORT806 LRCK-SEL DIT Select input / output to AK55XX (U1) LRCK
DIT: LRCK-AK4118A-T (default)
PORT: Pin Header PORT800-LRCK
GND: Connected to DVSS
Open: No signal
4 PORT807 BICK-PHASE THR Select polarity (non-inverted output / inverted output) of
BICK_SEL inputs / outputs.
THR: Non-inverted output. (default)
INV: Inverted output.
5 PORT808 SDTO_SEL SDTO1 Select input to DIT:AK4118A (U6) DAUX
SDTO1: AK55XX-SDTO1 is used. (default)
SDTO2: AK55XX-SDTO2 is used.
SDTO3: AK55XX-SDTO3 is used.
SDTO4: AK55XX-SDTO4 is used.
open: No signal for DAUX-AK4118A-T
6 PORT809 TDMI-SEL Open Select connect to AK55XX (U1) TDMI
Open: No signal for TDMIN (default)
Short: Pin Header PORT801-TDMIN
7 PORT810 MCKI-SEL DIT Select input to AK55XX (U1) MCLK
DIT: MCLK-AK4118A-T (default)
PORT: Pin Header PORT800-MCLK
EXT: External MCLK (JACK:J800 EXT) input.
GND: Connected to DVSS
8 JP800 EXT Open Open: No input (default)
Short: External MCLK (JACK:J800 EXT) input.
9 JP900 PS-SEL1 SDA/CDTI Select input / output to AK55XX (U1) CKS0/SDA/CDTI
SDA/CDTI:
SDA/CDTI signal input / output to AK55XX. (default)
CKS0:
CKS0 signal of SW803 input to AK55XX.
10 JP901 PS-SEL2 CAD0-I2C/CSN Select input to AK55XX (U1) CKS1/CAD0-I2C/CSN
CAD0-I2C/CSN:
CAD0-I2C/CSN signal input to AK55XX. (default)
CKS1:
CKS1 signal of SW803 input to AK55XX.
11 JP902 PS-SEL3 CAD0-I2C Select input to JP901 CAD0-I2C/CSN
CAD0-I2C:
CAD0-I2C signal of SW802 input to JP901. (default)
CSN:
CSN signal of SW802 input to JP901.
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12 JP903 PS-SEL4 SCL/CCLK Select input to AK55XX (U1) CKS2/SCL/CCLK
SCL/CCLK:
SCL/CCLK signal input to AK55XX. (default)
CKS2:
CKS2 signal of SW803 input to AK55XX.
13 JP904 PS-SEL5 CAD1 Select input to AK55XX (U1) CKS3/CAD1
CAD1: CAD1 signal input to AK55XX. (default)
CKS3: CKS3 signal of SW803 input to AK55XX.
14 JP905 PS-SEL6 PS Select input to AK55XX (U1) PS/CAD0-SPI
PS:
PS signal input to AK55XX. (default)
CAD0-SPI:
CAD0-SPI signal of SW802 input to AK55XX.
15 JP1000 TVDD-VSEL 3.3V Select power supply voltage of TVDD
3.3V: Regulator T3 (+5V => 3.3V) (default)
1.8V: Regulator T4 (+5V => 1.8V)
16 JP1001 TVDD-SEL TVDD Select power supply to TVDD
REG: Regulator T3/T4 (default)
JACK: Power supply jack J1006 “TVDD”
17 JP1002 VDD18-SEL REG Select power supply to VDD18
REG: Regulator T4 (default)
JACK: Power supply jack J1007 “VDD18”
18 JP1003 D33V-SEL REG Select power supply to D33V
REG: Regulator T5 (+5V => 3.3V) (default)
JACK: Power supply jack J1008 “D3.3V”
19 JP1004 VSS-SEL Short Select connection / separation between analog ground AVSS
and digital ground DVSS.
Open:
Separate analog ground from digital ground
Short:
Connect analog ground to digital ground (default)
Table 2. Main board Jumper pin setting
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[3] DIP switches settings
(3-1). Setting for SW600 (Sets AK4118A (U6) audio format and master clock setting)
No. Switch Name Function default
1 DIF2 Set-up of DIF0 pin. H
2 DIF1 Set-up of DIF1 pin. L
3 DIF0 Set-up of DIF2 pin. H
4 OCKS1 Set-up of OCKS1 pin. H
5 OCKS0 Set-up of OCKS0 pin. L
Table 3-1. SW600 Setting (AK4118A)
Mode
DIF2 pin
SW600_1
DIF1 pin
SW600_2
DIF0 pin
SW600_3
DAUX SDTO
LRCK BICK
DIF2 bit DIF1 bit DIF0 bit I/O I/O
0 0 0 0
24bit, Left
justified
16bit, Right
justified
H/L O 64fs O
1 0 0 1
24bit, Left
justified
18bit, Right
justified
H/L O 64fs O
2 0 1 0
24bit, Left
justified
20bit, Right
justified
H/L O 64fs O
3 0 1 1
24bit, Left
justified
24bit, Right
justified
H/L O 64fs O
4 1 0 0
24bit, Left
justified
24bit, Left
justified
H/L O 64fs O
5 1 0 1 24bit, I
2
S 24bit, I
2
S L/H O 64fs O default
6 1 1 0
24bit, Left
justified
24bit, Left
justified
H/L I 64-128fs I
7 1 1 1 24bit, I
2
S 24bit, I
2
S L/H I 64-128fs I
Table 3-2. Audio format (AK4118A)
OCKS1 pin
SW600_4
OCKS0 pin
SW600_5
(X’tal) MCKO1 MCKO2 fs (max)
OCKS1 bit OCKS0 bit
0 0 256fs 256fs 256fs 96 kHz
0 1 256fs 256fs 128fs 96 kHz
1 0 512fs 512fs 256fs 48 kHz
default
1 1 128fs 128fs 64fs 192 kHz
Table 3-3. Master Clock Frequency Select (AK4118A)
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(3-2). Setting for SW802 (Sets AK55XX (U1) )
No. Switch Name Function default
1 TEST TEST Enable. L
2 PW0 ADC Power Management and Monaural / Stereo select. H
3 PW1 ADC Power Management and Monaural / Stereo select. H
4 PW2 ADC Power Management and Monaural / Stereo select. H
5 MSN
Master/Slave select.
L: Slave Mode
H: Master Mode
L
6 CAD0-SPI
Chip Address0 Pin in 3-wire serial control mode.
(I2C pin =”L”)
L
7 CAD0-I2C
Chip Address0 Pin in I2C bus serial control mode.
(I2C pin =”H”, PS pin =”L”)
L
8 CAD1
Chip Address1 Pin in I2C bus or 3-wire serial control mode.
(3-wire : I2C pin =”L”)
(I2C bus : I2C =”H”, PS pin ”L”)
L
Table 3-4. SW802 Setting
(3-3). Setting for SW803 (Sets AK55XX (U1) )
No. Switch Name Function default
1 CKS0 Clock Mode Setting #0 L
2 CKS1 Clock Mode Setting #1 H
3 CKS2 Clock Mode Setting #2 H
4 CKS3 Clock Mode Setting #3 L
5 DIF0/DSDSEL0
DIF0 : Audio Data Format select in PCM Mode
L: MSB justified
H: I2S
DSDSEL0 : DSD Sampling Rate Control in DSD Mode
H
6 DIF1/DSDSEL1
DIF1 : Audio Data Format select in PCM Mode
L: 24-bit Mode
H: 32-bit Mode
DSDSEL1 : DSD Sampling Rate Control in DSD Mode
L
7 SLOW/DCKB
SLOW : Slow Roll-OFF Digital Filter select in PCM Mode
DCLKB : Polarity of DCLK in DSD Mode
L
8 SD/PMOD
SD : Short Delay Digital Filter select in PCM Mode
PMOD : DSD Phase Modulation Mode select in DSD Mode
L
Table 3-5. SW803 Setting
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(3-4). Setting for SW804 (Sets AK55XX (U1) )
No. Switch Name Function default
1 LDOE
LDO Enable
L: LDO Disable
H: LDO Enable
H
2 ODP Output Data Placement Select. L
3 TDM0 TDM Interface Format select #0 L
4 TDM1 TDM Interface Format select #1 L
5 PS
Control mode select (I2C pin =”H”)
L: I2C Bus serial control mode
H: Parallel control mode
L
6 I2C
Control mode select
L: 3-wire serial control mode
H: I2C Bus serial control mode
H
7 DP
DSD Mode Enable
L: PCM Mode
H: DSD Mode
L
8 HPFE/DCKS
HPFE : High Pass Filter Enable
L: HPF Disable
H: HPF Enable
DCKS : Master Clock Frequency select at DSD Mode (DSD only)
L: 512fs
H: 768fs
H
Table 3-6. SW804 Setting
(3-5). Setting for SW805 (Sets AK55XX (U1) )
No. Switch Name Function default
1 - No used L
2 - No used L
3 - No used L
4 - No used L
5 - No used L
6 - No used L
7 - No used L
8 - No used L
Table 3-7. SW805 Setting
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Parallel Mode, ODP pin = “L”, Normal Output (AK55X8)
PW0 pin
SW802_2
PW1 pin
SW802_3
PW2 pin
SW802_4
Slot 8 Slot 7 Slot 6 Slot 5 Slot 4 Slot 3 Slot 2 Slot 1
L L L
All “0” All “0” All “0” All “0” All “0” All “0” All “0” All “0”
L L H
(CH7+8)
/2
(CH7+8)
/2
All “0” All “0”
(CH3+4)
/2
(CH3+4)
/2
(CH1+2)
/2
(CH1+2)
/2
L H L
All “0” All “0”
(CH5+6)
/2
(CH5+6)
/2
(CH3+4)
/2
(CH3+4)
/2
(CH1+2)
/2
(CH1+2)
/2
L H H
(CH7+8)
/2
(CH7+8)
/2
(CH5+6)
/2
(CH5+6)
/2
(CH3+4)
/2
(CH3+4)
/2
(CH1+2)
/2
(CH1+2)
/2
H L L
All “0” CH7 CH6 CH5 CH4 CH3 CH2 CH1
H L H
CH8 CH7 All “0” All “0” CH4 CH3 CH2 CH1
H H L
All “0” All “0” CH6 CH5 CH4 CH3 CH2 CH1
H H H
CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1
default
Table 3-8-1. Channel Power & Mono Mode Select (AK55X8)
Parallel Mode, ODP pin = “H”, Normal Output (AK55X8)
PW0 pin
SW802_2
PW1 pin
SW802_3
PW2 pin
SW802_4
Slot 8 Slot 7 Slot 6 Slot 5 Slot 4 Slot 3 Slot 2 Slot 1
L L L
All “0” All “0” All “0” All “0” All “0” All “0” All “0” All “0”
L L H
All “0”
or
TDMIN
All “0”
or
TDMIN
All “0”
or
TDMIN
All “0”
or
TDMIN
All “0”
or
TDMIN
All “0”
or
TDMIN
(CH5+6
7+8)/4
(CH1+2
+3+4)/4
L H L
All “0”
or
TDMIN
All “0”
or
TDMIN
All “0”
or
TDMIN
All “0”
or
TDMIN
(CH7+8)
/2
(CH5+6)
/2
(CH3+4)
/2
(CH1+2)
/2
L H H
All “0”
or
TDMIN
All “0”
or
TDMIN
All “0”
or
TDMIN
All “0”
or
TDMIN
All “0”
or
TDMIN
All “0”
or
TDMIN
All “0”
or
TDMIN
(CH1+2+
3+4+5+6
+7+8)/8
H L L
CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1
H L H
All “0”
or
TDMIN
All “0”
or
TDMIN
All “0”
or
TDMIN
All “0”
or
TDMIN
All “0”
or
TDMIN
All “0”
or
TDMIN
(CH5+6
7+8)/4
(CH1+2
+3+4)/4
H H L
All “0”
or
TDMIN
All “0”
or
TDMIN
All “0”
or
TDMIN
All “0”
or
TDMIN
(CH7+8)
/2
(CH5+6)
/2
(CH3+4)
/2
(CH1+2)
/2
H H H
All “0”
or
TDMIN
All “0”
or
TDMIN
All “0”
or
TDMIN
All “0”
or
TDMIN
All “0”
or
TDMIN
All “0”
or
TDMIN
All “0”
or
TDMIN
(CH1+2+
3+4+5+6
+7+8)/8
Table 3-8-2. Channel Power & Mono Mode Select (AK55X8)
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Parallel Mode, ODP pin = “L”, Normal Output (AK55X6)
PW0 pin
SW802_2
PW1 pin
SW802_3
PW2 pin
SW802_4
Slot 6 Slot 5 Slot 4 Slot 3 Slot 2 Slot 1
L L L
All “0” All “0” All “0” All “0” All “0” All “0”
L L H
CH6 All “0”
(CH3+4)/
2
(CH3+4)/
2
(CH1+2)/
2
(CH1+2)/
2
L H L
All “0” CH5
(CH3+4)/
2
(CH3+4)/
2
(CH1+2)/
2
(CH1+2)/
2
L H H
(CH5+6)/
2
(CH5+6)/
2
(CH3+4)/
2
(CH3+4)/
2
(CH1+2)/
2
(CH1+2)/
2
H L L
All “0” All “0” CH4 CH3 CH2 CH1
H L H
CH6 All “0” CH4 CH3 CH2 CH1
H H L
All “0” CH5 CH4 CH3 CH2 CH1
H H H
CH6 CH5 CH4 CH3 CH2 CH1
default
Table 3-8-3. Channel Power & Mono Mode Select (AK55X6)
Parallel Mode, ODP pin = “H”, Normal Output (AK55X6)
PW0 pin
SW802_2
PW1 pin
SW802_3
PW2 pin
SW802_4
Slot 6 Slot 5 Slot 4 Slot 3 Slot 2 Slot 1
L L L
All “0” All “0” All “0” All “0” All “0” All “0”
L L H
All “0”
or
TDMIN
All “0”
or
TDMIN
All “0”
or
TDMIN
All “0”
or
TDMIN
(CH5+6)
/2
(CH1+2
+3+4)/4
L H L
All “0”
or
TDMIN
All “0”
or
TDMIN
(CH5+6)
/2
(CH5+6)
/2
(CH3+4)
/2
(CH1+2)
/2
L H H
All “0”
or
TDMIN
All “0”
or
TDMIN
All “0”
or
TDMIN
All “0”
or
TDMIN
All “0”
or
TDMIN
(CH1+2+
3+4+5+
6)/6
H L L
CH6 CH5 CH4 CH3 CH2 CH1
H L H
All “0”
or
TDMIN
All “0”
or
TDMIN
All “0”
or
TDMIN
All “0”
or
TDMIN
(CH5+6)
/2
(CH1+2
+3+4)/4
H H L
All “0”
or
TDMIN
All “0”
or
TDMIN
(CH5+6)
/2
(CH5+6)
/2
(CH3+4)
/2
(CH1+2)
/2
H H H
All “0”
or
TDMIN
All “0”
or
TDMIN
All “0”
or
TDMIN
All “0”
or
TDMIN
All “0”
or
TDMIN
(CH1+2+
3+4+5+
6)/6
Table 3-8-4. Channel Power & Mono Mode Select (AK55X6)
- 13-
[AKD55XX-A]
<KM117902> 2015/09
Parallel Mode, ODP pin = “L”, Normal Output (AK55X4)
PW0 pin
SW802_2
PW1 pin
SW802_3
PW2 pin
SW802_4
Slot 4 Slot 3 Slot 2 Slot 1
L L L
All “0” All “0” All “0” All “0”
L L H
(CH3+4)
/2
(CH3+4)
/2
All “0” All “0”
L H L
All “0” All “0”
(CH1+2)
/2
(CH1+2)
/2
L H H
(CH3+4)
/2
(CH3+4)
/2
(CH1+2)
/2
(CH1+2)
/2
H L L
All “0” CH3 CH2 CH1
H L H
CH4 CH3 All “0” All “0”
H H L
All “0” All “0” CH2 CH1
H H H
CH4 CH3 CH2 CH1
default
Table 3-8-5. Channel Power & Mono Mode Select (AK55X4)
Parallel Mode, ODP pin = “H”, Normal Output (AK55X4)
PW0 pin
SW802_2
PW1 pin
SW802_3
PW2 pin
SW802_4
Slot 4 Slot 3 Slot 2 Slot 1
L L L
All “0” All “0” All “0” All “0”
L L H
All “0”
or
TDMI
All “0”
or
TDMI
(CH3+4)
/2
(CH1+2)
/2
L H L
CH4 CH3 CH2 CH1
L H H
All “0”
or
TDMI
All “0”
or
TDMI
All “0”
or
TDMI
(CH1+2
+3+4)/4
H L L
CH4 CH3 CH2 CH1
H L H
All “0”
or
TDMI
All “0”
or
TDMI
(CH3+4)
/2
(CH1+2)
/2
H H L
CH4 CH3 CH2 CH1
H H H
All “0”
or
TDMI
All “0”
or
TDMI
All “0”
or
TDMI
(CH1+2
+3+4)/4
Table 3-8-6. Channel Power & Mono Mode Select (AK55X4)
- 14-
[AKD55XX-A]
<KM117902> 2015/09
Parallel Mode, ODP pin = “L”, Normal Output (AK55X2)
PW0 pin
SW802_2
PW1 pin
SW802_3
PW2 pin
SW802_4
Slot 2 Slot 1
L L L
All “0” All “0”
L L H
CH2 All “0”
L H L
All “0” CH1
L H H
(CH2+1)
/2
(CH2+1)
/2
H L L
All “0” All “0”
H L H
CH2 All “0”
H H L
All “0” CH1
H H H
CH2 CH1
default
Table 3-8-7. Channel Power & Mono Mode Select (AK55X2)
Parallel Mode, ODP pin = “H”, Normal Output (AK55X2)
PW0 pin
SW802_2
PW1 pin
SW802_3
PW2 pin
SW802_4
Slot 2 Slot 1
L L L
All “0” All “0”
L L H
(CH2+1)
/2
(CH2+1)
/2
L H L
CH2 CH1
L H H
All “0”
or
TDMI
(CH2+1)
/2
H L L
CH2 CH1
H L H
(CH2+1)
/2
(CH2+1)
/2
H H L
CH2 CH1
H H H
All “0”
or
TDMI
(CH2+1)
/2
Table 3-8-8. Channel Power & Mono Mode Select (AK55X2)
- 15-
[AKD55XX-A]
<KM117902> 2015/09
CKS3 pin
SW803-4
CKS2 pin
SW803-3
CKS1 pin
SW803-2
CKS0 pin
SW803-1
MSN pin
SW802-5
MCLK
Frequency
fs Range
L(0) L(0) L(0) L(0)
L(0) 128fs
24M
Quad Speed Mode
108kHz fs 216kHz
H(1)
L(0) L(0) L(0) H(1)
L(0) 192fs
36M
Quad Speed Mode
108kHz fs 216kHz
H(1)
L(0) L(0) H(1) L(0)
L(0) 256fs
12M
Normal Speed Mode
8kHz fs 54kHz
H(1)
L(0) L(0) H(1) H(1)
L(0) 256fs
24M
Double Speed Mode
54kHz fs 108kHz
H(1)
L(0) H(1) L(0) L(0)
L(0) 384fs
36M
Double Speed Mode
54kHz fs 108kHz
H(1)
L(0) H(1) L(0) H(1)
L(0) 384fs
18M
Normal Speed Mode
8kHz fs 54kHz
H(1)
L(0) H(1) H(1) L(0)
L(0) 512fs
24M
Normal Speed Mode
8kHz fs 54kHz
default
H(1)
L(0) H(1) H(1) H(1)
L(0) 768fs
36M
Normal Speed Mode
8kHz fs 54kHz
H(1)
H(1) L(0) L(0) L(0)
L(0) 64fs
24M
Oct Speed Mode
fs = 384kHz
H(1)
H(1) L(0) L(0) H(1)
L(0) 32fs
24M
Hex Speed Mode
fs = 768kHz
H(1)
H(1) L(0) H(1) L(0)
L(0) 96fs
36M
Oct Speed Mode
fs = 384kHz
H(1)
H(1) L(0) H(1) H(1)
L(0) 48fs
36M
Hex Speed Mode
fs = 768kHz
H(1)
H(1) H(1) L(0) L(0)
L(0) 64fs
49.1M
Hex Speed Mode
fs = 768kHz
H(1)
H(1) H(1) L(0) H(1)
L(0)
1024fs
32M
Normal Speed Mode
8kHz ≤ fs ≤ 32kHz
H(1)
H(1) H(1) H(1) L(0)
L(0)
NA NA
H(1)
H(1) H(1) H(1) H(1)
L(0)
Auto
8kHz fs 216kHz
-
Table 3-9. MCLK Frequency Select (AK55XX)
- 16-
[AKD55XX-A]
<KM117902> 2015/09
DSDSEL1 pin
SW803-6
DSDSEL0 pin
SW803-5
Frequency Mode DSD Sampling Frequency
fs=32kHz fs=44.1kHz fs=48kHz
L(0) L(0) 64fs 2.048MHz 2.8224MHz 3.072MHz default
L(0) H(1) 128fs 4.096MHz 5.6448MHz 6.144MHz
H(1) L(0) 256fs 8.192MHz 11.2896MHz 12.288MHz
H(1) H(1) -
Reserved
(8.192MHz)
Reserved
(11.2896MHz)
Reserved
(12.288MHz)
Table 3-10. DSD Sampling Frequency Select (AK55XX)
No.
Multiplex
Mode
Speed
Mode
TDM1
SW804-4
TDM0
SW804-3
MSN
SW802-5
DIF1
SW803-6
DIF0
SW803-5
SDTO
LRCK BICK MCLK
Pol. I/O Freq. I/O Freq. I/O
0
Normal
Normal
Double
Quad
L(0) L(0)
L(0)
L(0) L(0) 24-bit, MSB H/L I 48-128fs I 128-1024fs I
1
L(0) H(1)
24-bit, I
2
S
L/H I 48-128fs I 128-1024fs I
default
2
H(1) L(0) 32-bit, MSB H/L I 64-128fs I 128-1024fs I
3
H(1) H(1)
32-bit, I
2
S
L/H I 64-128fs I 128-1024fs I
4
H(1)
L(0) L(0) 24-bit, MSB H/L O 64fs O 128-1024fs I
5
L(0) H(1)
24-bit, I
2
S
L/H O 64fs O 128-1024fs I
6
H(1) L(0) 32-bit, MSB H/L O 64fs O 128-1024fs I
7
H(1) H(1)
32-bit, I
2
S
L/H O 64fs O 128-1024fs I
8
OCT
HEX
L(0) L(0)
L(0)
* L(0) 16-bit, MSB
I 32fs I 32-96fs I
9
* H(1)
16-bit, I
2
S
I 32fs I 32-96fs I
10
* L(0) 24-bit, MSB
I 48fs I 32-96fs I
11
* H(1)
24-bit, I
2
S
I 48fs I 32-96fs I
12
L(0) L(0) 24-bit, MSB
I 64fs I 32-96fs I
13
L(0) H(1)
24-bit, I
2
S
I 64fs I 32-96fs I
14
H(1) L(0) 32-bit, MSB
I 64fs I 32-96fs I
15
H(1) H(1)
32-bit, I
2
S
I 64fs I 32-96fs I
16
H(1)
* L(0) 16-bit, MSB
O 32fs O 32fs I
17
* H(1)
16-bit, I
2
S
O 32fs O 32fs I
18
* L(0) 24-bit, MSB
O 48fs O 48fs I
19
* H(1)
24-bit, I
2
S
O 48fs O 48fs I
20
L(0) L(0) 24-bit, MSB
O 64fs O 64-96fs I
21
L(0) H(1)
24-bit, I
2
S
O 64fs O 64-96fs I
22
H(1) L(0) 32-bit, MSB
O 64fs O 64-96fs I
23
H(1) H(1) 32-bit, I2S
O 64fs O 64-96fs I
Table 3-11. Audio Interface Format Select ( Normal mode, OCT/HEX mode) : PCM Mode (AK55XX)
- 17-
[AKD55XX-A]
<KM117902> 2015/09
No.
Multiplex
Mode
Speed
Mode
TDM1
SW804-4
TDM0
SW804-3
MSN
SW802-5
DIF1
SW803-6
DIF0
SW803-5
SDTO
LRCK BICK MCLK
Edg. I/O Freq. I/O Freq. I/O
24
TDM128
Normal
Double
Quad
L(0) H(1)
L(0)
L(0)
L(0) 24-bit, MSB
I 128fs I 128-1024fs I
25
L(0)
H(1)
24-bit, I
2
S
I 128fs I 128-1024fs I
26
H(1)
L(0) 32-bit, MSB
I 128fs I 128-1024fs I
27
H(1)
H(1)
32-bit, I
2
S
I 128fs I 128-1024fs I
28
H(1)
L(0)
L(0) 24-bit, MSB
O 128fs O 128-1024fs I
29
L(0)
H(1)
24-bit, I
2
S
O 128fs O 128-1024fs I
30
H(1)
L(0) 32-bit, MSB
O 128fs O 128-1024fs I
31
H(1)
H(1)
32-bit, I
2
S
O 128fs O 128-1024fs I
32
TDM256
Normal
Double
H(1) L(0)
L(0)
L(0)
L(0) 24-bit, MSB
I 256fs I 256-1024fs I
33
L(0)
H(1)
24-bit, I
2
S
I 256fs I 256-1024fs I
34
H(1)
L(0) 32-bit, MSB
I 256fs I 256-1024fs I
35
H(1)
H(1)
32-bit, I
2
S
I 256fs I 256-1024fs I
36
H(1)
L(0)
L(0) 24-bit, MSB
O 256fs O 256-1024fs I
37
L(0)
H(1)
24-bit, I
2
S
O 256fs O 256-1024fs I
38
H(1)
L(0) 32-bit, MSB
O 256fs O 256-1024fs I
39
H(1)
H(1)
32-bit, I
2
S
O 256fs O 256-1024fs I
40
TDM512 Normal H(1) H(1)
L(0)
L(0)
L(0) 24-bit, MSB
I 512fs I 512-1024fs I
41
L(0)
H(1)
24-bit, I
2
S
I 512fs I 512-1024fs I
42
H(1)
L(0) 32-bit, MSB
I 512fs I 512-1024fs I
43
H(1)
H(1)
32-bit, I
2
S
I 512fs I 512-1024fs I
44
H(1)
L(0)
L(0) 24-bit, MSB
O 512fs O 512-1024fs I
45
L(0)
H(1)
24-bit, I
2
S
O 512fs O 512-1024fs I
46
H(1)
L(0) 32-bit, MSB
O 512fs O 512-1024fs I
47
H(1)
H(1)
32-bit, I
2
S
O 512fs O 512-1024fs I
Table 3-12. Audio Interface Format Select ( TDM mode) : PCM Mode (AK55XX)
SD
SW803-8
SLOW
SW803-7
Filter
L L Sharp Roll-off Filter default
L H Slow Roll-off Filter
H L Short Delay Sharp Roll-off Filter
H H Short Delay Slow Roll-off Filter
Table 3-13. Digital Filter Select : PCM Mode (AK55XX)
LDOE
SW804-1
PDN
SW800
LDO VDD18 pin
TVDD pin
Power Supply
L L OFF External Power Supply 1.7~1.98V 1.7~1.98V
L H OFF External Power Supply 1.7~1.98V 1.7~1.98V
H L OFF
Internal 500 Pull Down
3.0~3.6V
H H ON LDO Power Output 3.0~3.6V default
Table 3-14. LDO Select (AK55XX)
- 18-
[AKD55XX-A]
<KM117902> 2015/09
I2C pin
SW804-6
PS pin
SW804-5
Control Mode
L L 3-wire Serial
L H 3-wire Serial
H L I
2
C Bus default
H H Parallel
Table 3-15. Control Mode Select (AK55XX)
- 19-
[AKD55XX-A]
<KM117902> 2015/09
[4] Toggle switches settings
Up=”H”, Down=”L”
[SW800] ( Power Down (PDN) for AK55XX):
Power Down (PDN) Switch for AK55XX
Reset AK55XX (U1) once by brining SW800 to “L” once upon power-up.
Keep “H” when AK55XX is in use; keep “L” when AK55XX is not in use.
[SW801] ( Power Down (PDN) for AK4118A):
Power Down (PDN) Switch for AK4118A
Reset AK4118A (U6) once by brining SW801 to “L” once upon power-up.
Keep “H” when AK4118A is in use; keep “L” when AK4118A is not in use.
- 20-
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