MPC5642A Microcontroller Reference Manual, Rev. 2.1
Freescale Semiconductor 1
Devices Supported:
MPC5642A
MPC5642A Microcontroller
Reference Manual
Supports MPC5642A
MPC5642ARM
Rev. 2.1
27 Sep 2012
MPC5642A Microcontroller Reference Manual, Rev. 2.1
2 Freescale Semiconductor
MPC5642A Microcontroller Reference Manual, Rev. 2.1
Freescale Semiconductor 3
Chapter 1
Introduction
1.1 The MPC5642A microcontroller family .........................................................................................25
1.2 MPC5642A device comparison ......................................................................................................26
1.3 Device Block Diagramshows a top-level block diagram of the MPC5642A. ................................29
1.4 Feature summary .............................................................................................................................30
1.5 Feature Details .................................................................................................................................31
1.5.1 e200z4 core .......................................................................................................................31
1.5.2 Crossbar switch (XBAR) ..................................................................................................32
1.5.3 Enhanced direct memory access (eDMA) ........................................................................33
1.5.4 Interrupt controller (INTC) ...............................................................................................33
1.5.5 Memory protection unit (MPU) ........................................................................................34
1.5.6 Frequency-modulated phase-locked loop (FMPLL) .........................................................35
1.5.7 System integration unit (SIU) ...........................................................................................36
1.5.8 Flash memory ...................................................................................................................37
1.5.9 Static random access memory (SRAM) ............................................................................37
1.5.10 Boot assist module (BAM) ...............................................................................................38
1.5.11 Enhanced modular input/output system (eMIOS) ............................................................38
1.5.12 Second generation enhanced time processing unit (eTPU2) ............................................39
1.5.13 Reaction module (REACM) .............................................................................................41
1.5.14 Enhanced queued analog-to-digital converter (eQADC) ..................................................41
1.5.15 Deserial serial peripheral interface (DSPI) .......................................................................43
1.5.16 Enhanced serial communications interface (eSCI) ...........................................................44
1.5.17 Controller area network (FlexCAN) .................................................................................44
1.5.18 FlexRay .............................................................................................................................45
1.5.19 System timers ....................................................................................................................46
1.5.20 Software watchdog timer (SWT) ......................................................................................47
1.5.21 Cyclic redundancy check (CRC) module .........................................................................47
1.5.22 Error correction status module (ECSM) ...........................................................................47
1.5.23 Peripheral bridge (PBRIDGE) ..........................................................................................48
1.5.24 Calibration bus interface ...................................................................................................48
1.5.25 Power management controller (PMC) ..............................................................................48
1.5.26 Nexus port controller (NPC) .............................................................................................48
1.5.27 JTAG controller (JTAGC) .................................................................................................49
1.5.28 Development trigger semaphore (DTS) ............................................................................49
Chapter 2
Memory map
2.1 Introduction .....................................................................................................................................51
2.2 Memory Map ...................................................................................................................................51
Chapter 3
Signal Description
3.1 Signal Properties .............................................................................................................................56
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Chapter 4
Resets
4.1 Reset sources ...................................................................................................................................81
4.2 Reset vector .....................................................................................................................................82
4.3 Reset pins ........................................................................................................................................82
4.3.1 RESET ..............................................................................................................................82
4.3.2 RSTOUT ...........................................................................................................................82
4.4 FMPLL lock gating signal ...............................................................................................................83
4.5 Reset source descriptions ................................................................................................................83
4.5.1 Power-on reset (POR) .......................................................................................................86
4.5.2 External reset ....................................................................................................................86
4.5.3 Loss of lock .......................................................................................................................86
4.5.4 Loss of clock .....................................................................................................................87
4.5.5 Core watchdog timer/debug reset .....................................................................................87
4.5.6 JTAG reset ........................................................................................................................88
4.5.7 Software system reset .......................................................................................................88
4.5.8 Software external reset ......................................................................................................88
4.6 Reset registers in the SIU ................................................................................................................88
4.7 Reset configuration .........................................................................................................................89
4.7.1 Reset configuration half word (RCHW) ...........................................................................89
4.7.2 Reset configuration timing ................................................................................................91
4.7.3 Reset weak pull up/down configuration ...........................................................................91
Chapter 5
Operating Modes and Clocking
5.1 Overview .........................................................................................................................................93
5.2 Modes of operation ..........................................................................................................................93
5.2.1 Normal mode ....................................................................................................................93
5.2.2 Debug mode ......................................................................................................................93
5.2.3 Low power modes .............................................................................................................93
5.3 Clock architecture ...........................................................................................................................94
5.3.1 Overview ...........................................................................................................................94
5.3.2 Block diagram ...................................................................................................................95
5.3.3 System clock sources ........................................................................................................95
5.3.4 FMPLL modes of operation ..............................................................................................97
Chapter 6
Device Performance Optimization
6.1 Introduction ...................................................................................................................................105
6.2 Features .........................................................................................................................................105
6.3 Configuring hardware features ......................................................................................................106
6.3.1 Branch target buffer (BTB) .............................................................................................106
6.3.2 Frequency-modulated PLL .............................................................................................107
6.3.3 Flash bus interface unit ...................................................................................................108
6.3.4 Crossbar switch ...............................................................................................................108
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6.3.5 Cache ..............................................................................................................................109
6.3.6 Memory management unit (MMU) ................................................................................111
6.4 Application software .....................................................................................................................112
6.4.1 Compiler optimizations ...................................................................................................112
6.4.2 Signal processing extension ............................................................................................113
6.4.3 Hardware single precision floating point ........................................................................114
6.4.4 Variable length encoding ................................................................................................114
6.5 Peripherals and general application guidelines .............................................................................115
6.6 Performance optimization checklist ..............................................................................................116
Chapter 7
e200z4 Core
7.1 Overview .......................................................................................................................................119
7.2 Features .........................................................................................................................................119
7.3 Microarchitecture summary ..........................................................................................................120
7.3.1 Instruction unit features ..................................................................................................122
7.3.2 Integer unit features ........................................................................................................123
7.3.3 Load/Store unit features ..................................................................................................123
7.3.4 Cache features .................................................................................................................123
7.3.5 MMU features .................................................................................................................123
7.3.6 e200z4 system bus features .............................................................................................124
7.3.7 Nexus 3 features ..............................................................................................................124
Chapter 8
Enhanced Direct Memory Access Controller (eDMA)
8.1 Introduction ...................................................................................................................................125
8.1.1 Block diagram .................................................................................................................125
8.1.2 Features ...........................................................................................................................125
8.1.3 Modes of operation .........................................................................................................126
8.2 External signal description ............................................................................................................127
8.3 Memory map and registers ............................................................................................................127
8.3.1 Module memory map ......................................................................................................127
8.3.2 Register descriptions .......................................................................................................134
8.4 Functional description ...................................................................................................................159
8.4.1 eDMA basic data flow ....................................................................................................161
8.5 Initialization / Application information .........................................................................................164
8.5.1 eDMA initialization ........................................................................................................164
8.5.2 DMA programming errors ..............................................................................................166
8.5.3 DMA request assignments ..............................................................................................167
8.5.4 DMA arbitration mode considerations ...........................................................................170
8.5.5 DMA transfer ..................................................................................................................171
8.5.6 TCD status ......................................................................................................................174
8.5.7 Channel linking ...............................................................................................................176
8.5.8 Dynamic programming ...................................................................................................177
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Chapter 9
Multi-Layer AHB Crossbar Switch (XBAR)
9.1 Introduction ...................................................................................................................................181
9.1.1 Overview .........................................................................................................................181
9.1.2 Features ...........................................................................................................................182
9.1.3 Limitations ......................................................................................................................182
9.1.4 General operation ............................................................................................................182
9.2 XBAR registers .............................................................................................................................183
9.2.1 Register summary ...........................................................................................................183
9.2.2 XBAR register descriptions ............................................................................................184
9.2.3 Coherency .......................................................................................................................189
9.3 Function .........................................................................................................................................190
9.3.1 Arbitration .......................................................................................................................190
9.3.2 Priority assignment .........................................................................................................191
Chapter 10
Peripheral Bridge (PBRIDGE)
10.1 PBRIDGE features ........................................................................................................................193
10.2 PBRIDGE modes of operation ......................................................................................................193
10.3 PBRIDGE block diagram ..............................................................................................................193
10.4 PBRIDGE signal description ........................................................................................................194
10.5 PBRIDGE functional description ..................................................................................................194
10.5.1 Read cycles .....................................................................................................................194
10.5.2 Write cycles .....................................................................................................................194
10.6 Memory map and register description ...........................................................................................194
10.6.1 Memory map ...................................................................................................................194
10.6.2 Register descriptions .......................................................................................................195
Chapter 11
Flash memory
11.1 Introduction ...................................................................................................................................199
11.1.1 Block diagram .................................................................................................................200
11.1.2 Features ...........................................................................................................................201
11.1.3 Modes of operation .........................................................................................................202
11.2 External signal description ............................................................................................................202
11.3 Memory map and registers ............................................................................................................202
11.3.1 Module memory map ......................................................................................................202
11.3.2 Register descriptions .......................................................................................................205
11.4 Functional description ...................................................................................................................226
11.4.1 Flash User Mode .............................................................................................................226
11.4.2 Flash Read and Write ......................................................................................................226
11.4.3 Read While Write (RWW) ..............................................................................................226
11.4.4 UTest Mode .....................................................................................................................227
11.4.5 Flash Programming .........................................................................................................230
11.4.6 Flash Erase ......................................................................................................................233
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11.4.7 Flash shadow block .........................................................................................................236
11.4.8 Flash reset .......................................................................................................................237
11.4.9 DMA requests .................................................................................................................237
11.4.10Interrupt requests ............................................................................................................237
Chapter 12
General-Purpose Static RAM (SRAM)
12.1 Introduction ...................................................................................................................................239
12.2 Features .........................................................................................................................................239
12.3 Modes of operation ........................................................................................................................239
12.3.1 Normal (Functional) mode ..............................................................................................239
12.3.2 Standby mode ..................................................................................................................239
12.4 Block diagram ...............................................................................................................................239
12.5 External signal description ............................................................................................................240
12.6 Register memory map ...................................................................................................................240
12.7 Functional description ...................................................................................................................240
12.8 SRAm ecc mechanism ..................................................................................................................240
12.8.1 Access timing ..................................................................................................................241
12.8.2 Reset effects on SRAM accesses ....................................................................................241
12.9 Initialization and application information .....................................................................................242
12.9.1 Example code ..................................................................................................................242
Chapter 13
Memory Protection Unit (MPU)
13.1 Introduction ...................................................................................................................................243
13.1.1 Features ...........................................................................................................................243
13.1.2 Modes of operation .........................................................................................................244
13.2 MPU-to-XBAR slave port mapping ..............................................................................................244
13.3 Signal description ..........................................................................................................................244
13.4 Memory map and registers ............................................................................................................244
13.4.1 Module memory map ......................................................................................................244
13.4.2 Register descriptions .......................................................................................................246
13.5 Functional Description ..................................................................................................................256
13.5.1 Access Evaluation ...........................................................................................................256
13.5.2 XBAR Error Terminations ..............................................................................................257
13.6 Initialization Information ..............................................................................................................257
13.7 Application Information ................................................................................................................258
Chapter 14
Interrupt Controller (INTC)
14.1 Information specific to this device ................................................................................................261
14.1.1 Device-specific features ..................................................................................................261
14.2 Introduction ...................................................................................................................................261
14.2.1 Block diagram .................................................................................................................261
14.2.2 Overview .........................................................................................................................262
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14.2.3 Features ...........................................................................................................................265
14.2.4 Modes of operation .........................................................................................................265
14.3 External signal description ............................................................................................................267
14.4 Memory map and register definition .............................................................................................267
14.4.1 Register descriptions .......................................................................................................268
14.5 Functional description ...................................................................................................................274
14.5.1 Interrupt request sources .................................................................................................274
14.5.2 Priority management .......................................................................................................288
14.5.3 Details on handshaking with processor ..........................................................................290
14.6 Initialization and application information .....................................................................................292
14.6.1 Initialization flow ............................................................................................................292
14.6.2 Interrupt exception handler .............................................................................................292
14.6.3 ISR, RTOS, and task hierarchy .......................................................................................294
14.6.4 Order of execution ..........................................................................................................295
14.6.5 Priority ceiling protocol ..................................................................................................296
14.6.6 Selecting priorities according to request rates and
deadlines 297
14.6.7 Software configurable interrupt requests ........................................................................297
14.6.8 Lowering priority within an ISR .....................................................................................298
14.6.9 Negating an interrupt request outside of its ISR .............................................................298
14.6.10Examining LIFO contents ...............................................................................................299
Chapter 15
System Integration Unit (SIU)
15.1 Overview .......................................................................................................................................301
15.2 Features .........................................................................................................................................301
15.3 Modes of operation ........................................................................................................................302
15.3.1 Normal mode ..................................................................................................................302
15.3.2 Debug mode ....................................................................................................................302
15.4 Block diagram ...............................................................................................................................302
15.5 Signal description ..........................................................................................................................303
15.6 Memory map and register descriptions .........................................................................................304
15.6.1 Memory map ...................................................................................................................304
15.6.2 MCU ID Register 2 (SIU_MIDR2) ................................................................................306
15.6.3 MCU ID Register (SIU_MIDR) .....................................................................................308
15.6.4 Reset Status Register (SIU_RSR) ...................................................................................309
15.6.5 System Reset Control Register (SIU_SRCR) .................................................................311
15.6.6 External Interrupt Status Register (SIU_EISR) ..............................................................312
15.6.7 DMA/Interrupt Request Enable Register (SIU_DIRER) ................................................313
15.6.8 DMA/Interrupt Request Select Register (SIU_DIRSR) .................................................314
15.6.9 Overrun Status Register (SIU_OSR) ..............................................................................315
15.6.10Overrun Request Enable Register (SIU_ORER) ............................................................316
15.6.11IRQ Rising-Edge Event Enable Register (SIU_IREER) ................................................316
15.6.12External IRQ Falling-Edge Event Enable Register (SIU_IFEER) .................................317
15.6.13External IRQ Digital Filter Register (SIU_IDFR) ..........................................................318
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15.6.14IRQ Filtered Input Register (SIU_IFIR) .........................................................................318
15.6.15Pad Configuration Registers (SIU_PCR) .......................................................................319
15.6.16GPIO Pin Data Output Registers (SIU_GPDO0_3 – SIU_GPDO412_413) ..................411
15.6.17GPIO Pin Data Input Registers (SIU_GPDI0_3 – SIU_GPDI_232) ..............................412
15.6.18eQADC Trigger Input Select Register (SIU_ETISR) .....................................................413
15.6.19External IRQ Input Select Register (SIU_EIISR) ..........................................................416
15.6.20DSPI Input Select Register (SIU_DISR) ........................................................................418
15.6.21IMUX Select Register 3 (SIU_ISEL3) ...........................................................................420
15.6.22IMUX Select Register 8 (SIU_ISEL8) ...........................................................................426
15.6.23IMUX Select Register 9 (SIU_ISEL9) ...........................................................................428
15.6.24IMUX Select Register 10 (SIU_ISEL10) .......................................................................429
15.6.25Chip Configuration Register (SIU_CCR) .......................................................................431
15.6.26External Clock Control Register (SIU_ECCR) ..............................................................432
15.6.27Compare A High Register (SIU_CARH) .......................................................................433
15.6.28Compare A Low Register (SIU_CARL) ........................................................................433
15.6.29Compare B High Register (SIU_CBRH) ........................................................................434
15.6.30Compare B Low Register (SIU_CBRL) .........................................................................434
15.6.31System Clock Register (SIU_SYSDIV) .........................................................................435
15.6.32Halt Register (SIU_HLT) ................................................................................................436
15.6.33Halt Acknowledge Register (SIU_HLTACK) ................................................................438
15.6.34Core MMU PID Control Register (SIU_EMPCR0) .......................................................441
15.7 Functional description ...................................................................................................................442
15.7.1 System configuration ......................................................................................................443
15.7.2 Reset control ...................................................................................................................443
15.7.3 External interrupt request input (IRQ) ............................................................................443
15.7.4 GPIO operation ...............................................................................................................445
15.7.5 Internal multiplexing .......................................................................................................446
Chapter 16
Frequency-modulated phase locked loop (FMPLL)
16.1 Information specific to this device ................................................................................................449
16.1.1 Device-specific features ..................................................................................................449
16.1.2 Device-specific parameters .............................................................................................449
16.2 Introduction ...................................................................................................................................449
16.2.1 Overview .........................................................................................................................450
16.2.2 Features ...........................................................................................................................450
16.2.3 Modes of operation .........................................................................................................451
16.3 External signal description ............................................................................................................452
16.3.1 Detailed signal descriptions ............................................................................................453
16.4 Memory map and register definition .............................................................................................453
16.4.1 Memory map ...................................................................................................................453
16.4.2 Register descriptions .......................................................................................................454
16.5 Functional description ...................................................................................................................464
16.5.1 Input clock frequency .....................................................................................................464
16.5.2 Clock configuration ........................................................................................................464
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16.5.3 Lock detection .................................................................................................................466
16.5.4 Loss-of-clock detection ...................................................................................................466
16.5.5 Frequency modulation ....................................................................................................469
Chapter 17
Error Correction Status Module (ECSM)
17.1 Overview .......................................................................................................................................473
17.2 Features .........................................................................................................................................473
17.3 Module memory map ....................................................................................................................473
17.4 Register descriptions .....................................................................................................................474
17.4.1 Miscellaneous Reset Status Register (ECSM_MRSR) ...................................................474
17.4.2 Miscellaneous Wakeup Control Register (ECSM_MWCR) ...........................................475
17.4.3 Miscellaneous User-Defined Control Register (ECSM_MUDCR) ................................476
17.4.4 ECC registers ..................................................................................................................477
Chapter 18
System Timer Module (STM)
18.1 Information Specific to This Device .............................................................................................497
18.1.1 Device-Specific Features ................................................................................................497
18.2 Introduction ...................................................................................................................................497
18.2.1 Overview .........................................................................................................................497
18.2.2 Modes of operation .........................................................................................................497
18.3 External signal description ............................................................................................................497
18.4 Memory map and register definition .............................................................................................497
18.4.1 Memory map ...................................................................................................................497
18.4.2 Register descriptions .......................................................................................................498
18.5 Functional Description ..................................................................................................................501
Chapter 19
Software Watchdog Timer (SWT)
19.1 Introduction ...................................................................................................................................503
19.1.1 Overview .........................................................................................................................503
19.1.2 Features ...........................................................................................................................503
19.1.3 Modes of operation .........................................................................................................503
19.2 External signal description ............................................................................................................503
19.3 Memory map and register definition .............................................................................................503
19.3.1 Memory map ...................................................................................................................504
19.3.2 Register descriptions .......................................................................................................504
19.4 Functional description ...................................................................................................................509
Chapter 20
Boot Assist Module (BAM)
20.1 Overview .......................................................................................................................................511
20.2 Features .........................................................................................................................................511
20.3 Modes of operation ........................................................................................................................511
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20.3.1 Normal mode ..................................................................................................................511
20.3.2 Debug mode ....................................................................................................................511
20.3.3 Internal boot mode ..........................................................................................................512
20.3.4 Serial boot mode .............................................................................................................512
20.3.5 Calibration bus boot mode ..............................................................................................512
20.4 Memory map .................................................................................................................................512
20.5 Functional description ...................................................................................................................512
20.5.1 BAM Program flow chart ...............................................................................................512
20.5.2 BAM program operation .................................................................................................513
20.5.3 Reset configuration half word (RCHW) .........................................................................516
20.5.4 Internal boot mode ..........................................................................................................518
20.5.5 Serial boot mode .............................................................................................................520
Chapter 21
Configurable Enhanced Modular IO Subsystem (eMIOS200)
21.1 Device-specific features ................................................................................................................527
21.2 Introduction ...................................................................................................................................527
21.2.1 Features ...........................................................................................................................528
21.2.2 Modes of operation .........................................................................................................529
21.2.3 Channel configurations ...................................................................................................529
21.3 External signals description ..........................................................................................................530
21.4 Memory map/register definition ....................................................................................................530
21.4.1 Memory map ...................................................................................................................530
21.4.2 Global registers ...............................................................................................................536
21.4.3 Channel registers .............................................................................................................541
21.5 Functional description ...................................................................................................................551
21.5.1 Unified channel (UC) ......................................................................................................551
21.5.2 IP bus interface unit (BIU) ..............................................................................................574
21.5.3 STAC client submodule ..................................................................................................574
21.5.4 Global clock prescaler submodule (GCP) ......................................................................576
21.6 Initialization/Application information ...........................................................................................576
21.6.1 Considerations ................................................................................................................576
21.6.2 Application information ..................................................................................................576
Chapter 22
Enhanced Time Processing Unit (eTPU2)
22.1 Information specific to this device ................................................................................................579
22.1.1 Device-specific features ..................................................................................................579
22.2 Introduction ...................................................................................................................................579
22.2.1 Overview .........................................................................................................................580
22.2.2 Features ...........................................................................................................................586
22.2.3 Modes of operation .........................................................................................................590
22.3 External signal description ............................................................................................................592
22.3.1 Overview .........................................................................................................................592
22.3.2 Detailed signal descriptions ............................................................................................592
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22.4 Memory map/register definition ....................................................................................................594
22.4.1 Memory map ...................................................................................................................594
22.4.2 System configuration registers ........................................................................................600
22.4.3 Time base registers ..........................................................................................................614
22.4.4 Engine related registers ...................................................................................................623
22.4.5 Channel registers layout ..................................................................................................625
22.4.6 Global channel registers ..................................................................................................625
22.4.7 Channel configuration and control registers ...................................................................634
22.5 Functional description ...................................................................................................................643
22.5.1 Functions and threads .....................................................................................................643
22.5.2 Host interface ..................................................................................................................656
22.5.3 Scheduler ........................................................................................................................662
22.5.4 Parameter sharing and coherency ...................................................................................669
22.5.5 Enhanced Channels .........................................................................................................673
22.5.6 Time Bases ......................................................................................................................718
22.5.7 EAC – eTPU angle counter ............................................................................................726
22.5.8 Microengine ....................................................................................................................745
22.5.9 Microinstruction set ........................................................................................................762
22.5.10Test and Development Support .......................................................................................794
22.6 Initialization/Application information ...........................................................................................801
22.6.1 Configuration sequence ..................................................................................................801
22.6.2 Reset options ...................................................................................................................802
22.6.3 Multiple parameter coherency methods ..........................................................................802
22.6.4 Programming hints and caveats ......................................................................................803
22.6.5 Estimating worst-case latency ........................................................................................804
22.6.6 Endianness ......................................................................................................................820
22.7 Appendices ....................................................................................................................................820
22.7.1 Microcycle and I/O timing ..............................................................................................820
22.7.2 Initialization code example .............................................................................................824
22.7.3 Predefined channel mode summary ................................................................................827
22.7.4 MISC algorithm ..............................................................................................................831
Chapter 23
Enhanced Queued Analog-to-Digital Converter (EQADC)
23.1 Information Specific to This Device .............................................................................................833
23.1.1 Device-Specific Pin Configuration Features ..................................................................833
23.1.2 Availability of Analog Inputs ..........................................................................................834
23.2 Introduction ...................................................................................................................................834
23.2.1 Module overview ............................................................................................................834
23.2.2 Block diagram .................................................................................................................835
23.2.3 Features ...........................................................................................................................836
23.3 Modes of operation ........................................................................................................................838
23.3.1 Normal mode ..................................................................................................................838
23.3.2 Streaming mode ..............................................................................................................838
23.3.3 Debug mode ....................................................................................................................839
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23.3.4 Stop mode .......................................................................................................................840
23.4 External signal description ............................................................................................................841
23.4.1 Overview .........................................................................................................................841
23.4.2 Detailed signal descriptions ............................................................................................843
23.5 Memory Map/Register Definition .................................................................................................847
23.5.1 EQADC Memory Map ....................................................................................................847
23.5.2 EQADC Register Descriptions .......................................................................................851
23.5.3 On-Chip ADC Registers .................................................................................................889
23.6 Functional Description ..................................................................................................................903
23.6.1 Overview .........................................................................................................................903
23.6.2 Data Flow in EQADC .....................................................................................................904
23.6.3 Command/Result Queues ...............................................................................................921
23.6.4 EQADC Command FIFOs ..............................................................................................921
23.6.5 EQADC Result FIFOs ....................................................................................................950
23.6.6 On-Chip ADC Configuration and Control ......................................................................954
23.6.7 Internal/External Multiplexing .......................................................................................966
23.6.8 EQADC DMA/Interrupt request .....................................................................................973
23.6.9 EQADC Synchronous Serial Interface (SSI) Sub-Block ................................................975
23.6.10EQADC Parallel Side Interface (PSI) Sub-Block ...........................................................980
23.6.11Analog Sub-Block ...........................................................................................................983
23.7 Initialization/Application information ...........................................................................................986
23.7.1 Multiple queues control setup example ..........................................................................986
23.7.2 EQADC/DMAC Interface ..............................................................................................991
23.7.3 Sending immediate command setup example .................................................................992
23.7.4 Modifying queues ...........................................................................................................993
23.7.5 CQueue and RQueues usage ...........................................................................................994
23.7.6 ADC Result Calibration ..................................................................................................996
23.7.7 EQADC versus QADC ...................................................................................................998
Chapter 24
System Information Module and Trim (SIM)
24.1 Overview .....................................................................................................................................1003
24.2 User trim values ..........................................................................................................................1003
Chapter 25
Decimation Filter
25.1 Information specific to this device ..............................................................................................1005
25.1.1 Device-specific parameters ...........................................................................................1005
25.1.2 Device-specific features ................................................................................................1005
25.1.3 Device-specific parameters ...........................................................................................1005
25.2 Introduction .................................................................................................................................1006
25.2.1 Overview .......................................................................................................................1006
25.2.2 Features .........................................................................................................................1007
25.2.3 Modes of operation .......................................................................................................1008
25.3 External signal description ..........................................................................................................1009
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25.3.1 Decimation trigger signal ..............................................................................................1009
25.3.2 Integrator enable signal .................................................................................................1009
25.3.3 Integrator halt signal .....................................................................................................1010
25.3.4 Integrator reset signal ....................................................................................................1010
25.3.5 Integrator output request signal ....................................................................................1010
25.4 Memory map and register definition ...........................................................................................1010
25.4.1 Decimation filter device memory map .........................................................................1010
25.4.2 Decimation filter register descriptions ..........................................................................1012
25.4.3 Decimation Filter Memory Map for Parallel Side Interface .........................................1034
25.4.4 PSI Register Description ...............................................................................................1035
25.5 Functional description .................................................................................................................1037
25.5.1 Overview .......................................................................................................................1037
25.5.2 Parallel Side Interface (PSI) description .......................................................................1038
25.5.3 Input buffer description .................................................................................................1038
25.5.4 Output buffer description ..............................................................................................1039
25.5.5 Bypass configuration description ..................................................................................1041
25.5.6 IIR and FIR filter ..........................................................................................................1041
25.5.7 Filter prefill control description ....................................................................................1045
25.5.8 Timestamp data transmission ........................................................................................1046
25.5.9 Flush command description ..........................................................................................1046
25.5.10Soft-reset command description ...................................................................................1047
25.5.11Interrupts requests description ......................................................................................1048
25.5.12DMA requests description ............................................................................................1049
25.5.13Freeze mode description ...............................................................................................1050
25.5.14Enhanced debug monitor description ...........................................................................1050
25.5.15Integrator .......................................................................................................................1051
25.5.16Cascade mode description ............................................................................................1054
25.6 Initialization information .............................................................................................................1060
25.6.1 Initialization procedure .................................................................................................1060
25.7 Application information ..............................................................................................................1060
25.7.1 eQADC IP as the PSI master block ..............................................................................1060
25.8 Filter example simulation ............................................................................................................1061
25.8.1 Coefficients calculation ................................................................................................1061
25.8.2 Input data calculation ....................................................................................................1062
25.8.3 Filter results ..................................................................................................................1062
Chapter 26
Cyclic Redundancy Checker (CRC) Unit
26.1 Overview .....................................................................................................................................1065
26.2 Features .......................................................................................................................................1065
26.2.1 Access and performance ...............................................................................................1065
26.3 Calculating a CRC checksum ......................................................................................................1066
26.3.1 Configuring the context ................................................................................................1067
26.3.2 Initializing the context seed value ................................................................................1068
26.3.3 Writing the data stream to the context input .................................................................1068
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26.3.4 Reading the checksum ..................................................................................................1069
26.4 Register descriptions ...................................................................................................................1069
26.4.1 CRC Configuration Register (CRC_CFG) ...................................................................1070
26.4.2 CRC Input Register (CRC_INP) ...................................................................................1071
26.4.3 CRC Current Status Register (CRC_CSTAT) ...............................................................1072
26.4.4 CRC Output Register (CRC_OUTP) ............................................................................1073
26.5 Use cases and limitations ............................................................................................................1074
26.5.1 Checksums for configuration registers .........................................................................1074
26.5.2 Calculations on incoming/outgoing protocol frames ....................................................1074
Chapter 27
Deserial Serial Peripheral Interface (DSPI)
27.1 Introduction .................................................................................................................................1079
27.2 Overview .....................................................................................................................................1079
27.3 Features .......................................................................................................................................1080
27.4 DSPI configurations ....................................................................................................................1081
27.4.1 SPI configuration ..........................................................................................................1082
27.4.2 DSI configuration .........................................................................................................1082
27.4.3 CSI configuration ..........................................................................................................1083
27.5 DSPI frequency support ..............................................................................................................1083
27.6 Modes of operation ......................................................................................................................1084
27.6.1 Master mode .................................................................................................................1084
27.6.2 Slave mode ....................................................................................................................1084
27.6.3 Module Disable mode ...................................................................................................1084
27.6.4 Debug mode ..................................................................................................................1084
27.7 External signal description ..........................................................................................................1085
27.7.1 Overview .......................................................................................................................1085
27.7.2 Detailed signal description ............................................................................................1085
27.8 Memory map and register definition ...........................................................................................1086
27.8.1 Memory map .................................................................................................................1086
27.8.2 Register descriptions .....................................................................................................1088
27.9 Functional description .................................................................................................................1119
27.9.1 Start and stop of DSPI transfers ....................................................................................1120
27.9.2 Serial peripheral interface (SPI) configuration .............................................................1120
27.9.3 Deserial serial interface (DSI) configuration ................................................................1123
27.9.4 Combined serial interface (CSI) configuration .............................................................1130
27.9.5 DSPI baud rate and clock delay generation ..................................................................1131
27.9.6 Transfer formats ............................................................................................................1133
27.9.7 Continuous serial communications clock .....................................................................1142
27.9.8 Timed serial bus (TSB) .................................................................................................1144
27.9.9 Parity generation and check ..........................................................................................1146
27.9.10Interrupts/DMA requests ..............................................................................................1147
27.9.11Buffered SPI operation .................................................................................................1149
27.9.12Continuous peripheral chip select .................................................................................1150
27.9.13Peripheral chip select expansion and deglitching .........................................................1150
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27.9.14DMA and interrupt conditions ......................................................................................1150
27.9.15Modified SPI transfer format ........................................................................................1151
27.9.16LVDS pad usage ............................................................................................................1151
27.9.17DSPI connections to eTPU_A, eMIOS and SIU ..........................................................1152
27.9.18Power saving features ...................................................................................................1159
27.10Initialization/Application information .........................................................................................1160
27.10.1How to manage DSPI queues .......................................................................................1160
27.10.2Switching master and slave mode .................................................................................1161
27.10.3Baud rate settings ..........................................................................................................1161
27.10.4Delay settings ................................................................................................................1161
27.10.5DSPI Compatibility with the QSPI of the MPC500 MCUs ..........................................1162
27.10.6Calculation of FIFO pointer addresses .........................................................................1163
Chapter 28
Enhanced Serial Communication Interface (eSCI)
28.1 Introduction .................................................................................................................................1165
28.1.1 Bibliography .................................................................................................................1165
28.1.2 Acronyms and abbreviations ........................................................................................1165
28.1.3 Glossary ........................................................................................................................1165
28.1.4 Overview .......................................................................................................................1166
28.1.5 Features .........................................................................................................................1167
28.1.6 Modes of operation .......................................................................................................1168
28.2 External signal description ..........................................................................................................1168
28.2.1 Detailed signal descriptions ..........................................................................................1168
28.3 Memory map and register definition ...........................................................................................1169
28.3.1 Memory map .................................................................................................................1169
28.3.2 Register descriptions .....................................................................................................1169
28.4 Functional description .................................................................................................................1182
28.4.1 Module control ..............................................................................................................1182
28.4.2 Frame formats ...............................................................................................................1182
28.4.3 Baud rate and clock generation .....................................................................................1185
28.4.4 Baud rate tolerance .......................................................................................................1187
28.4.5 SCI mode ......................................................................................................................1189
28.4.6 LIN mode ......................................................................................................................1203
28.4.7 Interrupts .......................................................................................................................1212
28.5 Application information ..............................................................................................................1213
28.5.1 SCI data frames separated by preamble ........................................................................1213
Chapter 29
FlexCAN Module
29.1 Information specific to this device ..............................................................................................1215
29.1.1 Device-specific features ................................................................................................1215
29.2 Introduction .................................................................................................................................1215
29.2.1 Overview .......................................................................................................................1217
29.2.2 FlexCAN module features ............................................................................................1217
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29.2.3 Modes of operation .......................................................................................................1218
29.3 External signal description ..........................................................................................................1219
29.3.1 Overview .......................................................................................................................1219
29.3.2 Signal descriptions ........................................................................................................1220
29.4 Memory map/Register definition ................................................................................................1220
29.4.1 FlexCAN memory mapping ..........................................................................................1220
29.4.2 Message buffer architecture ..........................................................................................1222
29.4.3 Message buffer structure ...............................................................................................1224
29.4.4 Rx FIFO structure .........................................................................................................1226
29.4.5 Register descriptions .....................................................................................................1229
29.5 Functional description .................................................................................................................1247
29.5.1 Overview .......................................................................................................................1247
29.5.2 Transmit process ...........................................................................................................1248
29.5.3 Arbitration process ........................................................................................................1248
29.5.4 Receive process .............................................................................................................1249
29.5.5 Matching process ..........................................................................................................1251
29.5.6 Data coherence ..............................................................................................................1252
29.5.7 Rx FIFO ........................................................................................................................1255
29.5.8 CAN protocol related features ......................................................................................1256
29.5.9 Modes of operation details ............................................................................................1261
29.5.10Interrupts .......................................................................................................................1262
29.5.11Bus interface .................................................................................................................1263
29.6 Initialization/Application information .........................................................................................1264
29.6.1 FlexCAN initialization sequence ..................................................................................1264
29.6.2 FlexCAN addressing and RAM size configurations .....................................................1265
Chapter 30
Periodic Interrupt Timer (PIT)
30.1 Information specific to this device ..............................................................................................1267
30.1.1 Device-specific features ................................................................................................1267
30.2 Introduction .................................................................................................................................1267
30.2.1 Overview .......................................................................................................................1268
30.2.2 Features .........................................................................................................................1268
30.3 Signal description ........................................................................................................................1269
30.4 Memory map and register description .........................................................................................1269
30.4.1 Memory map .................................................................................................................1269
30.4.2 Register descriptions .....................................................................................................1269
30.5 Functional description .................................................................................................................1273
30.5.1 General ..........................................................................................................................1273
30.5.2 Interrupts .......................................................................................................................1274
30.6 Initialization and application information ...................................................................................1275
30.6.1 Example configuration ..................................................................................................1275
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Chapter 31
FlexRay Communication Controller (FlexRay)
31.1 Introduction .................................................................................................................................1277
31.1.1 Reference ......................................................................................................................1277
31.1.2 Glossary ........................................................................................................................1277
31.1.3 Color coding .................................................................................................................1278
31.1.4 Overview .......................................................................................................................1278
31.1.5 Features .........................................................................................................................1280
31.1.6 Modes of operation .......................................................................................................1281
31.2 External signal description ..........................................................................................................1282
31.2.1 Detailed signal descriptions ..........................................................................................1282
31.3 Controller host interface clocking ...............................................................................................1283
31.4 Protocol engine clocking .............................................................................................................1283
31.4.1 Oscillator clocking ........................................................................................................1284
31.4.2 PLL clocking .................................................................................................................1284
31.5 Memory map and register description .........................................................................................1284
31.5.1 Memory map .................................................................................................................1284
31.5.2 Register descriptions .....................................................................................................1288
31.6 Functional description .................................................................................................................1361
31.6.1 Message buffer concept ................................................................................................1361
31.6.2 Physical message buffer ................................................................................................1361
31.6.3 Message buffer types ....................................................................................................1363
31.6.4 FlexRay memory area layout ........................................................................................1368
31.6.5 Physical message buffer description .............................................................................1371
31.6.6 Individual message buffer functional description .........................................................1380
31.6.7 Individual message buffer search ..................................................................................1406
31.6.8 Individual message buffer reconfiguration ...................................................................1409
31.6.9 Receive FIFOs ..............................................................................................................1410
31.6.10Channel device modes ..................................................................................................1416
31.6.11External clock synchronization .....................................................................................1418
31.6.12Sync frame ID and sync frame deviation tables ...........................................................1419
31.6.13MTS generation ............................................................................................................1422
31.6.14Key slot transmission ....................................................................................................1423
31.6.15Sync frame filtering ......................................................................................................1424
31.6.16Strobe signal support .....................................................................................................1425
31.6.17Timer support ................................................................................................................1426
31.6.18Slot status monitoring ...................................................................................................1427
31.6.19System bus access .........................................................................................................1430
31.6.20Interrupt support ...........................................................................................................1431
31.6.21Lower bit rate support ...................................................................................................1436
31.6.22PE data memory (PE DRAM) ......................................................................................1436
31.6.23CHI lookup-table memory (CHI LRAM) .....................................................................1437
31.6.24Memory content error detection ...................................................................................1438
31.6.25Memory error injection .................................................................................................1443
31.7 Application information ..............................................................................................................1445
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31.7.1 Module configuration ...................................................................................................1445
31.7.2 Initialization Sequence ..................................................................................................1446
31.7.3 CHI LRAM error injection out of POC:default config ................................................1447
31.7.4 PE DRAM error injection out of POC:default config ..................................................1447
31.7.5 Shut down sequence ......................................................................................................1447
31.7.6 Number of usable message buffers ...............................................................................1448
31.7.7 Protocol control command execution ...........................................................................1449
31.7.8 Message buffer search on simple message buffer configuration ..................................1450
Chapter 32
Power Management Controller (PMC)
32.1 Introduction .................................................................................................................................1453
32.1.1 Block diagram ...............................................................................................................1454
32.2 External signal description ..........................................................................................................1455
32.2.1 Detailed signal descriptions ..........................................................................................1455
32.3 Memory map/register definition ..................................................................................................1456
32.3.1 Module Configuration Register (MCR) ........................................................................1457
32.3.2 Trimming Register (TRIMR) ........................................................................................1459
32.3.3 Status Register (SR) ......................................................................................................1462
32.4 Functional description .................................................................................................................1465
32.4.1 Bandgap ........................................................................................................................1465
32.4.2 5 V LVI .........................................................................................................................1466
32.4.3 3.3 V internal voltage regulator ....................................................................................1466
32.4.4 3.3 V LVI ......................................................................................................................1468
32.4.5 1.2 V voltage regulator controller .................................................................................1469
32.4.6 1.2 V LVI ......................................................................................................................1469
32.4.7 Resets and interrupts .....................................................................................................1469
32.4.8 Soft-Start (for 1.2 V and 3.3 V regulators) ...................................................................1473
32.4.9 ADC test mux ...............................................................................................................1473
32.5 Electrical characteristics ..............................................................................................................1474
Chapter 33
JTAG Controller (JTAGC)
33.1 Information specific to this device ..............................................................................................1475
33.1.1 Device-specific parameters ...........................................................................................1475
33.1.2 Device identification register parameters .....................................................................1475
33.1.3 Auxiliary TAP controller instructions ...........................................................................1475
33.2 Introduction .................................................................................................................................1476
33.2.1 Overview .......................................................................................................................1476
33.2.2 Features .........................................................................................................................1476
33.2.3 Modes of operation .......................................................................................................1477
33.3 External signal description ..........................................................................................................1478
33.3.1 Overview .......................................................................................................................1478
33.3.2 Detailed signal descriptions ..........................................................................................1478
33.4 Register definition .......................................................................................................................1479
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33.4.1 Register descriptions .....................................................................................................1479
33.5 Functional description .................................................................................................................1482
33.5.1 JTAGC reset configuration ...........................................................................................1482
33.5.2 IEEE 1149.1-2001 (JTAG) test access port ..................................................................1482
33.5.3 TAP controller state machine ........................................................................................1482
33.5.4 JTAGC block instructions .............................................................................................1484
33.5.5 Boundary scan ...............................................................................................................1486
33.6 Initialization/application information ..........................................................................................1487
Chapter 34
Nexus Port Controller (NPC)
34.1 Information specific to this device ..............................................................................................1489
34.1.1 Device-specific features ................................................................................................1489
34.1.2 Parameter values ...........................................................................................................1490
34.2 Introduction .................................................................................................................................1491
34.2.1 Overview .......................................................................................................................1492
34.2.2 Features .........................................................................................................................1492
34.2.3 Modes of operation .......................................................................................................1493
34.3 External signal description ..........................................................................................................1494
34.3.1 Overview .......................................................................................................................1494
34.3.2 Detailed signal descriptions ..........................................................................................1494
34.4 Register definition .......................................................................................................................1495
34.4.1 Register descriptions .....................................................................................................1496
34.5 Functional description .................................................................................................................1499
34.5.1 NPC reset configuration ................................................................................................1499
34.5.2 Auxiliary output port ....................................................................................................1500
34.5.3 IEEE 1149.1-2001 (JTAG) TAP ...................................................................................1503
34.5.4 Nexus JTAG port sharing ..............................................................................................1507
34.5.5 MCKO and ipg_sync_mcko .........................................................................................1507
34.5.6 EVTO sharing ...............................................................................................................1507
34.5.7 Nexus reset control .......................................................................................................1507
34.5.8 System clock locked indication ....................................................................................1507
34.6 Initialization/Application information .........................................................................................1508
34.6.1 Accessing NPC tool-mapped registers .........................................................................1508
Chapter 35
Development Trigger Semaphore (DTS)
35.1 Introduction .................................................................................................................................1509
35.2 Overview .....................................................................................................................................1509
35.3 DTS device connections ..............................................................................................................1510
35.3.1 DTS register access .......................................................................................................1511
35.4 Memory map ...............................................................................................................................1512
35.5 Register descriptions ...................................................................................................................1512
35.5.1 DTS Output Enable Register (DTS_ENABLE) ...........................................................1512
35.5.2 DTS Startup Register (DTS_STARTUP) ......................................................................1513
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