Xilinx Virtex-6 FPGA User manual

Virtex-6LibrariesGuidefor

HDLDesigns

UG623(v14.5)March20,2013

NoticeofDisclaimer

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(whetherincontractortort,includingnegligence,orunderanyothertheoryofliability)foranylossordamage

ofanykindornaturerelatedto,arisingunder,orinconnectionwith,theMaterials(includingyouruseofthe

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Warrantieswhichcanbeviewedath

ttp://www.xilinx.com/warranty.htm;IPcoresmaybesubjecttowarranty

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Chapter1

Introduction

ThisHDLguideispartoftheISE®documentationcollection.Aseparateversionofthis

guideisavailableifyouprefertoworkwithschematics.

Thisguidecontainsthefollowing:

•Introduction.

•Descriptionsofeachavailablemacro.

•Alistofdesignelementssupportedinthisarchitecture,organizedbyfunctional

categories.

•Descriptionsofeachavailableprimitive.

AboutDesignElements

ThisversionoftheLibrariesGuidedescribesthevaliddesignelementsforVirtex®-6

devices,andincludesexamplesofinstantiationcodeforeachelement.Instantiation

templatesarealsosuppliedinaseparateZIPle,whichyoucanndinyourinstallation

directoryunderISE/doc/usenglish/isehelp.

Designelementsaredividedintothreemaincategories:

•Macros-TheseelementsareintheUniMacrolibraryintheXilinxtool,andareused

toinstantiateprimitivesthatarecomplextoinstantiatebyjustusingtheprimitives.

Thesynthesistoolswillautomaticallyexpandtheunimacrostotheirunderlying

primitives.

•Primitives-XilinxcomponentsthatarenativetotheFPGAyouaretargeting.Ifyou

instantiateaprimitiveinyourdesign,afterthetranslationprocess(ngdbuild)you

willendupwiththeexactsamecomponentinthebackend.Forexample,ifyou

instantiatetheVirtex®-5elementknownasISERDES_NODELAYasauserprimitive,

afteryouruntranslate(ngdbuild)youwillendupwithanISERDES_NODELAY

inthebackendaswell.IfyouwereusingISERDESinaVirtex-5device,thenthis

willautomaticallyretargettoanISERDES_NODELAYforVirtex-5inthebackend.

Hence,thisconceptofa“primitive”differsfromotherusesofthatterminthis

technology.

COREGeneratormaintainssoftwarelibrarieswithhundredsoffunctionaldesign

elements(UniMacrosandprimitives)fordifferentdevicearchitectures.Newfunctional

elementsareassembledwitheachreleaseofdevelopmentsystemsoftware.Inaddition

toacomprehensiveUniedLibrarycontainingalldesignelements,thisguideisonein

aseriesofarchitecture-speciclibraries.

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Chapter1:Introduction

DesignEntryMethods

Foreachdesignelementinthisguide,Xilinxevaluatesfouroptionsforusingthedesign

element,andrecommendswhatwebelieveisthebestsolutionforyou.Thefouroptions

are:

•Instantiation-Thiscomponentcanbeinstantiateddirectlyintothedesign.This

methodisusefulifyouwanttocontroltheexactplacementoftheindividualblocks.

•Inference-Thiscomponentcanbeinferredbymostsupportedsynthesistools.You

shouldusethismethodifyouwanttohavecompleteexibilityandportabilityofthe

codetomultiplearchitectures.Inferencealsogivesthetoolstheabilitytooptimize

forperformance,area,orpower,asspeciedbytheusertothesynthesistool.

•Coregen&Wizards-ThiscomponentcanbeusedthroughCOREGeneratoror

otherWizards.Youshouldusethismethodifyouwanttobuildlargeblocksofany

FPGAprimitivethatcannotbeinferred.Whenusingthisow,youwillhaveto

re-generateyourcoresforeacharchitecturethatyouaretargeting.

•MacroSupport-ThiscomponenthasaUniMacrothatcanbeused.These

componentsareintheUniMacrolibraryintheXilinxtool,andareusedtoinstantiate

primitivesthataretoocomplextoinstantiatebyjustusingtheprimitives.The

synthesistoolswillautomaticallyexpandUniMacrostotheirunderlyingprimitives.

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Chapter2

AboutUnimacros

ThissectiondescribestheunimacrosthatcanbeusedwithVirtex®-6devices.The

unimacrosareorganizedalphabetically.

Thefollowinginformationisprovidedforeachunimacro,whereapplicable:

•Nameofelement

•Briefdescription

•Schematicsymbol

•Logictable(ifany)

•Portdescriptions

•DesignEntryMethod

•Availableattributes

•Exampleinstantiationcode

•Formoreinformation

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Chapter2:AboutUnimacros

BRAM_SDP_MACRO

Macro:SimpleDualPortRAM

Introduction

FPGAdevicescontainseveralblockRAMmemoriesthatcanbeconguredasgeneral-purpose36Kbor18Kb

RAM/ROMmemories.TheseblockRAMmemoriesofferfastandexiblestorageoflargeamountsofon-chip

data.Bothreadandwriteoperationsarefullysynchronoustothesuppliedclock(s)ofthecomponent.However,

readandwriteportscanoperatefullyindependentlyandasynchronouslytoeachother,accessingthesame

memoryarray .Byte-enablewriteoperationsarepossible,andanoptionaloutputregistercanbeusedtoreduce

theclock-to-outtimesoftheRAM.

NoteThiselement,mustbeconguredsothatreadandwriteportshavethesamewidth.

PortDescription

NameDirectionWidth(Bits)Function

OutputPorts

DOOutput

SeeCongurationTableDataoutputbusaddressedbyRDADDR.

InputPorts

DIInput

SeeCongurationTableDatainputbusaddressedbyWRADDR.

WRADDR,

RDADDR

Input

SeeCongurationTable

Write/Readaddressinputbuses.

WE

Input

SeeCongurationTableByte-WideWriteenable.

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Chapter2:AboutUnimacros

NameDirectionWidth(Bits)Function

WREN,

RDEN

Input1

Write/Readenable

SSR

Input1

Outputregisterssynchronousreset.

REGCE

Input1

Outputregisterclockenableinput(validonly

whenDO_REG=1)

WRCLK,

RDCLK

Input1

Write/Readclockinput.

ConﬁgurationTable

DATA_WIDTHBRAM_SIZEADDRWE

72-37

36Kb

98

36Kb

10 36-19

18Kb

9

4

36Kb

11 18-10

18Kb

10

2

36Kb

12 9-5

18Kb

11

1

36Kb

13 4-3

18Kb

12

1

36Kb

14 2

18Kb

13

1

36Kb

15 1

18Kb

14

1

DesignEntryMethod

Thisunimacrocanbeinstantiatedonly.Itisaparameterizableversionoftheprimitive.ConsulttheConguration

Tableabovetocorrectlycongureittomeetyourdesignneeds.

Instantiation

Yes

Inference

No

COREGenerator™andwizards

No

Macrosupport

Recommended

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Chapter2:AboutUnimacros

AvailableAttributes

AttributeDataTypeAllowedValuesDefaultDescription

BRAM_SIZEString

"36Kb","18Kb""18Kb"ConguresRAMas"36Kb"or"18Kb"

memory.

DO_REG

Integer0,10

Avalueof1enablestotheoutput

registerstotheRAMenablingquicker

clock-to-outfromtheRAMatthe

expenseofanaddedclockcycleof

readlatency .Avalueof0allowsa

readinoneclockcyclebutwillhave

slowerclocktoouttiming.

INIT

HexadecimalAny72-BitValueAllzerosSpeciestheinitialvalueonthe

outputafterconguration.

READ_WIDTH,

WRITE_WIDTH

Integer1-7236

SpeciesthesizeoftheDIandDO

buses.

Thefollowingcombinationsare

allowed:

•READ_WIDTH=

WRITE_WIDTH

•Ifasymmetric,READ_WIDTH

andWRITE_WIDTHmustbein

theratioof2,ormustbevalues

allowedbytheunisim(1,2,4,8,

9,16,18,32,36,64,72)

INIT_FILE

StringStringrepresenting

lenameand

location

None

Nameofthelecontaininginitial

values.

SIM_COLLISION_

CHECK

String"ALL",

"WARNING_

ONLY",

"GENERATE_X_

ONLY",

"NONE"

"ALL"

Allowsmodicationofthesimulation

behaviorifamemorycollisionoccurs.

Theoutputisaffectedasfollows:

•"ALL"-Warningproduced

andaffectedoutputs/memory

locationgounknown(X).

•"WARNING_ONLY"-Warning

producedandaffected

outputs/memoryretainlast

value.

•"GENERATE_X_ONLY"-No

warning.However,affected

outputs/memorygounknown

(X).

•"NONE"-Nowarningand

affectedoutputs/memoryretain

lastvalue.

NoteSettingthistoavalueother

than"ALL"canallowproblemsin

thedesigngounnoticedduring

simulation.Careshouldbetaken

whenchangingthevalueofthis

attribute.PleaseseetheSynthesis

andSimulationDesignGuideformore

information.

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Chapter2:AboutUnimacros

AttributeDataTypeAllowedValuesDefaultDescription

SIM_MODEString"SAFE","FAST"."SAFE"

Thisisasimulationonlyattribute.It

willdirectthesimulationmodelto

runinperformance-orientedmode

whensetto"FAST."Pleaseseethe

SynthesisandSimulationDesignGuide

formoreinformation.

SRVAL

HexadecimalAny72-BitValueAllzeroesSpeciestheoutputvalueofonthe

DOportupontheassertionofthe

synchronousreset(RST)signal.

INIT_00to

INIT_7F

HexadecimalAny256-BitValueAllzeroesAllowsspecicationoftheinitial

contentsofthe16Kbor32Kbdata

memoryarray .

INITP_00to

INITP_0F

HexadecimalAny256-BitValueAllzeroesAllowsspecicationoftheinitial

contentsofthe2Kbor4Kbparity

datamemoryarray.

VHDLInstantiationTemplate

Unlesstheyalreadyexist,copythefollowingtwostatementsandpastethembeforetheentitydeclaration.

LibraryUNISIM;

useUNISIM.vcomponents.all;

--BRAM_SDP_MACRO:SimpleDualPortRAM

--Virtex-6

--XilinxHDLLibrariesGuide,version14.5

--Note-ThisUnimacromodelassumestheportdirectionstobe"downto".

--Simulationofthismodelwith"to"intheportdirectionscouldleadtoerroneousresults.

-----------------------------------------------------------------------

--READ_WIDTH|BRAM_SIZE|READDepth|RDADDRWidth|--

--WRITE_WIDTH||WRITEDepth|WRADDRWidth|WEWidth--

--============|===========|=============|==============|============--

--37-72|"36Kb"|512|9-bit|8-bit--

--19-36|"36Kb"|1024|10-bit|4-bit--

--19-36|"18Kb"|512|9-bit|4-bit--

--10-18|"36Kb"|2048|11-bit|2-bit--

--10-18|"18Kb"|1024|10-bit|2-bit--

--5-9|"36Kb"|4096|12-bit|1-bit--

--5-9|"18Kb"|2048|11-bit|1-bit--

--3-4|"36Kb"|8192|13-bit|1-bit--

--3-4|"18Kb"|4096|12-bit|1-bit--

--2|"36Kb"|16384|14-bit|1-bit--

--2|"18Kb"|8192|13-bit|1-bit--

--1|"36Kb"|32768|15-bit|1-bit--

--1|"18Kb"|16384|14-bit|1-bit--

-----------------------------------------------------------------------

BRAM_SDP_MACRO_inst:BRAM_SDP_MACRO

genericmap(

BRAM_SIZE=>"18Kb",--TargetBRAM,"18Kb"or"36Kb"

DEVICE=>"VIRTEX6",--Targetdevice:"VIRTEX5","VIRTEX6","SPARTAN6"

WRITE_WIDTH=>0,--Validvaluesare1-72(37-72onlyvalidwhenBRAM_SIZE="36Kb")

READ_WIDTH=>0,--Validvaluesare1-72(37-72onlyvalidwhenBRAM_SIZE="36Kb")

DO_REG=>0,--Optionaloutputregister(0or1)

INIT_FILE=>"NONE",

SIM_COLLISION_CHECK=>"ALL",--Collisioncheckenable"ALL","WARNING_ONLY",

--"GENERATE_X_ONLY"or"NONE"

SRVAL=>X"000000000000000000",--Set/Resetvalueforportoutput

INIT=>X"000000000000000000",--Initialvaluesonoutputport

--ThefollowingINIT_xxdeclarationsspecifytheinitialcontentsoftheRAM

INIT_00=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_01=>X"0000000000000000000000000000000000000000000000000000000000000000",

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Chapter2:AboutUnimacros

INIT_02=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_03=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_04=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_05=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_06=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_07=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_08=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_09=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_0A=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_0B=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_0C=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_0D=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_0E=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_0F=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_10=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_11=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_12=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_13=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_14=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_15=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_16=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_17=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_18=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_19=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_1A=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_1B=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_1C=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_1D=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_1E=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_1F=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_20=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_21=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_22=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_23=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_24=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_25=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_26=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_27=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_28=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_29=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_2A=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_2B=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_2C=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_2D=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_2E=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_2F=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_30=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_31=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_32=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_33=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_34=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_35=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_36=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_37=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_38=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_39=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_3A=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_3B=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_3C=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_3D=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_3E=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_3F=>X"0000000000000000000000000000000000000000000000000000000000000000",

--ThenextsetofINIT_xxarevalidwhenconfiguredas36Kb

INIT_40=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_41=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_42=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_43=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_44=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_45=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_46=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_47=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_48=>X"0000000000000000000000000000000000000000000000000000000000000000",

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INIT_49=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_4A=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_4B=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_4C=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_4D=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_4E=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_4F=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_50=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_51=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_52=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_53=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_54=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_55=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_56=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_57=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_58=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_59=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_5A=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_5B=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_5C=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_5D=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_5E=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_5F=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_60=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_61=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_62=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_63=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_64=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_65=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_66=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_67=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_68=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_69=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_6A=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_6B=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_6C=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_6D=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_6E=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_6F=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_70=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_71=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_72=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_73=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_74=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_75=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_76=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_77=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_78=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_79=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_7A=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_7B=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_7C=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_7D=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_7E=>X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_7F=>X"0000000000000000000000000000000000000000000000000000000000000000",

--ThenextsetofINITP_xxarefortheparitybits

INITP_00=>X"0000000000000000000000000000000000000000000000000000000000000000",

INITP_01=>X"0000000000000000000000000000000000000000000000000000000000000000",

INITP_02=>X"0000000000000000000000000000000000000000000000000000000000000000",

INITP_03=>X"0000000000000000000000000000000000000000000000000000000000000000",

INITP_04=>X"0000000000000000000000000000000000000000000000000000000000000000",

INITP_05=>X"0000000000000000000000000000000000000000000000000000000000000000",

INITP_06=>X"0000000000000000000000000000000000000000000000000000000000000000",

INITP_07=>X"0000000000000000000000000000000000000000000000000000000000000000",

--ThenextsetofINIT_xxarevalidwhenconfiguredas36Kb

INITP_08=>X"0000000000000000000000000000000000000000000000000000000000000000",

INITP_09=>X"0000000000000000000000000000000000000000000000000000000000000000",

INITP_0A=>X"0000000000000000000000000000000000000000000000000000000000000000",

INITP_0B=>X"0000000000000000000000000000000000000000000000000000000000000000",

INITP_0C=>X"0000000000000000000000000000000000000000000000000000000000000000",

INITP_0D=>X"0000000000000000000000000000000000000000000000000000000000000000",

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Chapter2:AboutUnimacros

INITP_0E=>X"0000000000000000000000000000000000000000000000000000000000000000",

INITP_0F=>X"0000000000000000000000000000000000000000000000000000000000000000")

portmap(

DO=>DO,--Outputreaddataport,widthdefinedbyREAD_WIDTHparameter

DI=>DI,--Inputwritedataport,widthdefinedbyWRITE_WIDTHparameter

RDADDR=>RDADDR,--Inputreadaddress,widthdefinedbyreadportdepth

RDCLK=>RDCLK,--1-bitinputreadclock

RDEN=>RDEN,--1-bitinputreadportenable

REGCE=>REGCE,--1-bitinputreadoutputregisterenable

RST=>RST,--1-bitinputreset

WE=>WE,--Inputwriteenable,widthdefinedbywriteportdepth

WRADDR=>WRADDR,--Inputwriteaddress,widthdefinedbywriteportdepth

WRCLK=>WRCLK,--1-bitinputwriteclock

WREN=>WREN--1-bitinputwriteportenable

);

--EndofBRAM_SDP_MACRO_instinstantiation

VerilogInstantiationTemplate

//BRAM_SDP_MACRO:SimpleDualPortRAM

//Virtex-6

//XilinxHDLLibrariesGuide,version14.5

///////////////////////////////////////////////////////////////////////

//READ_WIDTH|BRAM_SIZE|READDepth|RDADDRWidth|//

//WRITE_WIDTH||WRITEDepth|WRADDRWidth|WEWidth//

//============|===========|=============|==============|============//

//37-72|"36Kb"|512|9-bit|8-bit//

//19-36|"36Kb"|1024|10-bit|4-bit//

//19-36|"18Kb"|512|9-bit|4-bit//

//10-18|"36Kb"|2048|11-bit|2-bit//

//10-18|"18Kb"|1024|10-bit|2-bit//

//5-9|"36Kb"|4096|12-bit|1-bit//

//5-9|"18Kb"|2048|11-bit|1-bit//

//3-4|"36Kb"|8192|13-bit|1-bit//

//3-4|"18Kb"|4096|12-bit|1-bit//

//2|"36Kb"|16384|14-bit|1-bit//

//2|"18Kb"|8192|13-bit|1-bit//

//1|"36Kb"|32768|15-bit|1-bit//

//1|"18Kb"|16384|14-bit|1-bit//

///////////////////////////////////////////////////////////////////////

BRAM_SDP_MACRO#(

.BRAM_SIZE("18Kb"),//TargetBRAM,"18Kb"or"36Kb"

.DEVICE("VIRTEX6"),//Targetdevice:"VIRTEX5","VIRTEX6","SPARTAN6"

.WRITE_WIDTH(0),//Validvaluesare1-72(37-72onlyvalidwhenBRAM_SIZE="36Kb")

.READ_WIDTH(0),//Validvaluesare1-72(37-72onlyvalidwhenBRAM_SIZE="36Kb")

.DO_REG(0),//Optionaloutputregister(0or1)

.INIT_FILE("NONE"),

.SIM_COLLISION_CHECK("ALL"),//Collisioncheckenable"ALL","WARNING_ONLY",

//"GENERATE_X_ONLY"or"NONE"

.SRVAL(72’h000000000000000000),//Set/Resetvalueforportoutput

.INIT(72’h000000000000000000),//Initialvaluesonoutputport

.WRITE_MODE("WRITE_FIRST"),//Specify"READ_FIRST"forsameclockorsynchronousclocks

//Specify"WRITE_FIRSTforasynchronousclocksonports

.INIT_00(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_01(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_02(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_03(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_04(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_05(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_06(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_07(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_08(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_09(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_0A(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_0B(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_0C(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_0D(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_0E(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_0F(256’h0000000000000000000000000000000000000000000000000000000000000000),

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.INIT_10(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_11(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_12(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_13(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_14(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_15(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_16(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_17(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_18(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_19(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_1A(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_1B(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_1C(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_1D(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_1E(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_1F(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_20(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_21(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_22(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_23(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_24(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_25(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_26(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_27(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_28(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_29(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_2A(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_2B(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_2C(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_2D(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_2E(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_2F(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_30(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_31(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_32(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_33(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_34(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_35(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_36(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_37(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_38(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_39(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_3A(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_3B(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_3C(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_3D(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_3E(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_3F(256’h0000000000000000000000000000000000000000000000000000000000000000),

//ThenextsetofINIT_xxarevalidwhenconfiguredas36Kb

.INIT_40(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_41(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_42(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_43(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_44(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_45(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_46(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_47(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_48(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_49(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_4A(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_4B(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_4C(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_4D(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_4E(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_4F(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_50(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_51(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_52(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_53(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_54(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_55(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_56(256’h0000000000000000000000000000000000000000000000000000000000000000),

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Chapter2:AboutUnimacros

.INIT_57(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_58(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_59(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_5A(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_5B(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_5C(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_5D(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_5E(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_5F(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_60(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_61(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_62(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_63(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_64(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_65(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_66(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_67(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_68(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_69(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_6A(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_6B(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_6C(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_6D(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_6E(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_6F(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_70(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_71(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_72(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_73(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_74(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_75(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_76(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_77(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_78(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_79(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_7A(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_7B(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_7C(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_7D(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_7E(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_7F(256’h0000000000000000000000000000000000000000000000000000000000000000),

//ThenextsetofINITP_xxarefortheparitybits

.INITP_00(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INITP_01(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INITP_02(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INITP_03(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INITP_04(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INITP_05(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INITP_06(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INITP_07(256’h0000000000000000000000000000000000000000000000000000000000000000),

//ThenextsetofINITP_xxarevalidwhenconfiguredas36Kb

.INITP_08(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INITP_09(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INITP_0A(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INITP_0B(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INITP_0C(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INITP_0D(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INITP_0E(256’h0000000000000000000000000000000000000000000000000000000000000000),

.INITP_0F(256’h0000000000000000000000000000000000000000000000000000000000000000)

)BRAM_SDP_MACRO_inst(

.DO(DO),//Outputreaddataport,widthdefinedbyREAD_WIDTHparameter

.DI(DI),//Inputwritedataport,widthdefinedbyWRITE_WIDTHparameter

.RDADDR(RDADDR),//Inputreadaddress,widthdefinedbyreadportdepth

.RDCLK(RDCLK),//1-bitinputreadclock

.RDEN(RDEN),//1-bitinputreadportenable

.REGCE(REGCE),//1-bitinputreadoutputregisterenable

.RST(RST),//1-bitinputreset

.WE(WE),//Inputwriteenable,widthdefinedbywriteportdepth

.WRADDR(WRADDR),//Inputwriteaddress,widthdefinedbywriteportdepth

.WRCLK(WRCLK),//1-bitinputwriteclock

.WREN(WREN)//1-bitinputwriteportenable

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Chapter2:AboutUnimacros

);

//EndofBRAM_SDP_MACRO_instinstantiation

ForMoreInformation

SeetheVirtex-6FPGAUserDocumentation(UserGuidesandDataSheets).

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Chapter2:AboutUnimacros

BRAM_SINGLE_MACRO

Macro:SinglePortRAM

Introduction

FPGAdevicescontainseveralblockRAMmemoriesthatcanbeconguredasgeneral-purpose36Kbor18Kb

RAM/ROMmemories.Thesesingle-port,blockRAMmemoriesofferfastandexiblestorageoflargeamounts

ofon-chipdata.Byte-enablewriteoperationsarepossible,andanoptionaloutputregistercanbeusedto

reducetheclock-to-outtimesoftheRAM.

PortDescription

NameDirectionWidthFunction

OutputPorts

DOOutput

SeeCongurationTable

below.

DataoutputbusaddressedbyADDR.

InputPorts

DIInput

SeeCongurationTable

below.

DatainputbusaddressedbyADDR.

ADDR

Input

SeeCongurationTable

below.

Addressinputbus.

WE

Input

SeeCongurationTable

below.

Byte-WideWriteenable.

ENInput1

Write/Readenables.

RST

Input1

Outputregisterssynchronousreset.

REGCE

Input1

Outputregisterclockenableinput(validonlywhen

DO_REG=1)

CLK

Input1

Clockinput.

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Chapter2:AboutUnimacros

ConﬁgurationTable

WRITE_WIDTHREAD_WIDTHBRAM_SIZEADDRWE

37-729

36-1910

18-1011

9-512

4-313

214

37-72

1

36Kb

15

8

36-1910

18-1011

9-512

4-313

214

36-19

1

36Kb

15

4

36-1911

18-1011

9-512

4-313

214

18-10

1

36Kb

15

2

36-1912

18-1012

9-512

4-313

214

9-5

1

36Kb

15

1

36-1913

18-1013

9-513

4-313

214

4-3

1

36Kb

15

1

36-1914

18-1014

9-514

4-314

214

2

1

36Kb

15

1

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Chapter2:AboutUnimacros

WRITE_WIDTHREAD_WIDTHBRAM_SIZEADDRWE

36-1915

18-1015

9-515

3-415

215

1

36Kb

15

1

18-1010

9-511

4-312

213

18-10

1

18Kb

14

2

18-1011

9-511

4-312

213

9-5

1

18Kb

14

1

18-1012

9-512

4-312

213

4-3

1

18Kb

14

1

18-1013

9-513

4-313

213

2

1

18Kb

14

1

18-1014

9-514

4-314

214

1

18Kb

14

1

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Chapter2:AboutUnimacros

DesignEntryMethod

Thisunimacrocanbeinstantiatedonly.Itisaparameterizableversionoftheprimitive.Consulttheabove

CongurationTableincorrectlyconguringthiselementtomeetyourdesignneeds.

Instantiation

Yes

Inference

No

COREGenerator™andwizards

No

Macrosupport

Recommended

AvailableAttributes

AttributeDataTypeAllowedValuesDefaultDescription

BRAM_SIZEString

"36Kb","18Kb""18Kb"ConguresRAMas36Kbor18Kbmemory.

DO_REG

Integer0,10

Avalueof1enablestotheoutputregisters

totheRAMenablingquickerclock-to-out

fromtheRAMattheexpenseofanadded

clockcycleofreadlatency.Avalueof0

allowsareadinoneclockcyclebutwillhave

slowerclocktoouttiming.

READ_WIDTH,

WRITE_WIDTH

Integer1-361

SpeciesthesizeoftheDIandDObuses.

Thefollowingcombinationsareallowed:

•READ_WIDTH=WRITE_WIDTH

•Ifasymmetric,READ_WIDTHand

WRITE_WIDTHmustbeintheratio

of2,ormustbevaluesallowedbythe

unisim(1,2,4,8,9,16,18,32,36,64,72)

INIT_FILE

StringString

representingle

nameandlocation

NONE

Nameofthelecontaininginitialvalues.

WRITE_MODE

String"READ_FIRST",

"WRITE_FIRST",

"NO_CHANGE"

"WRITE_FIRST"

Specieswritemodetothememory

INIT

HexadecimalAny72-BitValueAllzerosSpeciestheinitialvalueontheoutputafter

conguration.

SRVAL

HexadecimalAny72-BitValueAllzeroesSpeciestheoutputvalueofontheDOport

upontheassertionofthesynchronousreset

(RST)signal.

SIM_MODEString"SAFE","FAST""SAFE"

Thisisasimulationonlyattribute.It

willdirectthesimulationmodeltorun

inperformance-orientedmodewhen

setto"FAST."PleaseseetheSynthesis

andSimulationDesignGuideformore

information.

INIT_00to

INIT_FF

HexadecimalAny256-BitValueAllzeroesAllowsspecicationoftheinitialcontentsof

the16Kbor32Kbdatamemoryarray.

INITP_00to

INITP_0F

HexadecimalAny256-BitValueAllzeroesAllowsspecicationoftheinitialcontentsof

the2Kbor4Kbparitydatamemoryarray .

VHDLInstantiationTemplate

Unlesstheyalreadyexist,copythefollowingtwostatementsandpastethembeforetheentitydeclaration.

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Chapter2:AboutUnimacros

LibraryUNISIM;

useUNISIM.vcomponents.all;

--BRAM_SINGLE_MACRO:SinglePortRAM

--Virtex-6

--XilinxHDLLibrariesGuide,version14.5

--Note-ThisUnimacromodelassumestheportdirectionstobe"downto".

--Simulationofthismodelwith"to"intheportdirectionscouldleadtoerroneousresults.

---------------------------------------------------------------------

--READ_WIDTH|BRAM_SIZE|READDepth|ADDRWidth|--

--WRITE_WIDTH||WRITEDepth||WEWidth--

--============|===========|=============|============|============--

--37-72|"36Kb"|512|9-bit|8-bit--

--19-36|"36Kb"|1024|10-bit|4-bit--

--19-36|"18Kb"|512|9-bit|4-bit--

--10-18|"36Kb"|2048|11-bit|2-bit--

--10-18|"18Kb"|1024|10-bit|2-bit--

--5-9|"36Kb"|4096|12-bit|1-bit--

--5-9|"18Kb"|2048|11-bit|1-bit--

--3-4|"36Kb"|8192|13-bit|1-bit--

--3-4|"18Kb"|4096|12-bit|1-bit--

--2|"36Kb"|16384|14-bit|1-bit--

--2|"18Kb"|8192|13-bit|1-bit--

--1|"36Kb"|32768|15-bit|1-bit--

--1|"18Kb"|16384|14-bit|1-bit--

---------------------------------------------------------------------

BRAM_SINGLE_MACRO_inst:BRAM_SINGLE_MACRO

genericmap(

BRAM_SIZE=>"18Kb",--TargetBRAM,"18Kb"or"36Kb"

DEVICE=>"VIRTEX6",--TargetDevice:"VIRTEX5","VIRTEX6","SPARTAN6"

DO_REG=>0,--Optionaloutputregister(0or1)

INIT=>X"000000000",--Initialvaluesonoutputport

INIT_FILE=>"NONE",

WRITE_WIDTH=>0,--Validvaluesare1-72(37-72onlyvalidwhenBRAM_SIZE="36Kb")

READ_WIDTH=>0,--Validvaluesare1-72(37-72onlyvalidwhenBRAM_SIZE="36Kb")

SRVAL=>X"000000000",--Set/Resetvalueforportoutput

WRITE_MODE=>"WRITE_FIRST",--"WRITE_FIRST","READ_FIRST"or"NO_CHANGE"