Xilinx Virtex-4 ML461 User manual

R

Virtex-4 ML461

Memory Interfaces

Development Board

User Guide

UG079 (v1.1) September 5, 2007

Virtex-4 ML461 Development Board User Guide www.xilinx.com UG079 (v1.1) September 5, 2007

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Virtex-4 ML461 Development Board

UG079 (v1.1) September 5, 2007

The following table shows the revision history for this document.

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Date Version Revision

11/15/04 1.0 Initial Xilinx release.

UG079 (v1.1) September 5, 2007 www.xilinx.com Virtex-4 ML461 Development Board User Guide

09/05/07 1.1 Chapter 1: Added XAPP721 to “Virtex-4 ML461 Memory Interfaces Development

Board” section.

Chapter 3: Added tables on voltage margining: Table 3-12, Table 3-13, and Table 3-14.

Updated “Hardware Overview.” Updated Table 3-2.

Chapter 4: Added “Power Measurements on the ML461” section. Updated link to

Samsung documentation in Table 4-1 and Table 4-3.

Chapter 5: Updated Read Data (Q) values in Table 5-5.

Appendix A: Updated FPGA pinout tables.

General text edits.

Date Version Revision

Virtex-4 ML461 Development Board User Guide www.xilinx.com UG079 (v1.1) September 5, 2007

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UG079 (v1.1) September 5, 2007

Chapter 1: Introduction

About the Virtex-4 ML461 Memory Interfaces Tool Kit. . . . . . . . . . . . . . . . . . . . . . . . 7

Virtex-4 ML461 Memory Interfaces Development Board . . . . . . . . . . . . . . . . . . . . . . 8

Chapter 2: Getting Started

Documentation and Reference Design CD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Initial Board Check Before Applying Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Applying Power to the Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Chapter 3: Hardware Description

Hardware Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Memory Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Direct Clocking Data Capture Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

DDR400 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

DDR2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

QDR II Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

RLDRAM II Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

External Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Liquid Crystal Display (LCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Configuration INIT and DONE LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

User Pushbutton Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Program Switch (PROG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

RS-232 Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Z-DOK+ Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Test Headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Voltage Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Power Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Board Design Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Chapter 4: Electrical Requirements

Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

FPGA Internal Power Budget. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Power Measurements on the ML461 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Chapter 5: Signal Integrity Recommendations and Simulations

Termination and Transmission Line Summaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

IBIS Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table of Contents

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Chapter 6: Configuration

Configuration Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

JTAG Chain. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

JTAG Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Parallel Cable IV Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

System ACE Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Appendix A: FPGA Pinouts

FPGA #1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

FPGA #2 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

FPGA #3 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

FPGA #4 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Appendix B: LCD Interface

General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Display Hardware Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Hardware Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Peripheral Device KS0713 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Controller – Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Controller – LCD Panel Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Controller – Power Supply Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Operation Example of the 64128EFCBC-3LP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Read/Write Characteristics (6800 Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Design Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

LCD Panel Used in Full Graphics Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

LCD Panel Used in Character Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Array Connector Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

UCF Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

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Chapter 1

Introduction

This chapter introduces the Virtex™-4 ML461 reference design. It contains the following

sections:

• ”About the Virtex-4 ML461 Memory Interfaces Tool Kit”

• ”Virtex-4 ML461 Memory Interfaces Development Board”

About the Virtex-4 ML461 Memory Interfaces Tool Kit

The Virtex-4 ML461 Memory Interfaces Tool Kit provides a complete development

platform to interface with external memory devices for designing and verifying

applications based on the Virtex-4 LX FPGA family. This kit allows designers to implement

high-speed applications with extreme flexibility using IP cores and customized modules.

The Virtex-4 LX FPGA, with its column-based architecture, makes it possible to develop

highly flexible memory interface applications.

The Virtex-4 ML461 Memory Interfaces Tool Kit includes the following:

• Virtex-4 ML461 Memory Interfaces Development Board (XC4VLX25-FF668 FPGA)

• 5V/6.5 A DC power supply

• Country-specific power supply line cord

• RS-232 serial cable, DB9-F to DB9-F

• Documentation and reference design CD-ROM

Optional items that also support development efforts include:

• Xilinx ISE™ software

• JTAG cable

• Xilinx Parallel Cable IV

FCRAM-II memory is not supported any longer on the ML461 board.

For assistance with any of these items, contact your local Xilinx distributor or visit the

Xilinx online store at www.xilinx.com

.

The heart of the Virtex-4 ML461 Memory Interfaces Tool Kit is the Virtex-4 ML461

Development Board. This manual provides comprehensive information on Rev B1 and

later revisions of this board.

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Virtex-4 ML461 Memory Interfaces Development Board

A high-level functional block diagram of the Virtex-4 ML461 Memory Interfaces

Development Board is shown in Figure 1-1.

The Virtex-4 ML461 Development Board includes the following major functional blocks:

• Four XC4VLX25-FF668 FPGAs (see DS112

: Virtex-4 Family Overview)

• DDR1 DIMM memory: Two PC-3200 DIMM sockets for up to 64M x 144 bits (see

XAPP709

)

• DDR400 components: 16M x 28 bits at 200 MHz clock speed

• DDR2 DIMM memory: Two PC2-4300 DIMM sockets for up to 64M x 144 bits (see

XAPP702

and XAPP721)

• DDR2-533 components: 8M x 28 bits at 267 MHz clock speed

• QDR II memory: 2M x 72 bits at up to 300 MHz clock speed (see XAPP703

)

• RLDRAM II memory: 16M x 36 bits at up to 400 MHz clock speed (see XAPP710

)

• One DB9-M RS232 port

• One 64 x 128 pixel Liquid Crystal Display (LCD)

• A System ACE™ CompactFlash (CF) Configuration Controller that allows storing

and downloading of up to eight FPGA configuration image files

• On-board power regulators with ±5% output margin test capabilities

Figure 1-1: Virtex-4 ML461 Development Board Block Diagram

DDR2 DIMM

144

DDR2 SDRAM

x4, x8,

x16

QDR II SRAM

72

RLDRAM II

36

FCRAM II

36

DDR1 DIMM

144

FPGA #1

LX25/

FF668

FPGA #2

LX25/

FF668

DDR1 SDRAM

x4, x8,

x16

SSTL2

SSTL18 HSTLHSTL/SSTL18

External Interfaces:

System ACE Controller,

ML410 Z-DOK+, LCD

UG079_c1_02_072905

FPGA #3

LX25/

FF668

FPGA #4

LX25/

FF668

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Figure 1-2 shows the Virtex-4 ML461 Development Board and indicates the locations of the

resident memory devices.

Figure 1-2: Virtex-4 ML461 Development Board

Source: Arial Narrow, 10 pt., white w/ drop shadow, F/L

DDR2 DIMM

DDR DIMM

System ACE

CompactFlash

Controller

FCRAM II

QDR II

SDRAM

LCD

Display

RLDRAM II

DDR2 SDRAM

DDR400

SDRAM

UG079_c1_02_102104

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Chapter 2

Getting Started

This chapter describes the items needed to configure the Virtex-4 ML461 Memory

Interfaces Development Board. The Virtex-4 ML461 Development Board is tested at the

factory after assembly and should be received in working condition. It is set up to load a

bitstream from the CompactFlash card at socket J6 through the System ACE controller

(U36).

This chapter contains the following sections:

• “Documentation and Reference Design CD”

• “Initial Board Check Before Applying Power”

• “Applying Power to the Board”

Documentation and Reference Design CD

The CD included in the Virtex-4 ML461 Memory Interfaces Tool Kit contains the design

files for the Virtex-4 ML461 Development Board, including schematics, board layout, and

reference design files. Open the ReadMe.rtf file on the CD to review the list of contents.

Initial Board Check Before Applying Power

Perform these steps before applying board power:

1. Set up the Configuration Mode Switch SW1.

See “Configuration Modes” on page 53 for all available modes for the Virtex-4 ML461

Development Board.

2. Confirm that the JTAG chain jumpers P9, P10, P26, and P60 are connecting pins 1 to 2.

This way, all four devices are in the chain. Otherwise, the ISE iMPACT software will

not find all four devices to configure. For more information see “JTAG Chain” on

page 54.

3. Make sure that no inhibit jumpers are present on any of the power supply regulator

modules. For more information, see “Voltage Regulators” on page 30.

4. The Virtex-4 ML461 Development Board has a 200 MHz on-board oscillator, which

provides a copy of a differential LVPECL clock to each of the four FPGAs through a

differential clock buffer (ICS853006). There is also a connection to a pair of SMA

connectors to provide a differential LVDS clock from an off-board signal generator.

Another differential clock buffer (ICS853006) provides a copy of this clock to each

FPGA. These clocks are available after configuration for the design to use for various

system clocks.

5. Insert the CompactFlash card included in the kit into socket J6 on the ML461

Development Board. To select the startup file, check that SW6 is set to position 0.

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Applying Power to the Board

The Virtex-4 ML461 Development Board is now ready to power on. The Virtex-4 ML461

Development Board is shipped with a country-specific AC line cord for the universal input

5V desktop power supply. Follow these steps to power on the Virtex-4 ML461

Development Board:

1. Confirm that the ON-OFF switch, SW4, is in the OFF position.

2. Plug the 5V desktop power supply into the 5V DC input barrel jack J9 on the Virtex-4

ML461 Development Board. Plug the desktop power supply AC line cord into an

electrical outlet supplying the appropriate voltage.

3. Turn SW4 to the ON position. The power indicators for all regulator modules should

come on, indicating output from the regulators. The System ACE status LED D9 comes

on when the System ACE controller (U36) extracts the BIT configuration file from the

CompactFlash card to the FPGA. If no CompactFlash card is installed in the card

socket J6 on the Virtex-4 ML461 Development Board, the red System ACE error LED

D11 flashes.

4. If a CompactFlash card is not installed in socket J6, a JTAG cable must be used to

configure the FPGAs. To use a Parallel Cable IV or other JTAG pod, download the

FPGA configuration bitstream into each FPGA. After the DONE LED (D1) comes on,

the FPGAs are configured and ready to use.

5. Eject the CompactFlash card from J6 after configuration is done and push the reset

button SW2.

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Chapter 3

Hardware Description

This chapter describes the major hardware blocks on the Virtex-4 ML461 Development

Board and provides useful design consideration. It contains the following sections:

• “Hardware Overview”

• “Memory Interfaces”

• “External Interfaces”

• “Board Design Considerations”

Hardware Overview

The ML461 Development/Evaluation system reference design is implemented with four

XC4VLX25-FF668 devices from the Virtex-4 FPGA device family to demonstrate high-

speed external memory application interfaces. The memory technologies supported by the

Virtex-4 ML461 Development Board are DDR1 (DIMM and discrete components), DDR2

(DIMM and discrete components), QDR II, and RLDRAM II.

Figure 3-1 is a high-level block diagram of the Virtex-4 ML461 Memory Interfaces

Development Board.

Figure 3-1: Virtex-4 ML461 Memory Interfaces Development Board Block Diagram

36

72

DDR2 Components

28

144

DDR2 DIMM

144

28

DDR1 DIMM

DDR1 Components

QDR II

72

36

FCRAM II

RLDRAM II

FPGA #4FPGA #3FPGA #2FPGA #1

Parallel IV Port

External Interface,

System ACE

Controller

MII Links Between FPGA #4 and Three Other FPGAs

Power Supply

+ Clocks

ML410 Z-DOK+ Interface

LCD Display

SSTL2 SSTL18 HSTL/SSTL18 HSTL

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Memory Interfaces

Table 3-1 summarizes the implementation of the Virtex-4 ML461 Development Board for

various memory types. The maximum speed goal is based on using faster speed grade

XC4VLX25-FF668-12 devices.

When a memory with a larger data/strobe ratio is implemented, for example, a x36 QDR II

device, the smaller configurations can also be demonstrated by programming the FPGA

for a smaller data width, such as a 9:1 data/strobe ratio for the QDR II device.

Figure 3-2 illustrates a detailed block diagram of the Virtex-4 ML461 Development Board

showing connectivity between the memory types and the four XC4VLX25-FF668 FPGAs.

The conventions for showing multiple loads on a net are as follows:

• stacks of devices are shown with overlapping blocks, such as two x4 devices for the

DDR1 component interface

• multiple signals are on the same arrow, such as Address/Control signals to most of

the memories

Table 3-1: Summary of ML461 Memory Interfaces

Memory Type

Maximum

Speed

Data Rate Data Width I/O Standard

Data/Strobe

Ratios

DDR2 DIMM 267 MHz 533 Mb/s 144 SSTL18 4:1, 8:1

DDR2 SDRAM 267 MHz 533 Mb/s 28 SSTL18 4:1, 8:1

DDR1 DIMM 200 MHz 400 Mb/s 144 SSTL2 4:1, 8:1

DDR1 SDRAM 200 MHz 400 Mb/s 28 SSTL2 4:1, 8:1

QDR II 300 MHz 1.2 Gb/s 72 HSTL 18:1, 36:1

RLDRAM II 300 MHz 600 Mb/s 36 HSTL Class II 9:1, 18:1

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Figure 3-2: ML461-XC4VLX25-FF668 Board Connectivity Diagram

ADDR/CNTL

36-Bit

RLDRAM II

36-Bit

FCRAM II

72-Bit

QDR II

28-Bit

DDR2

COMP

144-Bit

DDR2

DIMM

144-Bit

DDR1

DIMM

28-Bit

DDR1

COMP

Virtex-4

FPGA #1

(XC4VLX25-FF668)

448 I/Os

External Interfaces

8

16

4

8

16

4

72

36

18

ADDR/CNTL

Virtex-4

FPGA #2

(XC4VLX25-FF668)

448 I/Os

Virtex-4

FPGA #3

(XC4VLX25-FF668)

448 I/Os

Virtex-4

FPGA #4

(XC4VLX25-FF668)

448 I/Os

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Chapter 3: Hardware Description

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Direct Clocking Data Capture Method

The read data capture technique for all five memories (DDR1, DDR2, QDR II, and

RLDRAM II) is labeled as Direct Clocking method. Refer to XAPP701

: “Memory Interfaces

Data Capture Using Direct Clocking Technique” for a detailed description. Figure 3-3

shows a basic block diagram for all external memory interfaces on the Virtex-4 ML461

Development Board.

The memory controller in the respective FPGA sits in between the physical layer to the

external memory devices and the user interface. Refer to the respective application notes of

reference designs for each memory interface to understand the details of the memory

controller implementations.

Figure 3-3: Basic Memory Controller Block Diagram

UG079_c3_03_082807

External

Memory

Device

DCM

Datapath

Address and Controls

Data Bus

CLKs

Clock/Strobe

Rd/Wr Addr

Write Data

System

Clock

DCM Clocks

Ctrl

FPGA

Memory

Clock

Memory

Controller

State

Machine

Memory Interfaces Board

Read Data

User

Interface

(Testbench)

Virtex-4 ML461 Development Board User Guide www.xilinx.com 17

UG079 (v1.1) September 5, 2007

Memory Interfaces

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DDR400 Memory

The FPGA #1 device on the Virtex-4 ML461 Development Board is connected to DDR1

memories. The DDR1 memory interface includes:

• a 144-bit-wide DIMM connection to two 184-pin DDR1 DIMM sockets

• a 28-bit-wide datapath to four DDR400 memory discrete components

For the 144-bit-wide DIMM datapath, the data bytes are spread across multiple banks of

the FPGA #1 device. Figure 3-4 summarizes the distribution of DDR1 DIMM and discrete

component interface signals among the different banks of the FPGA #1 device.

Table 3-2 describes all the signals associated with DDR1 DIMM component memories. For

a bus or a group of signals, a shorthand method is used to describe these signals and

follows these rules:

1. All entities with a pair of square brackets represent a different signal.

For example, DDR1_[RAS,CAS,WE]_N represents three signals: DDR1_RAS_N,

DDR1_CAS_N, and DDR1_WE_N.

2. All numbers are represented as a range, for example, n:m, expands into (n-m+1)

unique signals.

For example, DDR1_A[12:0] represents 13 separate signals: DDR1_A12, DDR1_A11,

…., DDR1_A0.

3. Other items are listed within brackets separated by commas.

Figure 3-4: FPGA #1 Banks for DDR1 (SSTL2) Interfaces (Top View)

BANK 8 (64)

DIMM Bytes:

4, 5, 12, 13

BANK 10 (64)

DIMM Addr/Cntl

Component Bytes:

3

BANK 9 (64)

DIMM Bytes:

CB0_7, CB8_15

Component Bytes:

1,2

BANK 6 (64)

DIMM Bytes:

2, 3, 10, 11

Component Bytes:

0

BANK 7 (64)

DIMM Bytes:

6, 7, 14, 15

BANK 5 (64)

DIMM Bytes:

0, 1, 8, 9

BANK 0

(Configuration)

BANK 4 (16)

Global Clock Inputs

BANK 2 (16)

Component Control/Clocks

BANK 3 (16)

Inter-FPGA SERDES Links

BANK 1 (16)

Component Address

Note: Banks 1 & 2 do not have DCI capability due to lack of VRP/VRN.

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Chapter 3: Hardware Description

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For example, DDR1_CK[3:0]_[P,N] represents 4 * 2 = 8 signals to fully expand two sets

of brackets. That is, the eight signals are: DDR1_CK3_P, DDR1_CK3_N, DDR1_CK2_P,

…., DDR1_CK0_N.

To use Registered DDR1 DIMMs with the ML461 memory board, it is necessary to connect

Pin 10 of socket XP2 (reset#) and drive this signal with FPGA1.

Table 3-2: DDR1 DIMM Signal Summary

Board Signal Name(s) Bits Description Bank #

Schematic

Page #

DDR1_DIMM_A[12:0] 13 DDR1 DIMM Address 10 10

DDR1_DIMM_CK[5:0]_[P,N] 12 DDR1 DIMM Differential Clock 10 10

DDR1_DIMM_[RAS,CAS,WE]_N,

DDR1_DIMM_CKE, DDR1_DIMM_BA[1:0],

DDR1_DIMM_CS[3:0]_N,

10 DDR1 DIMM Control Signals 10 10

DDR1_DIMM_DQ_BY[0,1,8,9]_B[7:0],

DDR1_DIMM_DQS_BY[0,1,8,9]_L_P,

DDR1_DIMM_DM_DQS_BY[0,1,8,9]_H_P

40 DDR1 DIMM Data and Strobes:

Bytes 0, 1, 8, 9

68

DDR1_DIMM_DQ_BY[2,3,10,11]_B[7:0],

DDR1_DIMM_DQS_BY[2,3,10,11]_L_P,

DDR1_DIMM_DM_DQS_BY[2,3,10,11]_H_P

40 DDR1 DIMM Data and Strobes:

Bytes 0, 1, 8, 9

811

DDR1_DIMM_DQ_BY[4,5,12,13]_B[7:0],

DDR1_DIMM_DQS_BY[4,5,12,13]_L_P,

DDR1_DIMM_DM_DQS_BY[4,5,12,13]_H_P

40 DDR1 DIMM Data and Strobes:

Bytes 0, 1, 8, 9

57

DDR1_DIMM_DQ_BY[6,7,14,15]_B[7:0],

DDR1_DIMM_DQS_BY[6,7,14,15]_L_P,

DDR1_DIMM_DM_DQS_BY[6,7,14,15]_H_P

40 DDR1 DIMM Data and Strobes:

Bytes 6, 7, 14, 15

68

DDR1_DIMM_DQ_CB0_7_B[7:0],

DDR1_DIMM_DQS_CB0_7_L_P,

DDR1_DIMM_DM_DQS_CB0_7_H_P

10 DDR1 DIMM Data and Strobes:

Check Byte 0

99

DDR1_DIMM_DQ_CB8_15_B[7:0],

DDR1_DIMM_DQS_CB8_15_L_P,

DDR1_DIMM_DM_DQS_CB8_15_H_P

10 DDR1 DIMM Data and Strobes:

Check Byte 1

99

Notes:

1. DDR1_DIMM_CKE is connected to a 4.7K pull-down resistor.

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UG079 (v1.1) September 5, 2007

Memory Interfaces

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Table 3-3 describes all signals associated with DDR400 Component memories.

A copy of XAPP709

: "DDR SDRAM Controller Using Virtex-4 FPGA Devices" and its

corresponding reference design RTL code are included on the CD shipped with the ML461

Tool Kit. For a complete list of FPGA #1 signals and their pin locations, refer to Appendix

A, “FPGA Pinouts.”

Table 3-3: DDR400 Component Signal Summary

Board Signal Name(s) Bits Description

Bank

#

Schematic

Page #

DDR1_A[12:0] 13 DDR400 Component Address 1 4

DDR1_CK[3:0]_[P,N] 8 DDR400 Component Differential Clock 2 4

DDR1_[RAS,CAS,WE]_N, DDR1_CKE,

DDR1_BA[1:0], DDR1_CS[3:0]_N,

DDR1_DM_BY[3:0]

14 DDR400 Component Control Signals 2, 10 4, 10

DDR1_DQ_BY0_B[3:0],

DDR1_DQS_BY0_L_P

5 DDR400 Data and Strobe: Byte 0 6 8

DDR1_DQ_BY1_B[7:0],

DDR1_DQS_BY1_P

9 DDR400 Data and Strobe: Byte 1 6 8

DDR1_DQ_BY2_B[7:0],

DDR1_DQS_BY2_P

9 DDR400 Data and Strobe: Byte 2 6 8

DDR1_DQ_BY3_B[7:0],

DDR1_DQS_BY3_P

9 DDR400 Data and Strobe: Byte 3 6 8

Notes:

1. DDR1_CKE is connected to a 4.7K pull-down resistor.

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Chapter 3: Hardware Description

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DDR2 Memory

The FPGA #2 device on the Virtex-4 ML461 Development Board is connected to DDR2

memories. The DDR2 memory interface includes:

• a 144-bit-wide DIMM connection to two 240-pin DDR2 DIMM sockets

• a 28-bit-wide datapath to four DDR2 memory discrete components

For the 144-bit-wide DIMM datapath, the data bytes are spread across multiple banks of

the FPGA #2 device. Figure 3-5 summarizes the distribution of DDR2 DIMM and discrete

component interface signals among the different banks of the FPGA #2 device.

Table 3-4 describes all the signals associated with DDR2 DIMM component memories.

Figure 3-5: FPGA #2 Banks for DDR2 (SSTL18) Interfaces (Top View)

BANK 8 (64)

DIMM Bytes:

4, 5, 12, 13

BANK 10 (64)

DIMM Address/Control

Component Bytes:

3

BANK 9 (64)

DIMM Bytes:

CB0_7, CB8_15

Component Bytes:

1,2

BANK 6 (64)

DIMM Bytes:

2, 3, 10, 11

Component Bytes:

0

BANK 7 (64)

DIMM Bytes:

6, 7, 14, 15

BANK 5 (64)

DIMM Bytes:

0, 1, 8, 9

BANK 0

(Configuration)

BANK 4 (16)

Global Clock Inputs

BANK 2 (16)

Component Control/Clocks

BANK 3 (16)

Inter-FPGA SERDES Links

BANK 1 (16)

Component Address

Note: Banks 1 & 2 do not have DCI capability due to lack of VRP/VRN.

UG079_c3_05_072905

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Xilinx Virtex-4 ML461 User manual

Xilinx Virtex-4 ML461 User manual

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