XAUI v12.3 Product Guide www.xilinx.com 5
PG053 April 6, 2016 Product Specification
Introduction
The Xilinx
®
LogiCORE™ IP eXtended
Attachment Unit Interface (XAUI) core is a
high-performance, low-pin count 10-Gb/s
interface intended to allow physical separation
between the data link layer and physical layer
devices in a 10-Gigabit Ethernet system.
The XAUI core implements a single-speed
full-duplex 10-Gb/s Ethernet eXtended
Attachment Unit Interface (XAUI) solution for
the UltraScale™ architecture, Zynq®-7000 All
Programmable SoC, and 7-series devices.
Features
• Designed to 10-Gigabit Ethernet IEEE
802.3-2012 specification
• Supports 20G double-rate XAUI (Double
XAUI) using four transceivers at 6.25 Gb/s.
For devices and speed grades, see Speed
Grades.
• Uses four transceivers at 3.125 Gb/s line
rate to achieve 10-Gb/s data rate
• Implements Data Terminal Equipment (DTE)
XGMII Extender Sublayer (XGXS), PHY XGXS,
and 10GBASE-X Physical Coding Sublayer
(PCS) in a single netlist
• IEEE 802.3-2012 clause 45 Management
Data Input/Output (MDIO) interface
(optional)
• IEEE 802.3-2012 clause 48 State Machines
• Available under the Xilinx End User License
Agreement
IP Facts
LogiCORE IP Facts
Core Specifics
Supported Device
Family
(1)
1.For a complete list of supported devices, see Vivado IP catalog. See
Verification for supported speed grades.
UltraScale+™ Families,
UltraScale™ Architecture, Zynq®-7000, 7 Series
Devices
Supported User
Interfaces
64-bit XG
MII Interface
Resources
(2)
,
(3)
2.Resource utilizations for 20 G are the same as those for 10 G. For
detailed utilization numbers based upon configuration, see
Table 2-2 through Table 2-5.
3.Resource utilization depends on target device and configuration. See
Table 2-2 through Table 2-5 for detailed information.
See Table 2-2, Table 2-3, Table 2-4, and
Table 2-5.
Provided with Core
Design Files Encrypted RTL
Example Design VHDL and Verilog
Test Bench
VHDL Test Bench
Verilog Test Fixture
Constraints File Xilinx Design Constraints (XDC)
Simulation Model VHDL/Verilog
Supported S/W
Drivers
NA
Tested Design Flows
(4)
4.For the supported versions of the tools, see the Xilinx Design Tools:
Release Notes Guide.
Design Entry Vivado® Design Suite
Simulation
For supported simulators, see the
Xilinx Design Tools: Release Notes Guide
.
Synthesis Vivado Synthesis
Support
Provided by Xilinx, Inc.@ Xilinx Support web page