Altera Stratix III Device Handbook

101 Innovation Drive

San Jose, CA 95134

www.altera.com

Stratix III Device Handbook, Volume 1

SIII5V1-1.4

ii Altera Corporation

ignations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and

service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Al-

tera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants

performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make

changes to any products and services at any time without notice. Altera assumes no responsibility or liabil-

ity arising out of the application or use of any information, product, or service described herein except as

expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest ver-

sion of device specifications before relying on any published information and before placing orders for

products or services.

Altera Corporation iii

Contents

Chapter Revision Dates ......................................................................... xiii

About this Handbook .............................................................................. xv

How to Contact Altera ........................................................................................................................... xv

Typographic Conventions ..................................................................................................................... xv

Section I. Device Core

Chapter 1. Stratix III Device Family Overview

Introduction ............................................................................................................................................ 1–1

Features .............................................................................................................................................. 1–2

Architecture Features ............................................................................................................................ 1–5

Logic Array Blocks and Adaptive Logic Modules ...................................................................... 1–5

MultiTrack Interconnect .................................................................................................................. 1–6

TriMatrix Embedded Memory Blocks ........................................................................................... 1–7

DSP Blocks ......................................................................................................................................... 1–7

Clock Networks and PLLs .............................................................................................................. 1–8

I/O Banks and I/O Structure ......................................................................................................... 1–9

External Memory Interfaces ............................................................................................................ 1–9

High Speed Differential I/O Interfaces with DPA .................................................................... 1–10

Hot Socketing and Power-On Reset ............................................................................................ 1–10

Configuration .................................................................................................................................. 1–11

Remote System Upgrades ............................................................................................................. 1–12

IEEE 1149.1 (JTAG) Boundary Scan Testing ............................................................................... 1–12

Design Security ............................................................................................................................... 1–12

SEU Mitigation ................................................................................................................................ 1–13

Programmable Power .................................................................................................................... 1–13

Signal Integrity ............................................................................................................................... 1–14

Reference and Ordering Information ............................................................................................... 1–14

Software ........................................................................................................................................... 1–14

Ordering Information .................................................................................................................... 1–15

Referenced Documents ....................................................................................................................... 1–16

Document Revision History ............................................................................................................... 1–16

Chapter 2. Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices

Introduction ............................................................................................................................................ 2–1

Logic Array Blocks ................................................................................................................................ 2–1

LAB Interconnects ............................................................................................................................ 2–3

iv Altera Corporation

Contents Stratix III Device Handbook, Volume 2

LAB Control Signals ......................................................................................................................... 2–4

Adaptive Logic Modules ...................................................................................................................... 2–5

ALM Operating Modes ................................................................................................................... 2–8

Register Chain ................................................................................................................................. 2–20

ALM Interconnects ......................................................................................................................... 2–22

Clear and Preset Logic Control .................................................................................................... 2–23

LAB Power Management Techniques ......................................................................................... 2–23

Conclusion ............................................................................................................................................ 2–24

Referenced Documents ....................................................................................................................... 2–24

Document Revision History ............................................................................................................... 2–24

Chapter 3. MultiTrack Interconnect in Stratix III Devices

Introduction ............................................................................................................................................ 3–1

Row Interconnects ................................................................................................................................. 3–1

Column Interconnects ........................................................................................................................... 3–3

Memory Block Interface ........................................................................................................................ 3–8

DSP Block Interface ............................................................................................................................. 3–10

I/O Block Connections to Interconnect ............................................................................................ 3–13

Conclusion ............................................................................................................................................ 3–14

Document Revision History ............................................................................................................... 3–15

Chapter 4. TriMatrix Embedded Memory Blocks in Stratix III Devices

Introduction ............................................................................................................................................ 4–1

Overview ................................................................................................................................................. 4–1

TriMatrix Memory Block Types ..................................................................................................... 4–3

Parity Bit Support ............................................................................................................................. 4–3

Byte Enable Support ........................................................................................................................ 4–3

Packed Mode Support ..................................................................................................................... 4–5

Address Clock Enable Support ...................................................................................................... 4–5

Mixed Width Support ...................................................................................................................... 4–7

Asynchronous Clear ........................................................................................................................ 4–7

Error Correction Code (ECC) Support .......................................................................................... 4–8

Memory Modes ...................................................................................................................................... 4–9

Single Port RAM ............................................................................................................................. 4–10

Simple Dual-Port Mode ................................................................................................................. 4–12

True Dual-Port Mode ..................................................................................................................... 4–15

Shift-Register Mode ....................................................................................................................... 4–17

ROM Mode ...................................................................................................................................... 4–18

FIFO Mode ....................................................................................................................................... 4–19

Clocking Modes ................................................................................................................................... 4–19

Independent Clock Mode .............................................................................................................. 4–19

Input/Output Clock Mode ........................................................................................................... 4–20

Read/Write Clock Mode ............................................................................................................... 4–20

Single Clock Mode ......................................................................................................................... 4–20

Design Considerations ........................................................................................................................ 4–20

Selecting TriMatrix Memory Blocks ............................................................................................ 4–20

Conflict Resolution ......................................................................................................................... 4–21

Altera Corporation v

Contents Contents

Read During Write ......................................................................................................................... 4–21

Power-Up Conditions and Memory Initialization .................................................................... 4–24

Power Management ....................................................................................................................... 4–24

Conclusion ............................................................................................................................................ 4–24

Document Revision History ............................................................................................................... 4–25

Chapter 5. DSP Blocks in Stratix III Devices

Introduction ............................................................................................................................................ 5–1

DSP Block Overview ............................................................................................................................. 5–1

Simplified DSP Operation .................................................................................................................... 5–3

Operational Modes Overview ............................................................................................................. 5–9

DSP Block Resource Descriptions ..................................................................................................... 5–10

Input Registers ................................................................................................................................ 5–11

Multiplier and First-Stage Adder ................................................................................................. 5–15

Pipeline Register Stage .................................................................................................................. 5–16

Second-Stage Adder ....................................................................................................................... 5–16

Round and Saturation Stage ......................................................................................................... 5–17

Second Adder and Output Registers ........................................................................................... 5–17

Operational Mode Descriptions ........................................................................................................ 5–18

Independent Multiplier Modes ....................................................................................................5–18

9-, 12- and 18-Bit Multiplier .......................................................................................................... 5–18

36-Bit Multiplier ............................................................................................................................. 5–22

Double Multiplier ........................................................................................................................... 5–23

Two-Multiplier Adder Sum Mode ............................................................................................... 5–25

18 × 18 Complex Multiply ............................................................................................................. 5–29

Four-Multiplier Adder ................................................................................................................... 5–31

Multiply Accumulate Mode ......................................................................................................... 5–33

Shift Modes ...................................................................................................................................... 5–34

Rounding and Saturation Mode ................................................................................................... 5–36

DSP Block Control Signals ............................................................................................................ 5–39

Application Examples ......................................................................................................................... 5–41

FIR Example .................................................................................................................................... 5–41

FFT Example ................................................................................................................................... 5–48

Software Support ................................................................................................................................. 5–49

Conclusion ............................................................................................................................................ 5–49

Referenced Documents ....................................................................................................................... 5–49

Document Revision History ............................................................................................................... 5–50

Chapter 6. Clock Networks and PLLs in Stratix III Devices

Introduction ............................................................................................................................................ 6–1

Clock Networks in Stratix III Devices ................................................................................................. 6–1

Clock Input Connections to PLLs ................................................................................................ 6–12

Clock Output Connections ............................................................................................................ 6–13

Clock Source Control for PLLs ..................................................................................................... 6–14

Clock Control Block ....................................................................................................................... 6–16

Clock Enable Signals ...................................................................................................................... 6–20

PLLs in Stratix III Devices .................................................................................................................. 6–22

vi Altera Corporation

Contents Stratix III Device Handbook, Volume 2

Stratix III PLL Hardware Overview ............................................................................................ 6–24

Stratix III PLL Software Overview ............................................................................................... 6–28

Clock Feedback Modes .................................................................................................................. 6–32

Clock Multiplication and Division .............................................................................................. 6–38

Post-Scale Counter Cascading ...................................................................................................... 6–39

Programmable Duty Cycle ........................................................................................................... 6–40

PLL Control Signals ....................................................................................................................... 6–40

Clock Switchover ............................................................................................................................ 6–41

Programmable Bandwidth ............................................................................................................ 6–47

Phase-Shift Implementation ......................................................................................................... 6–50

PLL Reconfiguration ...................................................................................................................... 6–52

Spread-Spectrum Tracking ........................................................................................................... 6–64

PLL Specifications .......................................................................................................................... 6–64

Conclusion ............................................................................................................................................ 6–64

Referenced Documents ....................................................................................................................... 6–64

Document Revision History ............................................................................................................... 6–65

Section II. I/O Interfaces

Chapter 7. Stratix III Device I/O Features

Introduction ............................................................................................................................................ 7–1

Stratix III I/O Standards Support ....................................................................................................... 7–1

I/O Standards and Voltage Levels ................................................................................................ 7–3

Stratix III I/O Banks .............................................................................................................................. 7–5

Modular I/O Banks .......................................................................................................................... 7–8

Stratix III I/O Structure ...................................................................................................................... 7–14

3.3-V I/O Interface ......................................................................................................................... 7–15

External Memory Interfaces .......................................................................................................... 7–17

High-Speed Differential I/O with DPA Support ...................................................................... 7–17

Programmable Current Strength ................................................................................................. 7–18

Programmable Slew Rate Control ............................................................................................... 7–19

Programmable Delay ..................................................................................................................... 7–20

Open-Drain Output ........................................................................................................................ 7–20

Bus Hold .......................................................................................................................................... 7–21

Programmable Pull-Up Resistor .................................................................................................. 7–21

Programmable Pre-Emphasis .......................................................................................................7–22

Programmable Differential Output Voltage .............................................................................. 7–22

MultiVolt I/O Interface ................................................................................................................. 7–22

OCT Support ........................................................................................................................................ 7–23

LVDS Input On-Chip Termination (R

D

) ..................................................................................... 7–29

OCT Calibration ................................................................................................................................... 7–30

OCT Calibration Block Location ..................................................................................................7–30

OCT Calibration Block Modes of Operation .............................................................................. 7–33

Termination Schemes for I/O Standards ......................................................................................... 7–37

Single-Ended I/O Standards Termination ................................................................................. 7–37

Altera Corporation vii

Contents Contents

Differential I/O Standards Termination ..................................................................................... 7–39

Design Considerations ........................................................................................................................ 7–46

I/O Termination ............................................................................................................................. 7–46

I/O Banks Restrictions .................................................................................................................. 7–47

I/O Placement Guidelines ............................................................................................................ 7–48

Conclusion ............................................................................................................................................ 7–50

Referenced Documents ....................................................................................................................... 7–50

Chapter 8. External Memory Interfaces in Stratix III Devices

Introduction ............................................................................................................................................ 8–1

Memory Interfaces Pin Support .......................................................................................................... 8–6

Data and Data Clock/Strobe Pins .................................................................................................. 8–6

Optional Parity, DM, BWSn, ECC and QVLD Pins ................................................................... 8–18

Address and Control/Command Pins ........................................................................................ 8–19

Memory Clock Pins ........................................................................................................................ 8–20

Stratix III External Memory Interface Features ............................................................................... 8–21

DQS Phase-Shift Circuitry ............................................................................................................ 8–21

DQS Logic Block ............................................................................................................................. 8–32

Leveling Circuitry .......................................................................................................................... 8–36

Dynamic On-Chip Termination Control ..................................................................................... 8–38

I/O Element (IOE) Registers ........................................................................................................ 8–39

IOE Features .................................................................................................................................... 8–43

PLL ................................................................................................................................................... 8–45

Conclusion ............................................................................................................................................ 8–45

Referenced Documents ....................................................................................................................... 8–46

Document Revision History ............................................................................................................... 8–46

Chapter 9. High-Speed Differential I/O Interfaces and DPA in Stratix III Devices

Introduction ............................................................................................................................................ 9–1

I/O Banks ................................................................................................................................................ 9–2

LVDS Channels ...................................................................................................................................... 9–3

Differential Transmitter ........................................................................................................................ 9–4

Receiver Data Realignment Circuit (Bit Slip) ............................................................................... 9–9

Dynamic Phase Aligner (DPA) .....................................................................................................9–10

Soft-CDR Mode ............................................................................................................................... 9–11

Synchronizer ................................................................................................................................... 9–12

Programmable Pre-Emphasis and Programmable VOD ............................................................... 9–12

Differential I/O Termination ............................................................................................................. 9–13

Left/Right PLLs (PLL_Lx/ PLL_Rx) ................................................................................................ 9–14

Clocking ................................................................................................................................................ 9–15

Source-Synchronous Timing Budget ........................................................................................... 9–16

Differential Data Orientation ........................................................................................................ 9–17

Differential I/O Bit Position ......................................................................................................... 9–17

Receiver Skew Margin for Non-DPA .......................................................................................... 9–19

Differential Pin Placement Guidelines ............................................................................................. 9–21

Guidelines for DPA-Enabled Differential Channels ................................................................. 9–21

Guidelines for DPA-Disabled Differential Channels ................................................................ 9–29

viii Altera Corporation

Contents Stratix III Device Handbook, Volume 2

Referenced Documents ....................................................................................................................... 9–34

Document Revision History ............................................................................................................... 9–34

Section III. Hot Socketing, Configuration, Remote Upgrades, and

Testing

Chapter 10. Hot Socketing and Power-On Reset in Stratix III Devices

Introduction .......................................................................................................................................... 10–1

Stratix III Hot-Socketing Specifications ............................................................................................ 10–1

Devices Can Be Driven Before Power-Up .................................................................................. 10–2

I/O Pins Remain Tri-Stated During Power-Up ......................................................................... 10–2

Insertion or Removal of a Stratix III Device from a Powered-Up System ............................. 10–2

Hot Socketing Feature Implementation in Stratix III Devices ...................................................... 10–3

Power-On Reset Circuitry .................................................................................................................. 10–4

Power-On Reset Specifications .......................................................................................................... 10–6

Conclusion ............................................................................................................................................ 10–7

Referenced Documents ....................................................................................................................... 10–7

Document Revision History ............................................................................................................... 10–7

Chapter 11. Configuring Stratix III Devices

Introduction .......................................................................................................................................... 11–1

Configuration Devices ................................................................................................................... 11–1

Configuration Schemes ................................................................................................................. 11–1

Configuration Features ....................................................................................................................... 11–3

Configuration Data Decompression ............................................................................................ 11–4

Design Security Using Configuration Bitstream Encryption ................................................... 11–8

Remote System Upgrade ............................................................................................................... 11–8

Power-On Reset Circuit ................................................................................................................. 11–8

V

CCPGM

Pins ..................................................................................................................................... 11–9

V

CCPD

Pins ....................................................................................................................................... 11–9

Fast Passive Parallel Configuration ................................................................................................ 11–10

FPP Configuration Using a MAX II Device as an External Host .......................................... 11–10

FPP Configuration Using a Microprocessor ............................................................................. 11–21

Fast Active Serial Configuration (Serial Configuration Devices) ............................................... 11–21

Estimating Active Serial Configuration Time .......................................................................... 11–27

Programming Serial Configuration Devices ............................................................................ 11–28

Passive Serial Configuration ............................................................................................................ 11–31

PS Configuration Using a MAX II Device as an External Host ............................................. 11–31

PS Configuration Using a Microprocessor ............................................................................... 11–39

PS Configuration Using a Download Cable ............................................................................. 11–39

JTAG Configuration .......................................................................................................................... 11–43

Jam STAPL .................................................................................................................................... 11–50

Device Configuration Pins ............................................................................................................... 11–50

Conclusion .......................................................................................................................................... 11–60

Altera Corporation ix

Contents Contents

Referenced Documents ..................................................................................................................... 11–60

Document Revision History ............................................................................................................. 11–61

Chapter 12. Remote System Upgrades With Stratix III Devices

Introduction .......................................................................................................................................... 12–1

Enabling Remote Update .............................................................................................................. 12–4

Configuration Image Types .......................................................................................................... 12–5

Remote System Upgrade Mode ......................................................................................................... 12–6

Overview ......................................................................................................................................... 12–6

Remote Update Mode .................................................................................................................... 12–6

Dedicated Remote System Upgrade Circuitry ................................................................................ 12–8

Remote System Upgrade Registers ............................................................................................ 12–10

Remote System Upgrade State Machine ................................................................................... 12–13

User Watchdog Timer .................................................................................................................. 12–14

Quartus II Software Support ............................................................................................................ 12–15

altremote_update Megafunction ................................................................................................ 12–15

Conclusion .......................................................................................................................................... 12–16

Referenced Documents ..................................................................................................................... 12–16

Document Revision History ............................................................................................................. 12–16

Chapter 13. IEEE 1149.1 (JTAG) Boundary-Scan Testing in Stratix III Devices

Introduction .......................................................................................................................................... 13–1

IEEE Std. 1149.1 BST Architecture .................................................................................................... 13–2

IEEE Std. 1149.1 Boundary-Scan Register ........................................................................................ 13–4

Boundary-Scan Cells of a Stratix III Device I/O Pin ................................................................. 13–6

IEEE Std. 1149.1 BST Operation Control .......................................................................................... 13–9

SAMPLE/PRELOAD Instruction Mode ................................................................................... 13–12

EXTEST Instruction Mode .......................................................................................................... 13–14

BYPASS Instruction Mode .......................................................................................................... 13–16

IDCODE Instruction Mode ......................................................................................................... 13–17

USERCODE Instruction Mode ................................................................................................... 13–18

CLAMP Instruction Mode .......................................................................................................... 13–18

HIGHZ Instruction Mode ........................................................................................................... 13–18

I/O Voltage Support in JTAG Chain .............................................................................................. 13–18

IEEE Std. 1149.1 BST Circuitry ......................................................................................................... 13–20

IEEE Std. 1149.1 BST for Configured Devices ............................................................................... 13–21

IEEE Std. 1149.1 BST Circuitry (Disabling) .................................................................................... 13–21

IEEE Std. 1149.1 BST Guidelines ..................................................................................................... 13–22

Boundary-Scan Description Language (BSDL) Support .............................................................. 13–23

Conclusion .......................................................................................................................................... 13–23

Referenced Documents ..................................................................................................................... 13–23

Document Revision History ............................................................................................................. 13–24

x Altera Corporation

Contents Stratix III Device Handbook, Volume 2

Section IV. Design Security & Single Event Upset (SEU) Mitigation

Chapter 14. Design Security in Stratix III Devices

Introduction .......................................................................................................................................... 14–1

Stratix III Security Protection ............................................................................................................. 14–2

Security Against Copying ............................................................................................................. 14–2

Security Against Reverse Engineering ........................................................................................ 14–2

Security Against Tampering ......................................................................................................... 14–2

AES Decryption Block ......................................................................................................................... 14–3

Flexible Security Key Storage ............................................................................................................ 14–3

Stratix III Design Security Solution ................................................................................................... 14–4

Security Modes Available ................................................................................................................... 14–5

Supported Configuration Schemes ................................................................................................... 14–6

Conclusion ............................................................................................................................................ 14–9

Referenced Documents ....................................................................................................................... 14–9

Document Revision History ............................................................................................................... 14–9

Chapter 15. SEU Mitigation in Stratix III Devices

Introduction .......................................................................................................................................... 15–1

Configuration Error Detection ........................................................................................................... 15–2

User Mode Error Detection ................................................................................................................ 15–2

Automated Single Event Upset Detection .................................................................................. 15–6

Critical Error Detection ................................................................................................................. 15–6

Error Detection Pin Description ........................................................................................................ 15–7

CRC_ERROR Pin ............................................................................................................................ 15–7

CRITICAL ERROR Pin .................................................................................................................. 15–8

Error Detection Block .......................................................................................................................... 15–8

Error Detection Registers .............................................................................................................. 15–9

Error Detection Timing ..................................................................................................................... 15–11

Software Support .......................................................................................................................... 15–12

Recovering From CRC Errors .......................................................................................................... 15–14

Conclusion .......................................................................................................................................... 15–14

Referenced Documents ..................................................................................................................... 15–14

Document Revision History ............................................................................................................. 15–14

Section V. Power and Thermal Management

Chapter 16. Programmable Power and Temperature Sensing Diode in Stratix III Devices

Introduction .......................................................................................................................................... 16–1

Stratix III Power Technology ............................................................................................................. 16–2

Selectable Core Voltage ................................................................................................................. 16–2

Programmable Power Technology .............................................................................................. 16–3

Relationship Between Selectable Core Voltage and Programmable Power Technology .... 16–4

Stratix III External Power Supply Requirements ............................................................................ 16–5

Altera Corporation xi

Contents Contents

Temperature Sensing Diode ............................................................................................................... 16–6

External Pin Connections .............................................................................................................. 16–7

Conclusion ............................................................................................................................................ 16–7

Referenced Documents ....................................................................................................................... 16–7

Document Revision History ............................................................................................................... 16–8

Section VI. Packaging Information

Chapter 17. Stratix III Device Packaging Information

Introduction .......................................................................................................................................... 17–1

Thermal Resistance .............................................................................................................................. 17–2

Package Outlines ................................................................................................................................. 17–2

Referenced Documents ....................................................................................................................... 17–2

Document Revision History ............................................................................................................... 17–2

xii Altera Corporation

Contents Stratix III Device Handbook, Volume 2

Altera Corporation xiii

Chapter Revision Dates

The chapters in this book, Stratix III Device Handbook, Volume 1, were revised on the following dates.

Where chapters or groups of chapters are available separately, part numbers are listed.

Chapter 1. Stratix III Device Family Overview

Revised: November 2007

Part number: SIII51001-1.3

Chapter 2. Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices

Revised: October 2007

Part number: SIII51002-1.2

Chapter 3. MultiTrack Interconnect in Stratix III Devices

Revised: October 2007

Part number: SIII51003-1.1

Chapter 4. TriMatrix Embedded Memory Blocks in Stratix III Devices

Revised: November 2007

Part number: SIII51004-1.3

Chapter 5. DSP Blocks in Stratix III Devices

Revised: October 2007

Part number: SIII51005-1.2

Chapter 6. Clock Networks and PLLs in Stratix III Devices

Revised: November 2007

Part number: SIII51006-1.3

Chapter 7. Stratix III Device I/O Features

Revised: November 2007

Part number: SIII51007-1.3

Chapter 8. External Memory Interfaces in Stratix III Devices

Revised: November 2007

Part number: SIII51008-1.3

Chapter 9. High-Speed Differential I/O Interfaces and DPA in

Stratix III Devices

Revised: November 2007

Part number: SIII51009-1.3

xiv Altera Corporation

Chapter Revision Dates Stratix III Device Handbook, Volume 1

Chapter 10. Hot Socketing and Power-On Reset in Stratix III Devices

Revised: October 2007

Part number: SIII51010-1.2

Chapter 11. Configuring Stratix III Devices

Revised: November 2007

Part number: SIII51011-1.3

Chapter 12. Remote System Upgrades With Stratix III Devices

Revised: October 2007

Part number: SIII51012-1.2

Chapter 13. IEEE 1149.1 (JTAG) Boundary-Scan Testing in Stratix III Devices

Revised: November 2007

Part number: SIII51013-1.3

Chapter 14. Design Security in Stratix III Devices

Revised: October 2007

Part number: SIII51014-1.1

Chapter 15. SEU Mitigation in Stratix III Devices

Revised: October 2007

Part number: SIII51015-1.2

Chapter 16. Programmable Power and Temperature Sensing Diode

in Stratix III Devices

Revised: October 2007

Part number: SIII51016-1.2

Chapter 17. Stratix III Device

Packaging Information

Revised: November 2007

Altera Corporation xv

Preliminary

About this Handbook

This handbook provides comprehensive information about the Altera

®

Stratix

®

III family of devices.

How to Contact

Altera

For the most up-to-date information about Altera products, go to the

Altera world-wide web site at www.altera.com. For technical support on

this product, go to www.altera.com/mysupport. For additional

information about Altera products, consult the sources shown below.

Typographic

Conventions

This document uses the typographic conventions shown below.

Information Type USA & Canada All Other Locations

Technical support www.altera.com/mysupport/ www.altera.com/mysupport/

(800) 800-EPLD (3753)

(7:00 a.m. to 5:00 p.m. Pacific Time)

+1 408-544-8767

7:00 a.m. to 5:00 p.m. (GMT -8:00)

Pacific Time

Product literature www.altera.com www.altera.com

Altera literature services [email protected] [email protected]

Non-technical customer

service

(800) 767-3753 + 1 408-544-7000

7:00 a.m. to 5:00 p.m. (GMT -8:00)

Pacific Time

FTP site ftp.altera.com ftp.altera.com

Visual Cue Meaning

Bold Type with Initial

Capital Letters

Command names, dialog box titles, checkbox options, and dialog box options are

shown in bold, initial capital letters. Example: Save As dialog box.

bold type External timing parameters, directory names, project names, disk drive names,

filenames, filename extensions, and software utility names are shown in bold

type. Examples: f

MAX

, \qdesigns directory, d: drive, chiptrip.gdf file.

Italic Type with Initial Capital

Letters

Document titles are shown in italic type with initial capital letters. Example: AN 75:

High-Speed Board Design.

xvi Altera Corporation

Preliminary

Typographic Conventions Stratix III Device Handbook, Volume 1

Italic type Internal timing parameters and variables are shown in italic type.

Examples: t

PIA

, n + 1.

Variable names are enclosed in angle brackets (< >) and shown in italic type.

Example: <file name>, <project name>.pof file.

Initial Capital Letters Keyboard keys and menu names are shown with initial capital letters. Examples:

Delete key, the Options menu.

“Subheading Title” References to sections within a document and titles of on-line help topics are

shown in quotation marks. Example: “Typographic Conventions.”

Courier type Signal and port names are shown in lowercase Courier type. Examples: data1,

tdi, input. Active-low signals are denoted by suffix n, e.g., resetn.

Anything that must be typed exactly as it appears is shown in Courier type. For

example:

c:\qdesigns\tutorial\chiptrip.gdf. Also, sections of an

actual file, such as a Report File, references to parts of files (e.g., the AHDL

keyword

SUBDESIGN), as well as logic function names (e.g., TRI) are shown in

Courier.

1., 2., 3., and

a., b., c., etc.

Numbered steps are used in a list of items when the sequence of the items is

important, such as the steps listed in a procedure.

■

● • Bullets are used in a list of items when the sequence of the items is not important.

v The checkmark indicates a procedure that consists of one step only.

1 The hand points to information that requires special attention.

c

The caution indicates required information that needs special consideration and

understanding and should be read prior to starting or continuing with the

procedure or process.

w

The warning indicates information that should be read prior to starting or

continuing the procedure or processes.

r The angled arrow indicates you should press the Enter key.

f The feet direct you to more information on a particular topic.

Visual Cue Meaning

Altera Corporation Section I–1

Section I. Device Core

This section provides a complete overview of all features relating to the

Stratix

®

III device family, which is the most architecturally advanced,

high performance, low power FPGA in the market place. This section

includes the following chapters:

■ Chapter 1, Stratix III Device Family Overview

■ Chapter 2, Logic Array Blocks and Adaptive Logic Modules in

Stratix III Devices

■ Chapter 3, MultiTrack Interconnect in Stratix III Devices

■ Chapter 4, TriMatrix Embedded Memory Blocks in Stratix III Devices

■ Chapter 5, DSP Blocks in Stratix III Devices

■ Chapter 6, Clock Networks and PLLs in Stratix III Devices

Revision History

Refer to each chapter for its own specific revision history. For information

on when each chapter was updated, refer to the Chapter Revision Dates

section, which appears in the full handbook.

Section I–2 Altera Corporation

Device Core Stratix III Device Handbook, Volume 1

Altera Corporation 1–1

November 2007

1. Stratix III Device Family

Overview

Introduction

The Stratix

®

III family provides the most architecturally advanced, high

performance, low power FPGAs in the market place.

Stratix III FPGAs lower power consumption through Altera’s innovative

Programmable Power Technology, which provides the ability to turn on

the performance where needed and turn down the power consumption

everywhere else. Selectable Core Voltage and the latest in silicon process

optimizations are also employed to deliver the industry’s lowest power,

high performance FPGAs.

Specifically designed for ease of use and rapid system integration, the

Stratix III FPGA family offers three family variants optimized to meet

different application needs:

■ The Stratix III L family provides balanced logic, memory, and

multiplier ratios for mainstream applications.

■ The Stratix III E family is memory and multiplier rich for data-centric

applications.

Modular I/O banks with a common bank structure for vertical migration

lend efficiency and flexibility to the high speed I/O. Package and die

enhancements with dynamic on-chip termination, output delay and

current strength control provide best-in-class signal integrity.

Based on a 1.1-V, 65-nm all-layer copper SRAM process, the Stratix III

family is a programmable alternative to custom ASICs and

programmable processors for high performance logic, digital signal

processing (DSP), and embedded designs and architects.

Stratix III devices include optional configuration bit stream security

through volatile or non-volatile 256-bit Advanced Encryption Standard

(AES) encryption. Where ultra-high reliability is required, Stratix III

devices include automatic error detection circuitry to detect data

corruption by soft errors in the configuration random-access memory

(CRAM) and user memory cells.

SIII51001-1.3

1–2 Altera Corporation

Stratix III Device Handbook, Volume 1 November 2007

Introduction

Features

Stratix III devices offer the following features:

■ 48,000 to 338,000 equivalent logic elements (LEs), see Table 1–1

■ 2,430 to 20,497 Kbits of enhanced TriMatrix memory consisting of

three RAM block sizes to implement true dual-port memory and

first-in first-out (FIFO) buffers

■ High-speed DSP blocks provide dedicated implementation of 9×9,

12×12, 18×18, 36×36 multipliers (at up to 550 MHz), multiply-

accumulate functions, and finite impulse response (FIR) filters

■ I/O:GND:PWR ratio of 8:1:1 along with on-die and on-package

decoupling for robust signal integrity

■ Programmable Power Technology, which minimizes power while

maximizing device performance

■ Selectable Core Voltage, available in low-voltage devices (L ordering

code suffix), enables selection of lowest power or highest

performance operation

■ Up to 16 global clocks, 88 regional clocks and 116 peripheral clocks

per device

■ Up to 12 phase-locked loops (PLLs) per device that support PLL

reconfiguration, clock switchover, programmable bandwidth, clock

synthesis and dynamic phase shifting

■ Memory interface support with dedicated DQS logic on all I/O

banks

■ Support for high-speed external memory interfaces including

DDR,DDR2,DDR3 SDRAM, RLDRAM II, QDR II and QDR II+

SRAM on up to 24 modular I/O banks

■ Up to 1,104 user I/O pins arranged in 24 modular I/O banks that

support a wide range of industry I/O standards

■ Dynamic On-Chip Termination (OCT) with auto calibration support

on all I/O banks

■ High-speed differential I/O support with serializer/deserializer

(SERDES) and dynamic phase alignment (DPA) circuitry for 1.25

Gbps performance

■ Support for high-speed networking and communications bus

standards including SPI-4.2, SFI-4, SGMII, Utopia IV, 10 Gigabit

Ethernet XSLI, Rapid I/O and NPSI

■ The only high-density, high-performance FPGA with support for

256-bit (AES) volatile and non-volatile security key to protect

designs

■ Robust on-chip hot socketing and power sequencing support

■ Integrated cyclical redundancy check (CRC) for configuration

memory error detection with critical error determination for high

availability systems support

■ Built-in error correction coding (ECC) circuitry to detect and correct

configuration or user memory error due to SEU events

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Altera Stratix III Device Handbook

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