2. GOWIN
  3. IPUG548-1.11E
IPUG548-1.11E

GOWIN IPUG548-1.11E User guide

  • Hello! I've reviewed the Gowin SPDIF Receiver IP user guide and am ready to assist with your questions. This document details the features, signal definitions, operation, and GUI setup for using the SPDIF Receiver IP. It also covers its application in Gowin FPGA products, supporting sample rates from 8kHz to 192kHz and bit widths from 16bit to 24bit. I can help you with any details about this device, and its usage.
  • What is the working clock rate of the controller?
    What is the SPDIF recovery clock rate?
    What are the supported sample rates?
Gowin SPDIF Receiver IP
User Guide
IPUG548-1.11E,04/22/2021
Copyright © 2021 Guangdong Gowin Semiconductor Corporation. All Rights Reserved.
, Gowin and GOWINSEMI are trademarks of Guangdong Gowin Semiconductor
Corporation and are registered in China, the U.S. Patent and Trademark Office, and other
countries. All other words and logos identified as trademarks or service marks are the
property of their respective holders. No part of this document may be reproduced or
transmitted in any form or by any denotes, electronic, mechanical, photocopying, recording
or otherwise, without the prior written consent of GOWINSEMI.
Disclaimer
GOWINSEMI assumes no liability and provides no warranty (either expressed or implied)
and is not responsible for any damage incurred to your hardware, software, data, or
property resulting from usage of the materials or intellectual property except as outlined in
the GOWINSEMI Terms and Conditions of Sale. All information in this document should be
treated as preliminary. GOWINSEMI may make changes to this document at any time
without prior notice. Anyone relying on this documentation should contact GOWINSEMI for
the current documentation and errata.
Revision History
Date
Version
Description
05/10/2019
1.0E
Initial version published.
07/23/2020
1.1E
SPDIF recovery clock added.
04/22/2021
1.11E
Section 2.4 Signal Description updated.
Contents
IPUG548-1.11E
i
Contents
Contents ............................................................................................................... i
List of Figures ..................................................................................................... ii
List of Tables ...................................................................................................... iii
1 About This Guide ............................................................................................ 1
1.1 Purpose .............................................................................................................................. 1
1.2 Related Documents ............................................................................................................ 1
1.3 Terminology and Abbreviation ............................................................................................ 1
1.4 Support and Feedback ....................................................................................................... 1
2 Functional Description ................................................................................... 2
2.1 Overview ............................................................................................................................. 2
2.1.1 Features ........................................................................................................................... 2
2.1.2 Performance Reference .................................................................................................. 2
2.2 System Diagram ................................................................................................................. 3
2.3 Operating Pricinple ............................................................................................................. 4
2.3.1 Block Diagram ................................................................................................................. 4
2.3.2 SPDIF Frame Structure ................................................................................................... 4
2.3.3 BMC Encoding ................................................................................................................. 5
2.3.4 Controller Operating Flow ................................................................................................ 6
2.4 Signal Description ............................................................................................................... 6
2.4.1 Sigals of User Logic ......................................................................................................... 6
2.4.2 Signals of Receiver .......................................................................................................... 6
2.5 Parameter ........................................................................................................................... 6
2.6 Interface Timing .................................................................................................................. 7
3 Application....................................................................................................... 8
3.1 Overview ............................................................................................................................. 8
3.2 Application Diagram ............................................................................................................ 8
3.3 GUI...................................................................................................................................... 8
List of Figures
IPUG548-1.11E
ii
List of Figures
Figure 2-1 System Diagram ...................................................................................................... 3
Figure 2-2 Block Diagram ......................................................................................................... 4
Figure 2-3 Frame Format .......................................................................................................... 4
Figure 2-4 Subframe Format ..................................................................................................... 5
Figure 2-5 User Logic Timing .................................................................................................... 7
Figure 3-1 Application Diagram ................................................................................................. 8
Figure 3-2 Project View ............................................................................................................. 9
Figure 3-3 IP Core Generator View ........................................................................................... 10
Figure 3-4 SPDIF_RX_Top Instantiation ................................................................................... 10
List of Tables
IPUG548-1.11E
iii
List of Tables
Table 2-1 Performance Reference ............................................................................................ 3
Table 2-2 Signals of User Logic ................................................................................................ 6
Table 2-3 Signal of Receiver ..................................................................................................... 6
Table 2-4 GUI Paramrter ........................................................................................................... 6
1 About This Guide
1.1 Purpose
IPUG548-1.11E
1(10)
1 About This Guide
1.1 Purpose
Gowin SPDIF Receiver IP user guide describes the features, diagram,
signal definition, parameter, operation, timing and GUI of the product. It
aims to help users learn the usage of Gowin SPDIF Receiver IP to
accelerate product development.
1.2 Related Documents
The latest user guides are available on the Gowin website. See the
related documents at www.gowinsemi.com.
DS100, GW1N series of FPGA Products Data Sheet
DS226, GW2AR series of FPGA Products Data Sheet
DS102, GW2A series of FPGA Products Data Sheet
1.3 Terminology and Abbreviation
The terminology and abbreviations used in this manual are as shown
in Table 1-1.
Table 1-1 Abbreviations and Terminology
Terminology and Abbreviations
Full Name
FPGA
Field Programmable Gate Array
SPDIF
Sony/Philips Digital Interface Format
1.4 Support and Feedback
Gowin Semiconductor provides customers with comprehensive
technical support. If you have any questions, comments, or suggestions,
please feel free to contact us directly by the following ways.
Website: www.gowinsemi.com
E-mail:[email protected]
2 Functional Description
2.1 Overview
IPUG548-1.11E
2(10)
2 Functional Description
2.1 Overview
SPDIF (Sony/Philips Digital Interface Format) is a kind of digital audio
transmission interface. It usually outputs by using optical fiber and coaxial
line. The audio signal can be output to decoder to maintain high fidelity, and
it is widely used in DTS (Digital Theatre System).
In order to better serve FPGA users, reduce the difficulty of system
development and improve the speed of product development, a general
SPDIF receiver controller with low power is designed to realize the function
of SPDIF protocol and BMC encoding.
Gowin SPDIF receiver IP can be applied to Gowin all FPGA products
by using Gowin software.
2.1.1 Features
The input working clock rate of the controller shall not be less than
512Fs (FS is the audio sampling rate);
The data and clock is recovered by asynchronous sampling data with
high speed clock；
SPDIF recovery clock is an eighth of the input working clock of the
controller;
Supports 8KHz~192Khz sample rate;
Supports bit width of 16bit~24bit;
Supports IEC60958 (SPDIF) and AES3 PCM data transmission;
Locked time not greater than 1Fs;
Lower power consumption；
Can be synthesized.
2.1.2 Performance Reference
The frequency of Gowin SPDIF Receiver IP is mainly determined by
the max. frequency of the selected device. The specific device
performance test is shown below.
2 Functional Description
2.2 System Diagram
IPUG548-1.11E
3(10)
Table 2-1 Performance Reference
Programming Language
LUT4 Resources
Maximum Speed
Verilog
330
≥90MHz
Verilog
318
≥150MHz
2.2 System Diagram
The user logic of SPDIF Receiver controller mainly includes data,
control, clock, reset and other signals, and the transmitting only has input
data.
Figure 2-1 System Diagram
SPDIF Receiver
Controller
SPDIF Receiver
Controller
User Logic
User Logic
O_chan_status_bit
O_user_bit I_spdif_rx_data
I_clk
I_rst_n
O_block_start_flag
O_sub_frame0_flag
SPDIF
Transmitter
SPDIF
Transmitter
coaxial or optical
O_spdif_data_en
O_audio_d
O_parity_check_error
O_lock_flag
O_sub_frame1_flag
O_spdif_recovery_clk
2 Functional Description
2.3 Operating Pricinple
IPUG548-1.11E
4(10)
2.3 Operating Pricinple
2.3.1 Block Diagram
Figure 2-2 Block Diagram
I_spdif_rx_data
I_clk
Data
En_signal
SPDIF Receiver Controller
BMC
decode IDDR
Spdif Unpacking
Spdif
Phase
detect
The SPDIF Receiver controller includes SPDIF Unpacking, BMC
decode, SPDIF Phase detect, and IDDR modules.
Spdif Unpacking: Unpack the received Spdif data and transmit it to the
user port;
BMC decode: Decode the data transmitted from spdif;
Spdif Phase detect: Detect the phase of the data transmitted from
spdif;
IDDR: Realize 1:2 serial-parallel conversion.
2.3.2 SPDIF Frame Structure
Figure 2-3 Frame Format
Channel A Channel BYZ Channel A Channel BYX …… Channel A Channel BYX ……
Frame 191 Frame 0 Frame 1 Frame 191
Block
Sub-frame0 Sub-frame1
Frame 0
……
The SPDIF block is composed of 192 frames, and each frame is
composed of 2 subframes, which are divided into Channel A and Channel
B, respectively corresponding to the left and right channels. The length of
subframe data is 32 bits, including Preamble, Aux. Data, Audio Data, and
four bits information and check codes. A subframe is 4 Bytes, a frame is 8
Bytes, and a Block is 192 x 8 = 1536 Bytes.
2 Functional Description
2.3 Operating Pricinple
IPUG548-1.11E
5(10)
Figure 2-4 Subframe Format
1. Sync Preamble
There are X, Y and Z, which respectively indicate that the subframe is
the beginning of Channel 1, Channel 2, and Block.
2. Auxiliary
Currently, these four bits are used to store additional sample bits when
the audio data exceeds 20 bits. For example, when 24 bits of sample
data are to be transmitted, they are used to store the last four bits of
audio data.
3. Audio Sample Word
Store the actual sample data with a length of 20 bits and transmit it in
LSB priority mode. When the sample is less than 20 bits, the unused
LSB bits should be set to zero.
4. Validity Bit
This bit is used to identify whether the data in the subframe is correct. If
it sets to 0, it means that the data in the subframe is correct and can be
received; otherwise, if the bit is 1, it means that the receiving end
should ignore the subframe.
5. User Bit
This bit is user-defined bit. Each group of sample transmits one bit. 192
groups of sample are transmitted to form 192 bits of information, and
each channel has a group of 192 bits of user information.
6. Channel Status Bit
This bit is the same as the user bit, and each group of sample transmits
one bit. Finally, each channel has a group of 192 bits channel status
information. This 192 bits channel status information is divided into
professional and consumer, which is determined by the first bit. When it
is set to 1, it is in professional mode, and when it is set to 0, it is in
consumer mode.
7. Parity Bit
Parity Check is a simple error check method that uses Even Parity
Check to determine if an odd number of bits is wrong.
2.3.3 BMC Encoding
Biphase Mark Code, or BMC, belongs to a phase modulation encoding
method, which is used to mix clock signal and data signal for transmission.
Its principle is to use a double clock frequency of transmission bit rate
as a benchmark. An original data is split into two parts. When the data is 1,
shift the electrical level (0-1 - > 1-0) for one time in the clock cycle to make
the data into two data with different levels, to be10 or 01; When the data is
0, it does not need to shift levels, to be11 or 00. At the same time, the level
at the beginning of each bit should be different from the level at the end of
the previous bit, so that the receiver can determine the boundary of each
2 Functional Description
2.4 Signal Description
IPUG548-1.11E
6(10)
bit.
2.3.4 Controller Operating Flow
SPDIF Receiver controller operation process is as follows:
1. Before the controller enters into the operation state, the user logic
initializes the internal register and state machine by sending a reset
signal.
2. The controller will recover the data received from IDDR by detecting 10
or 01 in the input clock;
3. BMC decode the spdif data processed by phase detection module;
4. Carry out protocol analysis according to SPDIF protocol, and verify the
data.
5. Send audio data, user bit, validity bit, channel status bit and indicator
signals to the user interface.
2.4 Signal Description
2.4.1 Sigals of User Logic
Table 2-2 Signals of User Logic
No.
Signal Name
I/O
Description
Remarks
1
I_rst_n
I
Reset
The I/O
direction of
all the
signals
takes
controller
as
reference.
2
I_clk
I
Clock
3
O_audio_d
O
Audio data
4
O_user_bit
O
User bit data
5
O_chan_status_bit
O
Channel Status Bit data
6
O_spdif_data_en
O
Data valid signal
7
O_sub_frame0_flag
O
Sub Frame0 start flag
8
O_sub_frame1_flag
O
Sub Frame1 start flag
9
O_block_start_flag
O
Block start flag
10
O_parity_check_error
O
Parity check error (high level
indicating error code of current
subframe)
11
O_lock_flag
O
Lock flag
2.4.2 Signals of Receiver
Table 2-3 Signal of Receiver
No.
Signal Name
I/O
Description
Remarks
1
I_spdif_rx_data
I
Spdif transmission channel
data
The I/O direction of all the
signals takes the
controller as reference.
2.5 Parameter
This section introduces the GUI parameter of Gowin SPDIF Receiver
IP.
Table 2-4 GUI Paramrter
No.
Name
Value Range
Default Value
Description
1
SPDIF_DATA_WIDTH
16~24
24
Data width of audio data input
2 Functional Description
2.6 Interface Timing
IPUG548-1.11E
7(10)
2.6 Interface Timing
The user logic timing is as follows:
Figure 2-5 User Logic Timing
Note!
After enabling the clock enable signal, the controller needs to be reset first;
All input and output are aligned with the clock rising edge;
All data enable and flag signals are in one clock cycle, and the data and data enable
align to output.
O_spdif_recovery_clk is 1/8 of the input working clock.
3 Application
3.1 Overview
IPUG548-1.11E
8(10)
3 Application
3.1 Overview
This chapter describes how to configure parameters in the GUI and
generate SPDIF Receiver IP module.
3.2 Application Diagram
Figure 3-1 Application Diagram
SPDIF Receiver
Controller
SPDIF Receiver
Controller
User Logic
User Logic
O_chan_status_bit
O_user_bit I_spdif_rx_data
I_clk
I_rst_n
O_block_start_flag
O_sub_frame0_flag
SPDIF
Transmitter
SPDIF
Transmitter
coaxial or optical
O_spdif_data_en
O_audio_d
O_Parity_check_error
O_lock_flag
O_sub_frame1_flag
3.3 GUI
1. Start the Gowin Software and open an project, as shown below:
3 Application
3.3 GUI
IPUG548-1.11E
9(10)
Figure 3-2 Project View
2. Click "IP Core Generator" from the "Tools" menu, as shown below.
Click "SPDIF RX" and use the default parameters. Click "OK" to
generate SPDIF_RX_Top Module.
3 Application
3.3 GUI
IPUG548-1.11E
10(10)
Figure 3-3 IP Core Generator View
3. Instantiate the "SPDIF_RX_Top" module in the user application, as
shown below.
Figure 3-4 SPDIF_RX_Top Instantiation
/