GOWIN IPUG769-1.1E Video Frame Buffer IP User guide

Brand
GOWIN
Model
IPUG769-1.1E Video Frame Buffer IP
Type
User guide
GW1NSR Series of FPGA Products
Datasheet
DS861-1.6E, 03/30/2023
Copyright © 2023 Guangdong Gowin Semiconductor Corporation. All Rights Reserved.
, LittleBee, and GOWIN are trademarks of Guangdong Gowin Semiconductor
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or otherwise, without the prior written consent of GOWINSEMI.
Disclaimer
GOWINSEMI assumes no liability and provides no warranty (either expressed or implied)
and is not responsible for any damage incurred to your hardware, software, data, or
property resulting from usage of the materials or intellectual property except as outlined in
the GOWINSEMI Terms and Conditions of Sale. GOWINSEMI may make changes to this
document at any time without prior notice. Anyone relying on this documentation should
contact GOWINSEMI for the current documentation and errata.
Revision History
Date
Version
Description
11/15/2018
1.0E
Initial version published.
1/3/2019
1.1E
The recommended working voltage list updated;
The description about PSRAM reference manual
updated.
3/12/2019
1.2E
The environment temperature changed to junction
temperature;
Part name figures updated;
“LV” changed to “LX” and “UV” changed to “UX”.
11/13/2019
1.3E
Devices of GW1NSR-4 and GW1NSR-4C added.
02/20/2020
1.4E
Ordering information improved;
Chapter structure of AC/DC Characteristic improved.
04/16/2020
1.4.1E
Package Information updated;
CFU view updated.
06/28/2020
1.4.2E
The “QN48” package name of GW1NSR-2C/ GW1NSR-2
corrected as “QN48P”.
11/27/2020
1.4.3E
The Max. operating frequency of ARM Cortex-M3 updated.
07/12/2021
1.4.4E
The description of Cortex-M3 improved.
11/17/2021
1.4.5E
The I/O standards and ordering information updated.
07/21/2022
1.4.6E
Recommended operating conditions updated.
The maximum value of the differential input threshold
VTHD updated.
Note about USB 2.0 PHY added.
10/20/2022
1.5E
Note about DC current limit added.
Architecture overviews of GW1NSR series of FPGA
products updated.
Information on GW1NSR-2 and GW1NSR-2C deleted.
03/30/2023
1.6E
Table 3-1 Output I/O Standards and Configuration
Options updated.
Table 4-8 DC Electrical Characteristics over
Recommended Operating Conditions updated.
Section 3.7.4 Byte-enable removed.
Description of configuration Flash added.
Table 4-1 Absolute Max. Ratings updated.
Information on Slew Rate removed.
Table 4-24 GW1NSR-4C/4 User Flash Timing
Parameters updated.
Description added to 3.8 User Flash (GW1NSR-4C/4).
Description of true LVDS design modified.
Note about the default state of GPIO modified.
Table 4-3 Power Supply Ramp Rates updated.
Table 4-14 CLU Block Internal Timing Parameters
updated.
The I/O logic output diagram and the I/O logic input
diagram combined into Figure 3-7 I/O Logic Input and
Output .
Contents
DS861-1.6E
i
Contents
Contents ............................................................................................................... i
List of Figures .................................................................................................... iv
List of Tables ...................................................................................................... vi
1 About This Guide ............................................................................................. 1
1.1 Purpose .............................................................................................................................. 1
1.2 Related Documents ............................................................................................................ 1
1.3 Abbreviations and Terminology ........................................................................................... 2
1.4 Support and Feedback ....................................................................................................... 3
2 General Description ......................................................................................... 4
2.1 Features .............................................................................................................................. 4
2.2 Product Resources ............................................................................................................. 7
2.3 Package Information ........................................................................................................... 8
3 Architecture ...................................................................................................... 9
3.1 Architecture Overview ......................................................................................................... 9
3.2 PSRAM ..............................................................................................................................11
3.3 HyperRAM ........................................................................................................................ 12
3.4 NOR FLASH ..................................................................................................................... 13
3.5 Configurable Function Unit ............................................................................................... 13
3.6 IOB .................................................................................................................................... 15
3.6.1 I/O Buffer ....................................................................................................................... 16
3.6.2 True LVDS Design ......................................................................................................... 21
3.6.3 I/O Logic ........................................................................................................................ 22
3.6.4 I/O Logic Modes ............................................................................................................. 24
3.7 Block SRAM (BSRAM) ..................................................................................................... 29
3.7.1 Introduction .................................................................................................................... 29
3.7.2 Configuration Mode ....................................................................................................... 29
3.7.3 Mixed Data Bus Width Configuration ............................................................................. 31
3.7.4 Parity Bit ........................................................................................................................ 31
3.7.5 Synchronous Operation ................................................................................................. 32
3.7.6 Power up Conditions ..................................................................................................... 32
3.7.7 BSRAM Operation Modes ............................................................................................. 32
Contents
DS861-1.6E
ii
3.7.8 Clock Operations ........................................................................................................... 34
3.8 User Flash (GW1NSR-4C/4) ............................................................................................ 35
3.9 DSP .................................................................................................................................. 36
3.9.1 Introduction .................................................................................................................... 36
3.9.2 Macro ............................................................................................................................. 36
3.9.3 DSP Operations ............................................................................................................. 37
3.10 Cortex-M3 ....................................................................................................................... 37
3.10.1 Introduction .................................................................................................................. 37
3.10.2 Cortex-M3 .................................................................................................................... 39
3.10.3 Bus-Matrix .................................................................................................................... 40
3.10.4 NVIC ............................................................................................................................ 40
3.10.5 Boot Loader ................................................................................................................. 42
3.10.6 TimeStamp ................................................................................................................... 42
3.10.7 Timer ............................................................................................................................ 43
3.10.8 UART ........................................................................................................................... 44
3.10.9 Watchdog ..................................................................................................................... 47
3.10.10 GPIO .......................................................................................................................... 48
3.10.11 Debug Access Port .................................................................................................... 51
3.10.12 Memory Mapping ....................................................................................................... 52
3.10.13 Application ................................................................................................................. 52
3.11 Clock ............................................................................................................................... 53
3.11.1 Global Clock ................................................................................................................. 53
3.11.2 PLL ............................................................................................................................... 53
3.11.3 HCLK............................................................................................................................ 54
3.12 Long Wire (LW) ............................................................................................................... 55
3.13 Global Set/Reset (GSR) ................................................................................................. 55
3.14 Programming Configuration ............................................................................................ 55
3.14.1 SRAM Configuration .................................................................................................... 55
3.14.2 Flash Configuration ..................................................................................................... 55
3.15 On Chip Oscillator ........................................................................................................... 56
4 AC/DC Characteristic .................................................................................... 57
4.1 Operating Conditions ........................................................................................................ 57
4.1.1 Absolute Max. Ratings ................................................................................................... 57
4.1.2 Recommended Operating Conditions ........................................................................... 57
4.1.3 Power Supply Ramp Rates ........................................................................................... 58
4.1.4 Hot Socket Specifications .............................................................................................. 58
4.1.5 POR Specifications ........................................................................................................ 58
4.2 ESD .................................................................................................................................. 59
4.3 DC Electrical Characteristics ............................................................................................ 59
Contents
DS861-1.6E
iii
4.3.1 DC Electrical Characteristics over Recommended Operating Conditions .................... 59
4.3.2 Static Supply Current ..................................................................................................... 61
4.3.3 Recommended I/O Operating Conditions ..................................................................... 61
4.3.4 IOB Single‐Ended DC Electrical Characteristic .......................................................... 62
4.3.5 I/O Differential Electrical Characteristics ....................................................................... 63
4.4 AC Switching Characteristic ............................................................................................. 64
4.4.1 IO Speed ........................................................................................................................ 64
4.4.2 CLU Switching Characteristics ...................................................................................... 64
4.4.3 Clock and I/O Switching Characteristics........................................................................ 64
4.4.4 Gearbox Switching Characteristics ................................................................................ 65
4.4.5 BSRAM Switching Characteristics ................................................................................. 65
4.4.6 DSP Switching Characteristics ...................................................................................... 65
4.4.7 On chip Oscillator Switching Characteristics ................................................................. 65
4.4.8 PLL Switching Characteristics ....................................................................................... 66
4.5 Cortex-M3 Electrical Specification .................................................................................... 67
4.5.1 DC Characteristics ......................................................................................................... 67
4.5.2 AC Characteristics ......................................................................................................... 67
4.6 User Flash Characteristic (GW1NSR-4C/4) ..................................................................... 68
4.6.1 DC Characteristics ......................................................................................................... 68
4.6.2 AC Characteristics ......................................................................................................... 69
4.6.3 Operation Timing Diagrams ........................................................................................... 70
4.7 Configuration Interface Timing Specification .................................................................... 71
5 Ordering Information ..................................................................................... 72
5.1 Part Name ......................................................................................................................... 72
5.2 Package Mark ................................................................................................................... 74
List of Figures
DS861-1.6E
iv
List of Figures
Figure 3-1 GW1NSR-4 Architecture Overview .................................................................................. 9
Figure 3-2 GW1NSR-4C Architecture Overview ................................................................................ 9
Figure 3-3 CLU Structure ................................................................................................................... 14
Figure 3-4 IOB Structure View ........................................................................................................... 15
Figure 3-5 GW1NSR-4C/4 I/O Bank Distribution ............................................................................... 16
Figure 3-6 True LVDS Design ............................................................................................................ 21
Figure 3-7 I/O Logic Input and Output ............................................................................................... 22
Figure 3-9 IODELAY .......................................................................................................................... 23
Figure 3-10 Register Structure in I/O Logic ....................................................................................... 23
Figure 3-11 IEM Structure .................................................................................................................. 23
Figure 3-12 I/O Logic in Basic Mode ................................................................................................. 24
Figure 3-13 I/O Logic in SDR Mode ................................................................................................... 25
Figure 3-14 I/O Logic in DDR Input Mode ......................................................................................... 25
Figure 3-15 I/O Logic in DDR Output Mode ....................................................................................... 25
Figure 3-16 I/O Logic in IDES4 Mode ................................................................................................ 26
Figure 3-17 I/O Logic in OSER4 Mode .............................................................................................. 26
Figure 3-18 I/O Logic in IVideo Mode ................................................................................................ 26
Figure 3-19 I/O Logic in OVideo Mode .............................................................................................. 26
Figure 3-20 I/O Logic in IDES8 Mode ................................................................................................ 27
Figure 3-21 I/O Logic in OSER8 Mode .............................................................................................. 27
Figure 3-22 I/O Logic in IDES10 Mode .............................................................................................. 27
Figure 3-23 I/O Logic in OSER10 Mode ............................................................................................ 27
Figure 3-24 I/O Logic in IDES16 Mode .............................................................................................. 28
Figure 3-25 I/O Logic in OSER16 Mode ............................................................................................ 28
Figure 3-26 Pipeline Mode in Single Port, Dual Port and Semi-Dual Port ........................................ 32
Figure 3-27 Independent Clock Mode ............................................................................................... 34
Figure 3-28 Read/Write Clock Mode .................................................................................................. 34
Figure 3-29 Single Port Clock Mode .................................................................................................. 35
Figure 3-30 Cortex-M3 Architecture ................................................................................................... 39
Figure 3-31 DEMCR Register ............................................................................................................ 42
Figure 3-32 Timer0/ Timer1 Structure View ....................................................................................... 43
Figure 3-33 APB UART Buffering ...................................................................................................... 45
List of Figures
DS861-1.6E
v
Figure 3-34 Watchdog Operation ....................................................................................................... 47
Figure 3-35 Memory Mapping ............................................................................................................ 52
Figure 3-36 PLL Structure .................................................................................................................. 53
Figure 3-37 GW1NSR-4/GW1NSR-4C HCLK Distribution ................................................................ 55
Figure 4-1 User Flash Read Operation .............................................................................................. 70
Figure 4-2 User Flash Program Operation......................................................................................... 70
Figure 4-3 User Flash Erase Operation ............................................................................................. 71
Figure 5-1 GW1NSR-4 Part Naming–ES ........................................................................................... 72
Figure 5-2 GW1NSR-4C Part Naming–ES ........................................................................................ 73
Figure 5-3 GW1NSR-4 Part Naming – Production ............................................................................ 73
Figure 5-4 GW1NSR-4C Part Naming – Production ......................................................................... 73
Figure 5-5 GW1NSR-4 Package Mark .............................................................................................. 74
Figure 5-6 GW1NSR-4C Package Mark ............................................................................................ 74
List of Tables
DS861-1.6E
vi
List of Tables
Table 1-1 Abbreviations and Terminology .......................................................................................... 2
Table 2-1 Product Resources ............................................................................................................. 7
Table 2-2 Package Information, Max. User I/O, and LVDS Pairs ...................................................... 8
Table 3-1 Output I/O Standards and Configuration Options .............................................................. 16
Table 3-2 Input I/O Standards and Configuration Options ................................................................. 19
Table 3-3 Memory Size Configuration ................................................................................................ 30
Table 3-4 Dual Port Mixed Read/Write Data Width Configuration ..................................................... 31
Table 3-5 Semi Dual Port Mixed Read/Write Data Width Configuration ............................................ 31
Table 3-6 Clock Operations in Different BSRAM Modes ................................................................... 34
Table 3-7 NVIC Interrupt Vector Table ............................................................................................... 41
Table 3-8 Timer0/Timer1 Register ...................................................................................................... 44
Table 3-9 UART0/UART1 Register .................................................................................................... 46
Table 3-10 Watchdog Register ........................................................................................................... 48
Table 3-11 GPIO Register .................................................................................................................. 50
Table 3-12 Definition of the PLL Ports ............................................................................................... 54
Table 3-13 GW1NSR-4C/4 Oscillator Output Frequency Options ..................................................... 56
Table 4-1 Absolute Max. Ratings ....................................................................................................... 57
Table 4-2 Recommended Operating Conditions ................................................................................ 57
Table 4-3 Power Supply Ramp Rates ................................................................................................ 58
Table 4-4 Hot Socket Specifications .................................................................................................. 58
Table 4-5 POR Specifications ............................................................................................................ 58
Table 4-6 GW1NSR ESD - HBM ........................................................................................................ 59
Table 4-7 GW1NSR ESD – CDM ....................................................................................................... 59
Table 4-8 DC Electrical Characteristics over Recommended Operating Conditions ......................... 59
Table 4-9 Static Supply Current ......................................................................................................... 61
Table 4-10 Recommended I/O Operating Conditions ........................................................................ 61
Table 4-11 IOB Single‐Ended DC Electrical Characteristic ............................................................. 62
Table 4-12 I/O Differential Electrical Characteristics .......................................................................... 63
Table 4-13 IO Characteristics ............................................................................................................. 64
Table 4-14 CLU Block Internal Timing Parameters ............................................................................ 64
Table 4-15 External Switching Characteristics ................................................................................... 64
Table 4-16 Gearbox Internal Timing Parameters ............................................................................... 65
List of Tables
DS861-1.6E
vii
Table 4-17 BSRAM Internal Timing Parameters ................................................................................ 65
Table 4-18 DSP Internal Timing Parameters ..................................................................................... 65
Table 4-19 On chip Oscillator Output Frequency ............................................................................... 65
Table 4-20 PLL Parameters ............................................................................................................... 66
Table 4-21 Current Characteristics .................................................................................................... 67
Table 4-22 Clock Parameterss ........................................................................................................... 67
Table 4-23 GW1NSR-4C/4 User Flash DC Characteristic ................................................................. 68
Table 4-24 GW1NSR-4C/4 User Flash Timing Parameters ............................................................... 69
1 About This Guide
1.1 Purpose
DS861-1.6E
1(73)
1About This Guide
1.1 Purpose
This data sheet describes the features, product resources and
structure, AC/DC characteristics, timing specifications of the configuration
interface, and the ordering information of the GW1NSR series of FPGA
product. It is designed to help you understand the GW1NSR series of
FPGA products quickly and select and use devices appropriately.
1.2 Related Documents
The latest user guides are available on the GOWINSEMI Website. You
can find the related documents at www.gowinsemi.com:
UG290, Gowin FPGA Products Programming and Configuration User
Guide
UG863, GW1NSR series of FPGA Products Package and Pinout
UG864, GW1NSR-4 Pinout
UG865, GW1NSR-4C Pinout
1 About This Guide
1.3 Abbreviations and Terminology
DS861-1.6E
2(74)
1.3 Abbreviations and Terminology
The abbreviations and terminology used in this manual are as shown in
Table 1-1 below.
Table 1-1 Abbreviations and Terminology
Abbreviations and Terminology
AHB
ALU
APB
ARM
BSRAM
CFU
CLS
CRU
DAP
DCS
DNL
DP
DQCE
DWT
FPGA
GPIO
INL
IOB
ITM
LSB
LUT4
LUT5
LUT6
LUT7
LUT8
MG
NVIC
PHY
PLL
QN
REG
SAR
SDP
SFDR
1 About This Guide
1.4 Support and Feedback
DS861-1.6E
3(74)
Abbreviations and Terminology
SINAD
SoC
SP
SSRAM
TDM
Timer
TimeStamp
TPIU
UART
USB
Watchdog
1.4 Support and Feedback
Gowin Semiconductor provides customers with comprehensive
technical support. If you have any questions, comments, or suggestions,
please feel free to contact us directly using the information provided below.
Website: www.gowinsemi.com
E-mail: [email protected]
2 General Description
2.1 Features
DS861-1.6E
4(74)
2General Description
The GW1NSR series of FPGA products are the first generation
products in the LittleBee® family and represent one form of SIP chip. The
main difference between the GW1NS series and the GW1NSR series is
that the GW1NSR series integrates abundant PSRAM. The GW1NSR
series includes GW1NSR-4C and GW1NSR-4. When the ARM Cortex-M3
hard-core processor is employed as the core of GW1NSR-4C, the needs of
the Min. memory can be met. FPGA logic resources and other embedded
resources can flexibly facilitate the peripheral control functions, which
provide excellent calculation functions and exceptional system response
interrupts. They also offer high performance, low power consumption,
flexible usage, instant start-up, affordability, nonvolatile, high security, and
abundant package types, among other benefits. SoC devices achieve
seamless connection between programmable logic devices and embedded
processors. They are compatible with multiple peripheral device standards
and can, therefore, reduce costs of operation and be widely deployed in
industrial control, communication, Internet of Things, servo drive,
consumption fields, etc.
GOWINSEMI provides a new generation of FPGA hardware
development environment through market-oriented independent research
and development that supports the GW1NSR series of FPGA products and
applies to FPGA synthesizing, layout, place and routing, data bitstream
generation and download, etc.
2.1 Features
Lower power consumption
- 55nm embedded flash technology
- Core voltage: 1.2V
- GW1NSR-4C/4 supports LV
- Clock dynamically turns on and off
Integrated with HyperRAM/PSRAM
Integrated with NOR FLASH
Hard core processor
2 General Description
2.1 Features
DS861-1.6E
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- Cortex-M3 32-bit ARM processor
- ARM v7-M Thumb2 instruction set architecture optimized for
small-footprint embedded applications
- System timer (SysTick), providing a simple, 24-bit clear-on-write,
decrementing, wrap-on-zero counter with a flexible control
mechanism
- Thumb compatible Thumb-2-only instruction set processor core for
high code density
- GW1NSR-4C supports up to 80 MHz operating frequency
- Hardware-division and single-cycle-multiplication
- Integrated nested vectored interrupt controller (NVIC) providing
deterministic interrupt handling
- 26 interrupts with eight priority levels
- Memory protection unit (MPU), providing a privileged mode for
protecting operation system functionality
- Unaligned data access, enabling data to be efficiently packed into
memory
- Atomic bit manipulation (bit-banding), delivering maximum memory
utilization and streamlined peripheral control
- Timer0 and Timer1
- UART0 and UART1
- Watchdog
- Debug port: JTAG and TPIU
User Flash
- GW1NSR-4C/4 supports 256Kb storage space
- 32-bit data width
- 10,000 write cycles
- Greater than 10 years Data Retention at +85 ℃
Configuration Flash
- 10,000 write cycles
- Greater than 10 years Data Retention at +85 ℃
Multiple I/O Standards
- LVCMOS33/25/18/15/12; LVTTL33, SSTL33/25/18 I,
SSTL33/25/18 II, SSTL15; HSTL18 I, HSTL18 II, HSTL15 I; PCI,
LVDS25, RSDS, LVDS25E, BLVDSE
- MLVDSE, LVPECLE, RSDSE
- Input hysteresis option
- Supports 4mA,8mA,16mA,24mA,etc. drive options
2 General Description
2.1 Features
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- Individual Bus Keeper, Weak Pull-up, Weak Pull-down, and Open
Drain option
- Hot Socket
- Supports MIPI interface
- supports I3C
Abundant Slices
- Four input LUT (LUT4)
- Supports shifter register
Block SRAM with multiple modes
- Supports Dual Port, Single Port, and Semi Dual Port
- Supports bytes write enable
Flexible PLLs
- Frequency adjustment (multiply and division) and phase
adjustment
- Supports global clock
Built-in Flash programming
- Instant-on
- Supports security bit operation
- Supports AUTO BOOT and DUAL BOOT
Configuration
- JTAG configuration
- Supports on-chip DUAL BOOT configuration mode
- Multiple GowinCONFIG configuration modes: AUTOBOOT, SSPI,
MSPI, CPU, SERIAL
2 General Description
2.2 Product Resources
DS861-1.6E
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2.2 Product Resources
Table 2-1 Product Resources
Device
GW1NSR-4
GW1NSR-4C
LUT4
4,608
4,608
Flip-Flop (FF)
3,456
3,456
Block SRAM
BSRAM (bits)
180K
180K
BSRAM quantity
BSRAM
10
10
18 x 18 Multiplier
16
16
User Flash (bits)
256K
256K
PSRAM (bits)
64M
64M
HyperRAM(bits)
-
64M
NOR FLASH (bits)
–
32M
PLLs+DLLs
2+2
2+2
OSC
1,±5% accuracy
1,±5% accuracy
Hard core processor
–
Cortex-M3
Total number of I/O banks
4
4
Max. I/O
106
106
Core voltage
1.2V
1.2V
2 General Description
2.3 Package Information
DS861-1.6E
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2.3 Package Information
Table 2-3 Memory Information
Device
Package
Memory
Capacity
Bit Width
GW1NSR-4
MG64P
PSRAM
64Mb
16 bits
GW1NSR-4C
MG64P
PSRAM
64Mb
16 bits
QN48P
HyperRAM
8 bits
QN48G
NOR Flash
32Mb
1 bit
Table 2-2 Package Information, Max. User I/O, and LVDS Pairs
Package
Pitch(mm)
Size(mm)
GW1NSR-4
GW1NSR-4C
QN48P
0.4
6 x 6
-
39(4)
MG64P
0.5
4.2 x 4.2
55(8)
55(8)
QN48G
0.4
6 x 6
-
39(4)
Note!
The JTAGSEL_N and JTAG pins cannot be used as I/O simultaneously. The data in
this table is when the loaded four JTAG pins (TCK, TDI, TDO, and TMS) are used as
I/O; When mode [2:0] = 001, JTAGSEL_N and the four JTAG pins (TCK, TDI, TDO,
and TMS) can be used as GPIO simultaneously, and the Max. user I/O plus one. See
UG863, GW1NSR series of FPGA Products Package and Pinout User Guide for
more details.
The package types in this data sheet are written with abbreviations. See 5.1Part
Name.
Please refer to UG864, GW1NSR-4 Pinout, and UG865, GW1NSR-4C Pinout
3 Architecture
3.1 Architecture Overview
DS861-1.6E
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3Architecture
3.1 Architecture Overview
Figure 3-1 GW1NSR-4 Architecture Overview
Figure 3-2 GW1NSR-4C Architecture Overview
GW1NSR is one form of SIP chip, integrated with the GW1NS series
of FPGA products and PSRAM chip. For PSRAM features and overview,
see 3.2 PSRAM. For HypeRAM features and overview, see 3.3 HyperRAM.
For NOR FLASH features and overview, see 3.4 NOR FLASH.
I/OBank0
I/OBank3
CLU
I/OBank2
I/OBank1
DSP PLL
BSRAM
CLU
User Flash
PSRAM
IOB
CLU
BSRAM
Flash
OSC
OSC
PLL
CLU
Flash
UserFlash
PSRAM
CLU
CLU
DSP
IOB
IOB
IOB
IOB
CLU
CLU
IOB
IOB IOB IOB IOB
CLU
CLU
I/OBank0
I/OBank3
BSRAM
I/OBank2
I/OBank1
Cortex M3 PLL
DSP
User Flash HyperRAM
/ PSRAM/
NOR
FLASH
IOB
CLU
DSP
Flash
OSC
OSC
PLL
CLU
Flash
UserFlash
HyperRAM/PSRAM/
NOR FLASH
CLU
CLU
Cortex M3
IOB
IOB
IOB
IOB
CLU IOB
IOB IOB IOB IOB
CLU
BSRAM
3 Architecture
3.1 Architecture Overview
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Except for the basic units of CFU/CLU, I/O, GW1NSR series of FPGA
products include BSRAM, PLL, User Flash, on-chip oscillator, and Flash
resources for downloading. GW1NSR-2C also includes Cortex-M3, See
Table 2-1 for more detailed information.
Configurable Logic Unit (CLU) is the base cell for the array of the
GW1NSR series of FPGA Products. Devices with different capacities have
different numbers of rows and columns of CLUs.
The I/O resources in the GW1NSR series of FPGA products are
arranged around the periphery of the devices in groups referred to as
banks, including Bank0, Bank1, Bank2, and Bank3. The I/O resources
support multiple level standards, and support basic mode, SRD mode, and
generic DDR mode. For more detailed information, see 3.6 IOB.
The BSRAM is embedded as a row in the GW1NSR series of FPGA
products. In the FPGA array, each BSRAM occupies three columns of CLU.
BSRAM has two usages; however, these cannot be employed
simultaneously. One is for the Cortex-M3 processor SRAM in SoC devices,
which is used for memory data read/write. One BSRAM capacity is 16 Kbits,
and the total capacity is 128Kbits for GW1NSR-4/4C. One is for user
SRAM. One BSRAM capacity is 18 Kbits, and the total capacity is 180Kbits
for GW1NSR-4/4C. It supports multiple configuration modes and operation
modes. For further details, please refer to 3.7 Block SRAM (BSRAM).
The User Flash is embedded in the GW1NSR series of FPGA products,
without loss of data even if power off. The user flash in GW1NSR-4C/4 has
two usages, and these cannot be used simultaneously. One is used to
storage the ARM programs of Cortex-M3 processor. In this way, the User
Flash can only be read and cannot be written. One is used as the
non-volatile memory resource. See 3.8 User Flash (GW1NSR-4C/4) for
more detailed information.
The DSP is embedded in the GW1NSR series of FPGA products. DSP
blocks are embedded as a row in the FPGA array. Each DSP occupies nine
CLU columns. Each DSP block contains two Macros, and each Macro
contains two pre-adders, two multipliers with 18 by 18 inputs, and a three
input ALU54. For more detailed information, see 3.9 DSP.
GW1NSR series of FPGA products provide one PLL. PLL blocks
provide the ability to synthesize clock frequencies. Frequency adjustment
(multiply and division), phase adjustment, and duty cycle can be adjusted
using the configuration of parameters. There is an internal programmable
on-chip oscillator in each of the GW1NSR series of the FPGA product. The
on-chip oscillator supports the clock frequencies ranging from 2.5 MHz to
120MHz, providing the clock resource for the MSPI mode. It also provides
clock resource for user designs with the clock precision reaching ±5%. For
more detailed information, see 3.11 Clock.
The Flash resources embedded in the GW1NSR series of FPGA
products are used for built-in Flash programming, support instant start and
security bit operation, and support AUTO BOOT and DUAL BOOT
programming modes. For more detailed information, see 4.7 Configuration
Interface Timing Specification.
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GOWIN IPUG769-1.1E Video Frame Buffer IP User guide

Brand
GOWIN
Model
IPUG769-1.1E Video Frame Buffer IP
Type
User guide
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