Altera Stratix User manual

101 Innovation Drive

San Jose, CA 95134

(408) 544-7000

http://www.altera.com

Stratix Device Handbook, Volume 2

S5V2-3.5

ignations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and

service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Al-

tera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants

performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make

changes to any products and services at any time without notice. Altera assumes no responsibility or liabil-

ity arising out of the application or use of any information, product, or service described herein except as

expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest ver-

sion of device specifications before relying on any published information and before placing orders for

products or services.

ii Altera Corporation

Altera Corporation iii

Contents

Chapter Revision Dates ......................................................................... xiii

About This Handbook ............................................................................. xv

How to Find Information ...................................................................................................................... xv

How to Contact Altera ........................................................................................................................... xv

Typographic Conventions .................................................................................................................... xvi

Section I. Clock Management

Revision History ....................................................................................................................... Section I–1

Chapter 1. General-Purpose PLLs in Stratix & Stratix GX Devices

Introduction ............................................................................................................................................ 1–1

Enhanced PLLs ....................................................................................................................................... 1–5

Clock Multiplication & Division .................................................................................................... 1–9

External Clock Outputs ................................................................................................................. 1–10

Clock Feedback ............................................................................................................................... 1–14

Phase Shifting ................................................................................................................................. 1–14

Lock Detect ...................................................................................................................................... 1–15

Programmable Duty Cycle ........................................................................................................... 1–16

General Advanced Clear & Enable Control ............................................................................... 1–16

Programmable Bandwidth ............................................................................................................ 1–18

Clock Switchover ............................................................................................................................ 1–25

Spread-Spectrum Clocking ........................................................................................................... 1–25

PLL Reconfiguration ...................................................................................................................... 1–30

Enhanced PLL Pins ........................................................................................................................ 1–30

Fast PLLs ............................................................................................................................................... 1–31

Clock Multiplication & Division .................................................................................................. 1–34

External Clock Outputs ................................................................................................................. 1–34

Phase Shifting ................................................................................................................................. 1–35

Programmable Duty Cycle ........................................................................................................... 1–36

Control Signals ................................................................................................................................ 1–36

Pins ................................................................................................................................................... 1–37

Clocking ................................................................................................................................................ 1–39

Global & Hierarchical Clocking ................................................................................................... 1–39

Clock Input Connections ............................................................................................................... 1–41

Clock Output Connections ............................................................................................................ 1–43

Board Layout ........................................................................................................................................ 1–50

VCCA & GNDA ............................................................................................................................. 1–50

iv Altera Corporation

Contents Stratix Device Handbook, Volume 2

VCCG & GNDG .............................................................................................................................. 1–52

External Clock Output Power ...................................................................................................... 1–53

Guidelines ........................................................................................................................................ 1–56

Conclusion ............................................................................................................................................ 1–56

Section II. Memory

Revision History ..................................................................................................................... Section II–1

Chapter 2. TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices

Introduction ............................................................................................................................................ 2–1

TriMatrix Memory ................................................................................................................................. 2–1

Clear Signals ...................................................................................................................................... 2–3

Parity Bit Support ............................................................................................................................. 2–3

Byte Enable Support ........................................................................................................................ 2–4

Using TriMatrix Memory ..................................................................................................................... 2–7

Implementing Single-Port Mode .................................................................................................... 2–7

Implementing Simple Dual-Port Mode ......................................................................................... 2–8

Implementing True Dual-Port Mode .......................................................................................... 2–11

Implementing Shift-Register Mode ............................................................................................. 2–14

Implementing ROM Mode ............................................................................................................ 2–15

Implementing FIFO Buffers .......................................................................................................... 2–16

Clock Modes ......................................................................................................................................... 2–16

Independent Clock Mode .............................................................................................................. 2–16

Input/Output Clock Mode ........................................................................................................... 2–18

Read/Write Clock Mode ............................................................................................................... 2–21

Single-Port Mode ............................................................................................................................ 2–23

Designing With TriMatrix Memory .................................................................................................. 2–23

Selecting TriMatrix Memory Blocks ............................................................................................ 2–24

Pipeline & Flow-Through Modes ................................................................................................ 2–24

Power-up Conditions & Memory Initialization ......................................................................... 2–25

Read-During-Write Operation at the Same Address ..................................................................... 2–25

Same-Port Read-During-Write Mode .......................................................................................... 2–25

Mixed-Port Read-During-Write Mode ........................................................................................ 2–26

Conclusion ............................................................................................................................................ 2–27

Chapter 3. External Memory Interfaces in Stratix & Stratix GX Devices

Introduction ............................................................................................................................................ 3–1

External Memory Standards ................................................................................................................ 3–1

DDR SDRAM .................................................................................................................................... 3–1

RLDRAM II ....................................................................................................................................... 3–4

QDR & QDRII SRAM ...................................................................................................................... 3–6

ZBT SRAM ......................................................................................................................................... 3–8

DDR Memory Support Overview ..................................................................................................... 3–10

DDR Memory Interface Pins ......................................................................................................... 3–11

DQS Phase-Shift Circuitry ............................................................................................................ 3–15

Altera Corporation v

Contents Contents

DDR Registers ................................................................................................................................. 3–20

PLL ................................................................................................................................................... 3–27

Conclusion ............................................................................................................................................ 3–27

Section III. I/O Standards

Revision History .................................................................................................................... Section III–1

Chapter 4. Selectable I/O Standards in Stratix & Stratix GX Devices

Introduction ............................................................................................................................................ 4–1

Stratix & Stratix GX I/O Standards .................................................................................................... 4–1

3.3-V Low Voltage Transistor-Transistor Logic (LVTTL) - EIA/JEDEC Standard JESD8-B . 4–2

3.3-V LVCMOS - EIA/JEDEC Standard JESD8-B ........................................................................ 4–3

2.5-V LVTTL Normal Voltage Range - EIA/JEDEC Standard EIA/JESD8-5 .......................... 4–3

2.5-V LVCMOS Normal Voltage Range - EIA/JEDEC Standard EIA/JESD8-5 ..................... 4–3

1.8-V LVTTL Normal Voltage Range - EIA/JEDEC Standard EIA/JESD8-7 .......................... 4–4

1.8-V LVCMOS Normal Voltage Range - EIA/JEDEC Standard EIA/JESD8-7 ..................... 4–4

1.5-V LVCMOS Normal Voltage Range - EIA/JEDEC Standard JESD8-11 ............................ 4–4

1.5-V HSTL Class I & II - EIA/JEDEC Standard EIA/JESD8-6 ................................................. 4–5

1.5-V Differential HSTL - EIA/JEDEC Standard EIA/JESD8-6 ................................................ 4–6

3.3-V PCI Local Bus - PCI Special Interest Group PCI Local Bus Specification Rev. 2.3 ....... 4–6

3.3-V PCI-X 1.0 Local Bus - PCI-SIG PCI-X Local Bus Specification Revision 1.0a ................ 4–7

3.3-V Compact PCI Bus - PCI SIG PCI Local Bus Specification Revision 2.3 .......................... 4–7

3.3-V 1× AGP - Intel Corporation Accelerated Graphics Port Interface Specification 2.0 ..... 4–7

3.3-V 2× AGP - Intel Corporation Accelerated Graphics Port Interface Specification 2.0 ..... 4–8

GTL - EIA/JEDEC Standard EIA/JESD8-3 .................................................................................. 4–8

GTL+ .................................................................................................................................................. 4–8

CTT - EIA/JEDEC Standard JESD8-4 ............................................................................................ 4–9

SSTL-3 Class I & II - EIA/JEDEC Standard JESD8-8 .................................................................. 4–9

SSTL-2 Class I & II - EIA/JEDEC Standard JESD8-9A ............................................................. 4–10

SSTL-18 Class I & II - EIA/JEDEC Preliminary Standard JC42.3 ............................................ 4–11

Differential SSTL-2 - EIA/JEDEC Standard JESD8-9A ............................................................. 4–11

LVDS - ANSI/TIA/EIA Standard ANSI/TIA/EIA-644 .......................................................... 4–12

LVPECL ........................................................................................................................................... 4–13

Pseudo Current Mode Logic (PCML) ......................................................................................... 4–13

HyperTransport Technology - HyperTransport Consortium ................................................. 4–14

High-Speed Interfaces ......................................................................................................................... 4–15

OIF-SPI4.2 ........................................................................................................................................ 4–15

OIF-SFI4.1 ........................................................................................................................................ 4–15

10 Gigabit Ethernet Sixteen Bit Interface (XSBI) - IEEE Draft Standard P802.3ae/D2.0 ...... 4–16

RapidIO Interconnect Specification Revision 1.1 ....................................................................... 4–16

HyperTransport Technology - HyperTransport Consortium ................................................. 4–17

UTOPIA Level 4 – ATM Forum Technical Committee Standard AF-PHY-0144.001 ........... 4–17

Stratix & Stratix GX I/O Banks .......................................................................................................... 4–17

Non-Voltage-Referenced Standards ............................................................................................ 4–24

Voltage-Referenced Standards ..................................................................................................... 4–24

vi Altera Corporation

Contents Stratix Device Handbook, Volume 2

Mixing Voltage Referenced & Non-Voltage Referenced Standards ....................................... 4–25

Drive Strength ...................................................................................................................................... 4–26

Standard Current Drive Strength .................................................................................................4–26

Programmable Current Drive Strength ...................................................................................... 4–27

Hot Socketing ....................................................................................................................................... 4–27

DC Hot Socketing Specification ................................................................................................... 4–28

AC Hot Socketing Specification ................................................................................................... 4–28

I/O Termination .................................................................................................................................. 4–28

Voltage-Referenced I/O Standards ............................................................................................. 4–28

Differential I/O Standards ............................................................................................................ 4–29

Differential Termination (RD) ...................................................................................................... 4–29

Transceiver Termination ............................................................................................................... 4–30

I/O Pad Placement Guidelines .......................................................................................................... 4–30

Differential Pad Placement Guidelines ....................................................................................... 4–30

VREF Pad Placement Guidelines ................................................................................................. 4–31

Output Enable Group Logic Option in Quartus II .................................................................... 4–34

Toggle Rate Logic Option in Quartus II ...................................................................................... 4–35

DC Guidelines ................................................................................................................................. 4–35

Power Source of Various I/O Standards ......................................................................................... 4–38

Quartus II Software Support .............................................................................................................. 4–38

Compiler Settings ........................................................................................................................... 4–38

Device & Pin Options .................................................................................................................... 4–39

Assign Pins ...................................................................................................................................... 4–39

Programmable Drive Strength Settings ...................................................................................... 4–40

I/O Banks in the Floorplan View .................................................................................................4–40

Auto Placement & Verification of Selectable I/O Standards ................................................... 4–41

Conclusion ............................................................................................................................................ 4–42

More Information ................................................................................................................................ 4–42

References ............................................................................................................................................. 4–42

Chapter 5. High-Speed Differential I/O Interfaces in Stratix Devices

Introduction ............................................................................................................................................ 5–1

Stratix I/O Banks ................................................................................................................................... 5–1

Stratix Differential I/O Standards ................................................................................................. 5–2

Stratix Differential I/O Pin Location ............................................................................................. 5–5

Principles of SERDES Operation ......................................................................................................... 5–6

Stratix Differential I/O Receiver Operation ................................................................................. 5–7

Stratix Differential I/O Transmitter Operation ........................................................................... 5–9

Transmitter Clock Output ............................................................................................................. 5–10

Divided-Down Transmitter Clock Output ................................................................................. 5–10

Center-Aligned Transmitter Clock Output ................................................................................ 5–11

SDR Transmitter Clock Output ....................................................................................................5–12

Using SERDES to Implement DDR ................................................................................................... 5–13

Using SERDES to Implement SDR .................................................................................................... 5–14

Differential I/O Interface & Fast PLLs ............................................................................................. 5–16

Clock Input & Fast PLL Output Relationship ............................................................................ 5–18

Fast PLL Specifications .................................................................................................................. 5–20

Altera Corporation vii

Contents Contents

High-Speed Phase Adjust ............................................................................................................. 5–21

Counter Circuitry ........................................................................................................................... 5–22

Fast PLL SERDES Channel Support ............................................................................................ 5–23

Advanced Clear & Enable Control .............................................................................................. 5–25

Receiver Data Realignment ................................................................................................................ 5–25

Data Realignment Principles of Operation ................................................................................. 5–25

Generating the TXLOADEN Signal ............................................................................................. 5–27

Realignment Implementation ....................................................................................................... 5–28

Source-Synchronous Timing Budget ................................................................................................ 5–30

Differential Data Orientation ........................................................................................................ 5–30

Differential I/O Bit Position ......................................................................................................... 5–31

Timing Definition ........................................................................................................................... 5–32

Input Timing Waveform ............................................................................................................... 5–39

Output Timing ................................................................................................................................ 5–40

Receiver Skew Margin ................................................................................................................... 5–40

Switching Characteristics .............................................................................................................. 5–42

Timing Analysis .............................................................................................................................. 5–42

SERDES Bypass DDR Differential Signaling ................................................................................... 5–42

SERDES Bypass DDR Differential Interface Review ................................................................. 5–42

SERDES Clock Domains ................................................................................................................ 5–42

SERDES Bypass DDR Differential Signaling Receiver Operation .......................................... 5–43

SERDES Bypass DDR Differential Signaling Transmitter Operation ..................................... 5–44

High-Speed Interface Pin Locations ................................................................................................. 5–45

Differential I/O Termination ............................................................................................................. 5–46

R

D

Differential Termination .......................................................................................................... 5–46

HyperTransport & LVPECL Differential Termination ............................................................. 5–47

PCML Differential Termination ...................................................................................................5–47

Differential HSTL Termination .................................................................................................... 5–48

Differential SSTL-2 Termination .................................................................................................. 5–49

Board Design Consideration .............................................................................................................. 5–50

Software Support ................................................................................................................................. 5–51

Differential Pins in Stratix ............................................................................................................. 5–51

Fast PLLs .......................................................................................................................................... 5–52

LVDS Receiver Block ..................................................................................................................... 5–60

LVDS Transmitter Module ........................................................................................................... 5–65

SERDES Bypass Mode ................................................................................................................... 5–70

Summary ............................................................................................................................................... 5–75

Section IV. Digital Signal Processing (DSP)

Revision History .................................................................................................................... Section IV–1

Chapter 6. DSP Blocks in Stratix & Stratix GX Devices

Introduction ............................................................................................................................................ 6–1

DSP Block Overview ............................................................................................................................. 6–2

Architecture ............................................................................................................................................ 6–5

viii Altera Corporation

Contents Stratix Device Handbook, Volume 2

Multiplier Block ................................................................................................................................ 6–5

Adder/Output Block ....................................................................................................................... 6–9

Routing Structure & Control Signals ........................................................................................... 6–12

Operational Modes .............................................................................................................................. 6–18

Simple Multiplier Mode ................................................................................................................ 6–18

Multiply Accumulator Mode ........................................................................................................ 6–22

Two-Multiplier Adder Mode ........................................................................................................ 6–23

Four-Multiplier Adder Mode ....................................................................................................... 6–24

Software Support ................................................................................................................................. 6–28

Conclusion ............................................................................................................................................ 6–28

Chapter 7. Implementing High Performance DSP Functions

in Stratix & Stratix GX Devices

Introduction ............................................................................................................................................ 7–1

Stratix & Stratix GX DSP Block Overview ......................................................................................... 7–1

TriMatrix Memory Overview .............................................................................................................. 7–4

DSP Function Overview ....................................................................................................................... 7–5

Finite Impulse Response (FIR) Filters ................................................................................................. 7–5

FIR Filter Background ...................................................................................................................... 7–6

Basic FIR Filter .................................................................................................................................. 7–7

Time-Domain Multiplexed FIR Filters ........................................................................................ 7–13

Polyphase FIR Interpolation Filters .............................................................................................7–17

Polyphase FIR Decimation Filters ................................................................................................7–24

Complex FIR Filter ......................................................................................................................... 7–31

Infinite Impulse Response (IIR) Filters ............................................................................................. 7–34

IIR Filter Background .................................................................................................................... 7–34

Basic IIR Filters ............................................................................................................................... 7–36

Butterworth IIR Filters ................................................................................................................... 7–39

Matrix Manipulation ........................................................................................................................... 7–45

Background on Matrix Manipulation .......................................................................................... 7–45

Two-Dimensional Filtering & Video Imaging ........................................................................... 7–46

Discrete Cosine Transform (DCT) ..................................................................................................... 7–52

DCT Background ............................................................................................................................ 7–52

2-D DCT Algorithm ....................................................................................................................... 7–53

Arithmetic Functions ........................................................................................................................... 7–59

Background ..................................................................................................................................... 7–59

Arithmetic Function Implementation ......................................................................................... 7–60

Arithmetic Function Implementation Results ............................................................................ 7–62

Arithmetic Function Design Example ......................................................................................... 7–62

Conclusion ............................................................................................................................................ 7–62

References ............................................................................................................................................. 7–63

Section V. IP & Design Considerations

Revision History ..................................................................................................................... Section V–1

Altera Corporation ix

Contents Contents

Chapter 8. Implementing 10-Gigabit Ethernet Using Stratix & Stratix GX Devices

Introduction ............................................................................................................................................ 8–1

Related Links ..................................................................................................................................... 8–1

10-Gigabit Ethernet ................................................................................................................................ 8–1

Interfaces ................................................................................................................................................. 8–5

XSBI .................................................................................................................................................... 8–5

XGMII ............................................................................................................................................... 8–13

XAUI ................................................................................................................................................. 8–19

I/O Characteristics for XSBI, XGMII & XAUI ................................................................................. 8–21

Software Implementation .............................................................................................................. 8–22

AC/DC Specifications ................................................................................................................... 8–22

10-Gigabit Ethernet MAC Core ....................................................................................................8–24

Conclusion ....................................................................................................................................... 8–25

Chapter 9. Implementing SFI-4 in Stratix & Stratix GX Devices

Introduction ............................................................................................................................................ 9–1

System Topology .............................................................................................................................. 9–3

Interface Implementation in Stratix & Stratix GX Devices ......................................................... 9–5

AC Timing Specifications .............................................................................................................. 9–10

Electrical Specifications ................................................................................................................. 9–12

Software Implementation .............................................................................................................. 9–13

Conclusion ....................................................................................................................................... 9–13

Chapter 10. Transitioning APEX Designs to Stratix & Stratix GX Devices

Introduction .......................................................................................................................................... 10–1

General Architecture ........................................................................................................................... 10–1

Logic Elements ................................................................................................................................ 10–2

MultiTrack Interconnect ................................................................................................................ 10–3

DirectDrive Technology ................................................................................................................ 10–4

Architectural Element Names ...................................................................................................... 10–5

TriMatrix Memory ............................................................................................................................... 10–8

Same-Port Read-During-Write Mode ........................................................................................ 10–10

Mixed-Port Read-During-Write Mode ...................................................................................... 10–11

Memory Megafunctions .............................................................................................................. 10–12

FIFO Conditions ........................................................................................................................... 10–13

Design Migration Mode in Quartus II Software ...................................................................... 10–13

DSP Block ............................................................................................................................................ 10–16

DSP Block Megafunctions ........................................................................................................... 10–16

PLLs & Clock Networks ................................................................................................................... 10–18

Clock Networks ............................................................................................................................ 10–18

PLLs ................................................................................................................................................ 10–19

I/O Structure ...................................................................................................................................... 10–25

External RAM Interfacing ........................................................................................................... 10–25

I/O Standard Support ................................................................................................................. 10–26

High-Speed Differential I/O Standards .................................................................................... 10–26

altlvds Megafunction ................................................................................................................... 10–29

Configuration ..................................................................................................................................... 10–30

x Altera Corporation

Contents Stratix Device Handbook, Volume 2

Configuration Speed & Schemes ................................................................................................ 10–30

Remote Update Configuration ................................................................................................... 10–31

JTAG Instruction Support ........................................................................................................... 10–31

Conclusion .......................................................................................................................................... 10–32

Section VI. System Configuration & Upgrades

Revision History .................................................................................................................... Section VI–2

Chapter 11. Configuring Stratix & Stratix GX Devices

Introduction .......................................................................................................................................... 11–1

Device Configuration Overview ....................................................................................................... 11–2

MSEL[2..0] Pins ............................................................................................................................... 11–3

V

CCSEL

Pins ...................................................................................................................................... 11–3

PORSEL Pins ................................................................................................................................... 11–5

nIO_PULLUP Pins ......................................................................................................................... 11–5

TDO & nCEO Pins .......................................................................................................................... 11–6

Configuration File Size ....................................................................................................................... 11–6

Altera Configuration Devices ............................................................................................................ 11–7

Configuration Schemes ....................................................................................................................... 11–7

PS Configuration ............................................................................................................................ 11–7

FPP Configuration ........................................................................................................................ 11–21

PPA Configuration ....................................................................................................................... 11–30

JTAG Programming & Configuration ....................................................................................... 11–36

JTAG Programming & Configuration of Multiple Devices ................................................... 11–39

Configuration with JRunner Software Driver .......................................................................... 11–41

Jam STAPL Programming & Test Language ............................................................................ 11–42

Configuring Using the MicroBlaster Driver .................................................................................. 11–51

Device Configuration Pins ............................................................................................................... 11–51

Chapter 12. Remote System Configuration with Stratix & Stratix GX Devices

Introduction .......................................................................................................................................... 12–1

Remote Configuration Operation ...................................................................................................... 12–1

Remote System Configuration Modes ........................................................................................ 12–3

Remote System Configuration Components .............................................................................. 12–5

Quartus II Software Support ............................................................................................................ 12–12

altremote_update Megafunction ................................................................................................ 12–14

Remote Update WYSIWYG ATOM ........................................................................................... 12–17

Using Enhanced Configuration Devices ........................................................................................ 12–19

Local Update Programming File Generation ........................................................................... 12–21

Remote Update Programming File Generation ....................................................................... 12–32

Combining MAX Devices & Flash Memory .................................................................................. 12–42

Using an External Processor ............................................................................................................ 12–43

Conclusion .......................................................................................................................................... 12–44

Altera Corporation xi

Contents Contents

Section VII. PCB Layout Guidelines

Revision History .................................................................................................................. Section VII–1

Chapter 13. Package Information for Stratix Devices

Introduction .......................................................................................................................................... 13–1

Device & Package Cross Reference ................................................................................................... 13–1

Thermal Resistance .............................................................................................................................. 13–2

Package Outlines ................................................................................................................................. 13–3

484-Pin FineLine BGA - Flip Chip ............................................................................................... 13–4

672-Pin FineLine BGA - Flip Chip ............................................................................................... 13–6

780-Pin FineLine BGA - Flip Chip ............................................................................................... 13–8

956-Pin Ball Grid Array (BGA) - Flip Chip ............................................................................... 13–10

1,020-Pin FineLine BGA - Flip Chip .......................................................................................... 13–12

1,508-Pin FineLine BGA - Flip Chip .......................................................................................... 13–14

Chapter 14. Designing with 1.5-V Devices

Introduction .......................................................................................................................................... 14–1

Power Sequencing & Hot Socketing ................................................................................................. 14–1

Using MultiVolt I/O Pins ................................................................................................................... 14–2

Voltage Regulators .............................................................................................................................. 14–3

Linear Voltage Regulators ............................................................................................................. 14–5

Switching Voltage Regulators ...................................................................................................... 14–7

Maximum Output Current ........................................................................................................... 14–8

Selecting Voltage Regulators ........................................................................................................ 14–9

Voltage Divider Network ............................................................................................................ 14–10

1.5-V Regulator Circuits .............................................................................................................. 14–10

1.5-V Regulator Application Examples .......................................................................................... 14–19

Synchronous Switching Regulator Example ............................................................................ 14–20

Board Layout ...................................................................................................................................... 14–21

Split-Plane Method ....................................................................................................................... 14–23

Conclusion .......................................................................................................................................... 14–23

References ........................................................................................................................................... 14–24

xii Altera Corporation

Contents Stratix Device Handbook, Volume 2

Altera Corporation xiii

Chapter Revision Dates

The chapters in this book, Stratix Device Handbook, Volume 2, were revised on the following dates.

Where chapters or groups of chapters are available separately, part numbers are listed.

Chapter 1. General-Purpose PLLs in Stratix & Stratix GX Devices

Revised: July 2005

Part number: S52001-3.2

Chapter 2. TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices

Revised: July 2005

Part number: S52003-3.3

Chapter 3. External Memory Interfaces in Stratix & Stratix GX Devices

Revised: June 2006

Part number: SII52003-3.3

Chapter 4. Selectable I/O Standards in Stratix & Stratix GX Devices

Revised: June 2006

Part number: S52004-3.4

Chapter 5. High-Speed Differential I/O Interfaces in Stratix Devices

Revised: July 2005

Part number: S52005-3.2

Chapter 6. DSP Blocks in Stratix & Stratix GX Devices

Revised: July 2005

Part number: S52006-2.2

Chapter 7. Implementing High Performance DSP Functions in Stratix & Stratix GX Devices

Revised: September 2004

Part number: S52007-1.1

Chapter 8. Implementing 10-Gigabit Ethernet Using Stratix & Stratix GX Devices

Revised: July 2005

Part number: S52010-2.0

Chapter 9. Implementing SFI-4 in Stratix & Stratix GX Devices

Revised: July 2005

Part number: S52011-2.0

xiv Altera Corporation

Chapter Revision Dates Stratix Device Handbook, Volume 2

Chapter 10. Transitioning APEX Designs to Stratix & Stratix GX Devices

Revised: July 2005

Part number: S52012-3.0

Chapter 11. Configuring Stratix & Stratix GX Devices

Revised: July 2005

Part number: S52013-3.2

Chapter 12. Remote System Configuration with Stratix & Stratix GX Devices

Revised: September 2004

Part number: S52015-3.1

Chapter 13. Package Information for Stratix Devices

Revised: July 2005

Part number: S53008-3.0

Chapter 14. Designing with 1.5-V Devices

Revised: January 2005

Part number: C51012-1.1

Altera Corporation xv

About This Handbook

This handbook provides comprehensive information about the Altera

®

Stratix

®

family of devices.

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xvi Altera Corporation

Typographic Conventions Stratix Device Handbook, Volume 2

Typographic

Conventions

This document uses the typographic conventions shown below.

Visual Cue Meaning

Bold Type with Initial

Capital Letters

Command names, dialog box titles, checkbox options, and dialog box options are

shown in bold, initial capital letters. Example: Save As dialog box.

bold type External timing parameters, directory names, project names, disk drive names,

filenames, filename extensions, and software utility names are shown in bold

type. Examples: f

MAX

, \qdesigns directory, d: drive, chiptrip.gdf file.

Italic Type with Initial Capital

Letters

Document titles are shown in italic type with initial capital letters. Example: AN 75:

High-Speed Board Designs.

Italic type Internal timing parameters and variables are shown in italic type.

Examples: t

PIA

, n + 1.

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Example: <file name>, <project name>.pof file.

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shown in quotation marks. Example: “Typographic Conventions.”

Courier type Signal and port names are shown in lowercase Courier type. Examples: data1,

tdi, input. Active-low signals are denoted by suffix n, e.g., resetn.

Anything that must be typed exactly as it appears is shown in Courier type. For

example:

c:\qdesigns\tutorial\chiptrip.gdf. Also, sections of an

actual file, such as a Report File, references to parts of files (e.g., the AHDL

keyword

SUBDESIGN), as well as logic function names (e.g., TRI) are shown in

Courier.

1., 2., 3., and

a., b., c., etc.

Numbered steps are used in a list of items when the sequence of the items is

important, such as the steps listed in a procedure.

■

● • Bullets are used in a list of items when the sequence of the items is not important.

v The checkmark indicates a procedure that consists of one step only.

1 The hand points to information that requires special attention.

r The angled arrow indicates you should press the Enter key.

f The feet direct you to more information on a particular topic.

Altera Corporation Section I–1

Section I. Clock

Management

This section provides information on the different types of phase-lock

loops (PLLs). The feature-rich, enhanced PLLs assist you in managing

clocks internally and also have the ability to drive off-chip to control

system-level clock networks. The fast PLLs offer general-purpose clock

management with multiplication and phase shifting as well as

high-speed outputs to manage the high-speed differential I/O interfaces.

This chapter contains detailed information on the features, the

interconnections to the core and off-chip, and the specifications for both

types of PLLs.

This section contains the following:

■ Chapter 1, General-Purpose PLLs in Stratix & Stratix GX Devices

Revision History

The table below shows the revision history for Chapter 1.

Chapter Date/Version Changes Made

1 July 2005, v3.2 ● Removed information regarding delay shift (time delay elements).

● Updated Ta bl e 1 –8 .

● Updated “Clock Switchover” section.

● Updated Figure 1–22.

● Updated “Control Signals” section.

● Updated Table 1–16.

September 2004, v3.1

● Updated Note 1 in Table 1–17 on page 1–32.

● Updated Note 1 in Table 1–21 on page 1–48.

● Updated Table 1–12 on page 1–34.

April 2004, v3.0

● Changed PCI-X to PCI-X 1.0 throughout volume.

● Note 3 added to columns 11 and 12 in Table 1–1.

● Deleted “Stratix GX Clock Input Sources for Enhanced and Fast PLLs”

table.

● Deleted “Stratix GX Global and Regional Clock Output Line Sharing for

Enhanced and Fast PLLS” table.

● Deleted “Stratix GX CLK and FPLLCLK Input Pin Connections to Global

& Regional Clock Networks” table.

● Changed CLK checkmarks in Table 1–14.

● Updated notes to Table 1–3. and Figure 1–3.

● Added Table 1–7.

● Clock Switchover section has been moved to AN 313.

● Changed RCLK values in Figures 1–20 and 1–22.

Section I–2 Altera Corporation

Clock Management Stratix Device Handbook, Volume 2

1 November 2003, v2.2 ● Updated the “Lock Detect” section.

October 2003, v2.1

● Updated the “VCCG & GNDG” section.

● Updated Figure 1–14.

July 2003, v2.0

● Updated clock multiplication and division, spread spectrum, and Notes 1

and 8 in Table 1-3.

● Updated inclk[1..0] port name in Table 1-4.

● Updated ranges for EPLL post-scale and pre-scale dividers on page 1-9

● Added 1.8V HSTL support for EPLL in Table 1-6 and 1-13.

● New requirement to assert are set signal each PLL when it has to re-

acquire lock on either a new clock after loss of lock (page 1-16)

● Corrected input port extswitch to clkswitch throughout this

chapter.

● Updated clkloss description in Table 1-9.

● Updated text on jitter for spread spectrum on page 1-38.

● Removed PLL specifications. See Chapter 4 of Volume 1.

Chapter Date/Version Changes Made

Altera Corporation 1–1

July 2005

1. General-Purpose PLLs in

Stratix & Stratix GX Devices

Introduction

Stratix

®

and Stratix GX devices have highly versatile phase-locked loops

(PLLs) that provide robust clock management and synthesis for on-chip

clock management, external system clock management, and high-speed

I/O interfaces. There are two types of PLLs in each Stratix and Stratix GX

device: enhanced PLLs and fast PLLs. Each device has up to four

enhanced PLLs, which are feature-rich, general-purpose PLLs supporting

advanced capabilities such as external feedback, clock switchover, phase

and delay control, PLL reconfiguration, spread spectrum clocking, and

programmable bandwidth. There are also up to eight fast PLLs per

device, which offer general-purpose clock management with

multiplication and phase shifting as well as high-speed outputs to

manage the high-speed differential I/O interfaces.

The Altera

®

Quartus

®

II software enables the PLLs and their features

without requiring any external devices.

Tables 1–1 and 1–2 show PLL availability for Stratix and Stratix GX

devices, respectively.

Table 1–1. Stratix Device PLL Availability

Device

Fast PLLs Enhanced PLLs

1234 7 8 9 10 5(1) 6(1) 11(2) 12(2)

EP1S10

vvvv v v

EP1S20

vvvv v v

EP1S25

vvvv v v

EP1S30

vvvvv (3) v (3) v (3) v (3) vv

EP1S40

vvvvv (3) v (3) v (3) v (3) vvv (3) v (3)

EP1S60

vvvv v v v v v v v v

EP1S80

vvvv v v v v v v v v

Notes to Ta b le 1 – 1 :

(1) PLLs 5 and 6 each have eight single-ended outputs or four differential outputs.

(2) PLLs 11 and 12 each have one single-ended output.

(3) EP1S30 and EP1S40 devices do not support these PLLs in the 780-pin FineLine BGA

®

package.

S52001-3.2

1–2 Altera Corporation

Stratix Device Handbook, Volume 2 July 2005

Introduction

Table 1–2. Stratix GX Device PLL Availability

Device

Fast PLLs Enhanced PLLs

1278561112

EP1S10C

vv vv

EP1S10D

vv vv

EP1S25C

vv vv

EP1S25D

vv vv

EP1S25F

vv vv

EP1S40D

vvvvvvvv

EP1S40G

vvvvvvvv

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