Terasic TSOM User manual

Brand
Terasic
Model
TSOM
Type
User manual
TSoM Evaluation
User Manual
1
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March 8, 2019
TABLE OF CONTENTS
Chapter 1 Introduction ................................................................................................................... 3
1.1 Package Contents ................................................................................................................................ 3
1.2 TSoM Design Package ........................................................................................................................ 4
1.3 Getting Help ........................................................................................................................................ 4
Chapter 2 Board Specification ......................................................................................................... 5
2.1 Layout and Components ..................................................................................................................... 5
2.2 Block Diagram .................................................................................................................................... 6
Chapter 3 System Interface ............................................................................................................. 9
3.1 Settings of FPGA Configuration Mode ............................................................................................... 9
3.2 Configuration of Cyclone V SoC FPGA on TSoM evaluation kit .................................................... 10
3.3 Board Status Elements ...................................................................................................................... 16
3.4 Board Reset Elements ....................................................................................................................... 16
Chapter 4 HPS Fabric Components ............................................................................................... 18
4.1 Ethernet RJ45 .................................................................................................................................... 18
4.2 USB OTG Connector ........................................................................................................................ 19
4.3 UART to USB ................................................................................................................................... 20
4.4 Micro SD Card .................................................................................................................................. 21
4.5 QSPI Flash (DNI) ............................................................................................................................. 22
4.6 Raspberry Pi 2x13 GPIO .................................................................................................................. 23
Chapter 5 FPGA Fabric Components ............................................................................................. 26
5.1 TMD Header ..................................................................................................................................... 28
5.2 A/D Converter and Analog Input ...................................................................................................... 29
5.3 HDMI TX Interface .......................................................................................................................... 31
Chapter 6 Examples For FPGA ..................................................................................................... 33
6.1 HDMI TX .......................................................................................................................................... 33
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6.2 DDR3_RTL ....................................................................................................................................... 37
Appendix
40
Revision History ..................................................................................................................................... 40
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Chapter 1
Introduction
TSoM (Terasic SoC System on Module) Evaluation Kit is composed of TSoM module and Based
Board(TSoM-BB). TSoM module is small, integrated single-board computers with Cyclone® V
SoC at the core. The SoC SoM includes DDR3 memory, flash memory, power management,
common interface controllers. Users can install the TSoM based board on it through the 260-pin
edge connector, combined to a complete FPGA evaluation kit.
TSOM-BB is a based board developed based on TSoM card. The main purpose is providing
expansion interface, power and JTAG configuration function for TSoM, it connects the FPGA and
HPS fabric I/O of TSoM to many application interfaces, such as USB, Ethernet, HDMI, Micro SD
card and so on, it expanded the FPGA I/O which are connected to 260-pin edge connector to a
variety of applications. The TSoM based board also provides USB Blaster II circuit, users can
configure and debug the FPGA on TSoM through the JTAG interface. TSoM based board provides
power source to TSoM through the 260-pin edge connector. With the TSoM based board, users can
use TSoM Evaluation Kit to develop various FPGA projects.
1.1
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Figure 1-1 shows a photograph of TSoM Evaluation Kit.
Figure 1-1 TSoM Evaluation Kit Package Contents
The TSoM Evaluation Kit package includes:
1. TSOM Module (installed)
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2. TSOM Based board (TSOM-BB)
3. Quick Start Guide
4. Power DC Adapter (5V)
5. Type A to Mini-B USB Cable x2
6. MicroSD card (installed)
7. Four Silicon Footstands
1.2
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The TSoM Evaluation Kit design package contains all the documents and supporting materials
associated with TSoM Evaluation Kit, including the user manual, reference designs, and device
datasheets.
Users can download this design package from the link: http://TSoM.terasic.com/cd.
1.3
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Here are the addresses where you can get help if you encounter any problems:
Terasic Technologies
9F., No.176, Sec.2, Gongdao 5th Rd, East Dist, Hsinchu City, 30070. Taiwan
Email: [email protected]
Tel.: +886-3-575-0880
Website: TSoM.terasic.com
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Chapter 2
Board Specification
This chapter provides an introduction to the features and design characteristics of the board.
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Figure 2-1 and Figure 2-2 shows a photograph of the TSoM Evaluation Kit (TSoM module
board and TSOM Based Board). It depicts the layout of the board and indicates the location of the
connectors and key components.
Figure 2-1 TSoM Evaluation Kit (Top View)
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Figure 2-2 TSoM Evaluation Kit (Back View)
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Figure 2-3 is the block diagram of the TSoM Evaluation Kit and Figure 2-4 shows the block
diagram of the TSoM Module board
Figure 2-3 Block diagram of the TsoM evaluation kit
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Figure 2-4 Block diagram of the TSoM Module
Detailed information about TSoM module and TSOM based board are listed below.
◼ TSoM Module
⚫ FPGA: Cyclone V SE 5CSEBA6U23I7NDK (110K LEs)
⚫ Interface: DDR4 Edge (include 3.3V power source)
⚫ Dimension: 50 mm x 70 mm
⚫ FPGA Fabric side:
⚫ DDR3 SDRAM 1GB, 32bit – 303MHz (Soft IP)
⚫ LVDS Transmitter x15 & LVDS Receiver x17 pairs & GPIO x3 (Total GPIO x67)
⚫ Optional EPCS64
⚫ HPS Fabric side:
⚫ Boot Selection DIP Switch: boot from eMMC or MicroSD Card
⚫ DDR3 SDRAM 1GB, 32bit - 400MHz
⚫ USB 2.0 PHY
⚫ Gigabit Ethernet PHY
⚫ 3.3V GPIO x25 (Can/UART/SPI/I2C/Trace Buses)
⚫ 1.5V GPI x4 (Input pins)
⚫ Optional eMMC 8GB
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◼ TSOM based board
⚫ System:
⚫ Power source: 5V DC
⚫ on-board USB Blaster II
⚫ DDR4 socket for TSOM installation
⚫ FPGA Fabric:
⚫ LED x 2, Key x 2, Switch x 2
⚫ HDMI TX v1.4, 1080P Full-HD, Compatible with HDCP v1.4
⚫ TMD Header x2 (support 16 GPIO)
⚫ ADC, 8-channel, 12-bit, 500Ksps
⚫ HPS Fabric:
⚫ MicroSD Socket
⚫ Optional 512Mb QSPI FLASH (Need to rework Boot Selection resistor on Module)
⚫ USB to UART (USB OTG PHY, Mini-B Connector)
⚫ Ethernet (RJ45 Connector)
⚫ USB OTG (Micro-AB Connector)
⚫ 2x13 GPIO (include I2C/UART/SPI), Compatible with Raspberry Pi Expansion IO
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Chapter 3
System Interface
This chapter provides an instruction for the system interface of the TSoM evaluation kit.
3.1
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Since the factory setting of MSEL[4:0] on the TSoM module is FPPx32 mode, it means that when
the TSoM evaluation kit is power on. The FPGA is configured from the HPS fabric. When the
software on the HPS is running, the FPGA can be configured via HPS.
As shown in the Figure 3-1, there are 3 storage devices can be supported on TSoM evaluation kit to
boot HPS: SD Card, QSPI flash and eMMC flash. The eMMC flash is embedded in the TSoM
module. The SD Card and QSPI Flash are on the TSoM based board. The QSPI Flash is the option
function and don’t install on the board. Users can apply it on their own if needed.
Figure 3-1 Boot device for HPS on the TsoM evaluation kit
As described in section 3.1 of the TSoM module manual, the SD card shares the same HPS data bus
as the eMMC flash. Therefore, only one of these two storage devices can be used to boot HPS at the
same time. Users can switch between the two boot devices through the switch SW1 on the TSOM
module board (See Figure 3-2). The factory default boot device is SD card interface (SW1 is set to
"down" position).
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Figure 3-2 eMMC/SD Card select switch
If users need to use QSPI flash to boot HPS, you can refer to section 3.1 in TSoM module manual to
modify some resistors to change the HPS boot device.
If the user wants to the FPGA is configured by EPCS on TSoM evaluation kit when power on. Then
refer to section 3.1 of the TSoM module manual for EPCS part. Modify the MSEL[4:0] resistor on
the TSoM module to AS mode.
3.2
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There are two types of programming method supported by TSoM evaluation kit:
1. JTAG programming: It is named after the IEEE standards Joint Test Action Group. The
configuration bit stream is downloaded directly into the Cyclone V SoC FPGA. The FPGA will
retain its current status as long as the power keeps applying to the board; the configuration
information will be lost when the power is off.
2. AS programming: The other programming method is Active Serial configuration. The
configuration bit stream is downloaded into the serial configuration device (EPCS64), which
provides non-volatile storage for the bit stream. The information is retained within EPCS64
even if the TSoM evaluation kit board is turned off. When the board is powered on, the
configuration data in the EPCS64 device is automatically loaded into the Cyclone V SoC
FPGA.
◼ JTAG Chain on TSoM Evaluation Kit
The FPGA device can be configured through JTAG interface on TSoM evaluation kit board, but the
JTAG chain must form a closed loop, which allows Quartus II programmer to the detect FPGA
device. Figure 3-3 illustrates the JTAG chain on TSoM evaluation kit board.
In addition, the TSoM evaluation kit has one external JTAG Header (J7) reserved for users to
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connect to JTAG chain of the TSoM evaluation kit via external blaster. The J7 header is not
installed, so users need to solder a 2.54mm 2 x 5 male pin header if it is necessary.
Figure 3-3 Path of the JTAG chain
◼ Configure the FPGA in JTAG Mode
There are two devices (FPGA and HPS) on the JTAG chain. The following shows how the FPGA is
programmed in JTAG mode step by step.
Open the Quartus II programmer, please Choose Tools > Programmer. The Programmer window
opens. Please click “Hardware Setup”, as circled in Figure 3-4.
Figure 3-4 Programmer Window
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If it is not already turned on, turn on the DE-SoC [USB-1] option under currently selected hardware
and click “Close” to close the window. See Figure 3-5.
Figure 3-5 Hardware Setting
Return to the Quartus II programmer and click “Auto Detect”, as circled in Figure 3-6.
Figure 3-6 Detect FPGA device in JTAG mode
If the device is detected, the window of the selection device is opened, Please select detected device
associated with the board and click “OK” to close the window, as circled in Figure 3-7.
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Figure 3-7 Select 5CSEBA6 device
Both FPGA and HPS are detected, as shown in Figure 3-8.
Figure 3-8 FPGA and HPS detected in Quartus programmer
Right click on the FPGA device and open the .sof file to be programmed, as highlighted in Figure
3-9.
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Figure 3-9 Open the .sof file to be programmed into the FPGA device
Select the .sof file to be programmed, as shown in Figure 3-10.
Figure 3-10 Select the .sof file to be programmed into the FPGA device
Click “Program/Configure” check box and then click “Start” button to download the .sof file into
the FPGA device, as shown in Figure 3-11.
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Figure 3-11 Program .sof file into the FPGA device
◼ Configure the FPGA in AS Mode
The TSoM evaluation kit board uses a serial configuration device (EPCS64) to store configuration
data for the Cyclone V SoC FPGA. This configuration data is automatically loaded from the serial
configuration device chip into the FPGA when the board is powered up.
Users need to use Serial Flash Loader (SFL) to program the serial configuration device via JTAG
interface. The FPGA-based SFL is a soft intellectual property (IP) core within the FPGA that bridge
the JTAG and Flash interfaces. The SFL Megafunction is available in Quartus II. Figure 3-12
shows the programming method when adopting SFL solution.
Figure 3-12 Programming a serial configuration device with SFL solution
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3.3
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In addition to the 9 LEDs that FPGA/HPS device can control, there are 6 indicators which can
indicate the board status (See Figure 3-13), please refer the details in Table 3-1.
Figure 3-13 LED Indicators on TSoM evaluation kit
Table 3-1 LED Indicators
Board Reference
Description
LED2
Illuminate when 3.3V power is active.
LED10
Illuminate when 5V power is active.
LED4
Illuminate when data is transferred from JTAG to USB Host.
LED5
Illuminate when data is transferred from USB Host to JTAG.
TXD1
Illuminate when data is transferred from FT232R to USB Host.
RXD1
Illuminate when data is transferred from USB Host to FT232R.
3.4
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There are two HPS reset buttons on TSoM evaluation kit, HPS (cold) reset and HPS warm reset, as
shown in Figure 3-14. Table 3-2 describes the purpose of these two HPS reset buttons. Figure 3-15
is the reset tree for TSoM evaluation kit.
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Figure 3-14 HPS cold and warm reset buttons on TSoM evaluation kit
Table 3-2 Description of Two HPS Reset Buttons on TSoM evaluation kit
Board Reference
Signal Name
Description
Button1(TSoM
Based board)
HPS_RESET_N
Cold reset to the HPS, Ethernet PHY and USB host device.
Active low input which resets all HPS logics that can be reset.
KEY1 (TSoM
Module board)
HPS_WARM_RST_N
Warm reset to the HPS block. Active low input affects the system
reset domain for debug purpose.
Figure 3-15 HPS reset tree on TSoM evaluation kit board
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Chapter 4
HPS Fabric Components
This chapter describes the interfaces connected to TSoM Based Board. Users can access these
interfaces via the HPS processor on the TSoM module.
4.1
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The board supports a RJ-45 connector, which is provided by the TsoM Based Board. Figure 4-1
shows the connections between the TSoM module, 260 Pin edge connector and RJ-45 connector.
The pin assignment of Ethernet PHY and HPS is listed in Table 4-1.
Figure 4-1 The connections between the TSoM module, 260 Pin edge connector and
RJ-45 connector
Table 4-1 The pin assignment of Ethernet PHY and HPS on the TSoM module
Signal Name
FPGA Pin No.
Description
I/O Standard
HPS_ENET_TX_EN
A12
GMII and MII transmit enable
3.3V
HPS_ENET_TX_DATA[0]
A16
MII transmit data[0]
3.3V
HPS_ENET_TX_DATA[1]
J14
MII transmit data[1]
3.3V
HPS_ENET_TX_DATA[2]
A15
MII transmit data[2]
3.3V
HPS_ENET_TX_DATA[3]
D17
MII transmit data[3]
3.3V
HPS_ENET_RX_DV
J13
GMII and MII receive data valid
3.3V
HPS_ENET_RX_DATA[0]
A14
GMII and MII receive data[0]
3.3V
HPS_ENET_RX_DATA[1]
A11
GMII and MII receive data[1]
3.3V
HPS_ENET_RX_DATA[2]
C15
GMII and MII receive data[2]
3.3V
HPS_ENET_RX_DATA[3]
A9
GMII and MII receive data[3]
3.3V
HPS_ENET_RX_CLK
J12
GMII and MII receive clock
3.3V
HPS_ENET_MDIO
E16
Management Data
3.3V
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HPS_ENET_MDC
A13
Management Data Clock
Reference
3.3V
HPS_ENET_INT_N
B14
Interrupt Open Drain Output
3.3V
HPS_ENET_GTX_CLK
J15
GMII Transmit Clock
3.3V
There are two LEDs, green LED (LEDG) and yellow LED (LEDY), which represent the status of
Ethernet PHY (KSZ9031RN). The LED control signals are connected to the LEDs on the RJ-45
connector. The state and definition of LEDG and LEDY are listed in Table 4-2. For instance, the
connection from board to Gigabit Ethernet is established once the LEDG lights on.
Table 4-2 State and Definition of LED Mode Pins
LED (State)
LED (Definition)
Link /Activity
LEDG
LEDY
LEDG
LEDY
H
H
OFF
OFF
Link off
L
H
ON
OFF
1000 Link / No Activity
Toggle
H
Blinking
OFF
1000 Link / Activity (RX, TX)
H
L
OFF
ON
100 Link / No Activity
H
Toggle
OFF
Blinking
100 Link / Activity (RX, TX)
L
L
ON
ON
10 Link/ No Activity
Toggle
Toggle
Blinking
Blinking
Link / Activity (RX, TX)
4.2
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The board has an USB interfaces (using the SMSC USB3300 controller), which is provided by
TsoM Based Board. A SMSC USB3300 device in a 32-pin QFN package device is used to interface
to a single Type AB Micro-USB connector. This device supports UTMI+ Low Pin Interface (ULPI)
to communicate to USB 2.0 controller in HPS. As defined by OTG mode, the PHY can operate in
Host or Device modes. When operating in Host mode, the interface will supply the power to the
device through the Micro-USB interface. Figure 4-2 shows the connections between the TSoM
module, 260 Pin edge connector and RJ-45 connector. Table 4-3 lists the pin assignment of USB
OTG PHY to HPS.
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Terasic TSOM User manual

Brand
Terasic
Model
TSOM
Type
User manual
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