User's Guide
SCAU040–March 2010
Quad Sine-Wave Clock Buffer Evaluation Board
Contents
1 General Description ......................................................................................................... 2
1.1 Features ............................................................................................................. 2
2 Signal Path and Control Circuitry ......................................................................................... 2
3 Getting Started .............................................................................................................. 3
4 Power-Supply Connections ................................................................................................ 3
5 Output Clock ................................................................................................................. 3
6 Enabling/Disabling Outputs ................................................................................................ 3
7 Bill of Materials .............................................................................................................. 4
8 Schematic .................................................................................................................... 6
List of Figures
1 CDC3S04 Evaluation Board............................................................................................... 2
2 Schematic – (1 of 3)........................................................................................................ 6
3 Schematic – (2 of 3)........................................................................................................ 7
4 Schematic – (3 of 3)........................................................................................................ 8
List of Tables
1 Clock Source ................................................................................................................ 3
2 Supply source ............................................................................................................... 3
3 Outputs on the CDC3S04EVM............................................................................................ 3
4 Jumpers to Control the CDC3S04........................................................................................ 3
5 Bill of Materials.............................................................................................................. 4
I2C is a trademark of NXP B.V Corporation.
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General Description
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Figure 1. CDC3S04 Evaluation Board
1 General Description
The CDC3S04 is a four-channel low-power sine-wave clock buffer. It can be used to buffer a single master
clock to multiple peripherals. The four sine-wave outputs (CLK1–CLK4) are designed for minimal
channel-to-channel skew and ultralow additive output jitter. Each output has its own clock request input
which enables the dedicated clock output. These clock requests are active-high (can also be changed to
be active-low via I2C™), and an output signal is generated that can be sent back to the master clock to
request the clock (MCLK_REQ). MCKL_REQ is an open-source output and supports the wired-OR
function (default mode). It needs an external pulldown resistor. MCKL_REQ can be changed to wired-AND
or push-pull functionality via I2C.
This evaluation module (EVM) is designed to demonstrate the electrical performance of the
CDC3S04.Throughout this document, the acronym EVM and the phrases evaluation module and
evaluation board are synonymous with the CDC3S04 EVM. Figure 1 illustrates the CDC3S04 EVM.
For optimum performance, the board is equipped with 50Ω SMA connectors and well controlled 50Ω
impedance microstrip transmission lines.
1.1 Features
• Easy-to-use evaluation board to fan out low phase noise
• Easy device setup
• Control pins configurable though jumpers
• Board powered using USB or external supply
2 Signal Path and Control Circuitry
The CDC3S04 EVM has a TCXO soldered. If the customer wants to try out a different source then the
EVM allows routing the external signal to the CDC3S04. Resistors must be solder or desolder. See
Table 1 for each configuration.
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Getting Started
Table 1. Clock Source
Component TCXO on board External input
R80 Not mounted Not mounted
R74 Not mounted Not mounted
R98 0R0 Not mounted
R97 Not mounted 0R0
C8 15 pF 15 pF
3 Getting Started
The CDC3S04EVM has self-explanatory labeling and uses similar naming conventions as the CDC3S04
product data sheet (SCAS883). In this user’s guide, all words in boldface and italic print reflect the
actual labeling on the EVM.
4 Power-Supply Connections
The CDC3S04EVM has three pins that require external supply. Those pins are VDD_ANA, VDD_DIG and
VBAT. These supplies can come from the USB or using an external power supply. See Table 2 for further
information.
Table 2. Supply source
USB External Power Supply
R113 = 0R0 J50 OFF
R112 = Not mounted J51 OFF
J50 ON P3 = VDD_ANA
J51 ON P1 = VDD_DIG
Also the CDC3S04 has an LDO build in that generates the supply for the TCXO. This voltage can be
generated using the TPS71219 on board or the P2 connector.
5 Output Clock
The outputs of the CDC3S04 are available on any of the SMA connectors
Table 3. Outputs on the CDC3S04EVM
SMA Output
J17 CLK1
J68 CLK2
J21 CLK3
J20 CLK4
6 Enabling/Disabling Outputs
The CDC3S04EVM has several jumpers that can control the output enable of the CDC3S04.
Table 4. Jumpers to Control the CDC3S04
Jumper Function
J66 REQ1
J67 REQ2
J68 REQ3
J69 REQ4
J74 RESET
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Bill of Materials
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7 Bill of Materials
Table 5. Bill of Materials
QTY Value Designator PKG/CASE Manufacturer Lot Number
10 0.01uF C8, C12, C13, C33, C35, 0402 Venkel C0402X7R500-103KNE
C53, C58, C63, C67, C71
15 0.1uF C4, C5, C6, C16, C34, C36, 0402 Venkel C0402X7R160-104KNE
C49, C54, C64, C68, C72,
C55, C73, C75, C76
2 0.22uF C3, C74 0402 Venkel C0402X5R6R3-224KNE
1 0.47uF C7 0402 Murata Electronics North Am GRM155R61A474KE15D
5 1.0uF C51, C62, C66, C70, C48 0402 Murata Electronics North Am GRM155R61A105KE15D
5 10pF C1, C2, C43, C46, C47 0402 Venkel C0402COG500-100JNE
3 15pF C31, C32, C61 0402 Venkel C0402COG500-150JNE
2 2.2ìF C59, C60 0402 Murata Electronics North Am GRM155R60J225ME15D
1 10000pF C14 0603 Tdk Corporation C1608X7R1H103K
1 10ìF C77 0603 Panasonic ECJ-1VB0J106M
1 0.1ìF C57 0805 Kemet C0805C104J5RACTU
10 4.7ìF C41, C42, C44, C50, C52, 0805 Venkel C0805X5R250-475KNE
C56, C65, C69, C78, C79
2 10ìF C11, C15 3216-18 (EIA) Kemet B45196H3106K109
1 100K R73 7.04 x 6.71 x 4.8 Bourns Inc. 3361P-1-104GLF
7 0R0 R98, R106, R108, R112, 0402 Panasonic - Ecg ERJ-2GE0R00X
R113, R114, R115
2 1.00K R124, R125 0402 Venkel CR0402-16W-1001FT
1 1.00M R7 0402 Venkel CR0402-16W-1004FT
1 1.40K R3 0402 Panasonic - Ecg ERJ-2RKF1401X
3 10 R70, R75, R77 0402 Venkel CR0402-16W-10R0FT
12 10.0K R79, R94, R95, R99, R100, 0402 Rohm MCR01MZPF1002
R101, R102, R103, R104,
R109, R116, R123
1 100K R8 0402 Yageo America RC0402FR-07100KL
7 22.1 R107, R117, R118, R119, 0402 Panasonic - Ecg ERJ-2RKF22R1X
R120, R121, R122
1 3.32K R78 0402 Panasonic - Ecg ERJ-2RKF3321X
1 30.1K R111 0402 Venkel CR0402-16W-3012FT
1 31.6K R110 0402 Panasonic - Ecg ERJ-2RKF3162X
2 33.2 R1, R2 0402 Venkel CR0402-16W-33R2FT
1 33.2K R105 0402 Panasonic - Ecg ERJ-2RKF3322X
1 332 R76 0402 Vishay/Dale CRCW0402332RFKED
1 47.5K R9 0402 Venkel CR0402-16W-4752FT
1 5.1K R96 0402 Venkel CR0402-16W-5101FT
2 5.62K R5, R6 0402 Venkel CR0402-16W-5621FT
1 USB - Mini AB type USB1 SMT Jae Electronics DX3R005HN2E700
1 38.4MHz X1 4-SMT KDS 1XXD38400CAA
1 TPD2E001DZDR U7 4-SOP Texas Instruments TPD2E001DZDR
1 LLSD103A-7 D1 Mini MELF Diodes Inc LLSD103A-7
5 50 L6, L7, L8, L9, L10 1206 Murata Electronics North Am BLM31PG500SN1L
1 TPS71219DRCT U5 10-SON Texas Instruments TPS71219DRCT
1 CDC3S04YFFR U4 20-DSBGA Texas Instruments CDC3S04YFFR
3 LED - Green Clear D3, D4, D8 1206 Lite-On LTST-C150KGKT
1 LED - Red Clear D5 1206 (3216) Cml Innovative Technologies CMD15-21VRC/TR8
2 PTS635SL25SMTR LFS SW2, SW3 6mm x 3.50mm C&K Components PTS635SL25SMTR LFS
5 142-0701-801 J17, J18, J19, J20, J21 RF SMA EDGE Emerson Network Power Co 142-0701-801
2 Test Loop - Black J72, J73 0.1" Components Corporation TP-105-40-00
6 1 X 2 J7, J11, J12, J50, J51, J52 0.1" HTSW-150-08-G-S K10000012278
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Bill of Materials
Table 5. Bill of Materials (continued)
5 1 X 3 J66, J67, J68, J69, J74 0.1" HTSW-150-08-G-S K10000012278
4 Banana Plug - Metal P1, P2, P3, P4 4mm Emerson Network Power Co 108-0740-001
5 4-40/0.25"- Screws MH1, MH2, MH3, MH4, Building Fasteners PMSSS 440 0025 PH
MH5
5 0.75" MH1, MH2, MH3, MH4,
MH5
14 DNI C9, C10, R26, R27, R28,
R29, R30, R31, R32, R33,
C45, R74, R80, R97
2 DNI J70, J71
1 DNI U3
1 DNI Y1
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MCLK_IN_2
CLK1
CLK2
CLK3
MCLK_IN
CLK1_1
CLK2_1
CLK4_1
CLK3_1
CLK4
MCLK_IN_1
V_LDO
1.8V_Vdd_ANA
1.8V_Vdd_DIG
1.8V_Vdd_DIG
1.8V_Vdd_DIG
1.8V_Vdd_ANA
Adj_V
V_LDO
1.8V_Vdd_ANA
1.8V_Vdd_ANA
1.8V_Vdd_ANA
1.8V_Vdd_ANA
1.8V_Vdd_DIG
1.8V_Vdd_DIG
1.8V_Vdd_DIG
1.8V_Vdd_DIG
1.8V_Vdd_DIG
1.8V_Vdd_DIG
1.8V_Vdd_ANA
REQ1
REQ2
REQ3
REQ4
MCLK_REQ
RESET
REQ1
REQ2
REQ3
REQ4
SCLH
SDAH
RESET
MCLK_REQ_P
MCLK_REQ_P
The outputs of the CDC4S04 need to have the minimum
amount of capacitance to GND and VDD.
R29
R
DNP
R29
R
DNP
R101
10k
R101
10k
C73
100n
C73
100n
J18
SMA-EDGE
J18
SMA-EDGE
2
3
4
5
1
C34
100nF
C34
100nF
J73
HEADER1
J73
HEADER1
1
C8
15PF
C8
15PF
C33
10nF
C33
10nF
R99
10k
R99
10k
R98
0R
R98
0R
1
2
MH2
MHOLE1
MH2
MHOLE1
1
1
R103
10k
R103
10k
MH5
MHOLE1
MH5
MHOLE1
1
1
J21
SMA-EDGE
J21
SMA-EDGE
2
3
4
5
1
MH4
MHOLE1
MH4
MHOLE1
1
1
R80
500R
R80
500R
12
R97
0R
R97
0R
1
2
R26
R
DNP
R26
R
DNP
R30
R
DNP
R30
R
DNP
J19
SMA-EDGE
J19
SMA-EDGE
2
3
4
5
1
J20
SMA-EDGE
J20
SMA-EDGE
2
3
4
5
1
J17
SMA-EDGE
J17
SMA-EDGE
2
3
4
5
1
R124
1k
R124
1k
U4
CDC3S04
U4
CDC3S04
REQ2
A1
CLK2
A2
REQ1
A3
CLK1
A4
MCLK_IN
B1
/Reset
B2
VDD_ANA
B3
GND_ANA
B4
REQ4
C1
CLK4
C2
REQ3
C3
CLK3
C4
VDD_DIG
D1
GND_DIG
D2
MCLK_REQ
D3
ADR_A0
D4
VLDO
E1
VBAT
E2
SDAH
E3
SCLH
E4
R95
10k
R95
10k
R31
R
DNP
R31
R
DNP
R27
R
DNP
R27
R
DNP
J66
Jumper3
J66
Jumper3
1 3
2
R125
1k
R125
1k
X1
TCXO
X1
TCXO
V
4
GND
2
GND
1
OUT
3
R94
10k
R94
10k
R32
R
DNP
R32
R
DNP
C75
100n
C75
100n
MH1
MHOLE1
MH1
MHOLE1
1
1
MH3
MHOLE1
MH3
MHOLE1
1
1
C49
100nF
C49
100nF
R102
10k
R102
10k
R28
R
DNP
R28
R
DNP
J68
Jumper3
J68
Jumper3
1 3
2
C48
800nF
C48
800nF
C55
100n
C55
100n
R123
10k
R123
10k
R116
10k
R116
10k
R106
0R0
R106
0R0
R74
500R
R74
500R
12
C36
100nF
C36
100nF
R104
10k
R104
10k
R33
R
DNP
R33
R
DNP
J74
Jumper3
J74
Jumper3
1 3
2
R100
10k
R100
10k
R107
22R
R107
22R
C35
10nF
C35
10nF
R96
5k1
R96
5k1
12
J69
Jumper3
J69
Jumper3
1 3
2
C76
100n
C76
100n
J67
Jumper3
J67
Jumper3
1 3
2
Schematic
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8 Schematic
Figure 2. Schematic – (1 of 3)
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DVcc
AVcc
Test/SBWTCK
TDO
TDI
TMS
TCK
RST/NMI/SBWTDIO
VBUS_4v3
VBUS_4v3
1.8V_Vdd_MSP
1.8V_Vdd_MSP
1.8V_Vdd_MSP
1.8V_Vdd_MSP
1.8V_Vdd_MSP
VBUS_4v3
ADC_0
ADC_1
MCLK_REQ
REQ1
REQ4
REQ3
REQ2
MSP_EN_Adj
RESET
SDAH
SCLH
I2C
USBConnection
withESDprotection
measurementfor
Vdd_ANA&Vadj
DNP
C7
470n
C7
470n
C74 220nFC74 220nF
SW2
SWPUSHBUTTON
SW2
SWPUSHBUTTON
C45 15PFC45 15PF
D1
LL103A
D1
LL103A
R6
5.6K
R6
5.6K
C78
4u7
C78
4u7
R121 22RR121 22R
C9 15PFC9 15PF
C47
10PF
C47
10PF
C16
100nF
C16
100nF
C13
10nF
C13
10nF
R1 33R1 33
C4 100nFC4 100nF
R5
5.6K
R5
5.6K
R122 22RR122 22R
J7J7
1
2
R8
100K
R8
100K
R2 33R2 33
C10
2.2nFDNP
C10
2.2nFDNP
C1
10PF
C1
10PF
C5
100nF
C5
100nF
C2
10PF
C2
10PF
C12
10nF
C12
10nF
U3
MSP430F5529
U3
MSP430F5529
P5.0/VREF+/VeREF+
9
P5.1/VREF-/VeREF-
10
AVcc1
11
P5.4/XIN
12
P5.5/XOUT
13
AVss1
14
DVcc1
18
DVss1
19
Vcore
20
P2.7/UCB0STE/UCA0CLK
36
DVss2
49
DVcc2
50
P3.0/UCB0SIMO/UCB0SDA
37
P3.1/UCB0SOMI/UCB0SCL
38
P3.2/UCB0CLK/UCA0STE
39
P3.3/UCA0TXD/UCA0SIMO
40
P3.4/UCA0RXD/UCA0SOMI
41
P4.0/PM_UCB1STE/PM_UCA1CLK
45
P4.1/PM_UCB1SIMO/PM_UCB1SDA
46
P4.2/PM_UCB1SOMI/PM_UCB1SCL
47
P4.3/PM_UCB1CLK/PM_UCA1STE
48
P4.4/PM_UCA1TXD/PM_UCA1SIMO
51
P4.5/PM_UCA1RXD/PM_UCA1SOMI
52
P4.6/PM_NONE
53
P4.7/PM_NONE
54
P6.4/CB4/A4
1
P6.5/CB5/A5
2
P6.6/CB6/A6
3
P6.7/CB7/A7
4
P7.0/CB8/A12
5
P7.1/CB9/A13
6
P7.2/CB10/A14
7
P7.3/CB11/A15
8
VSSU
61
PU.0/DP
62
PUR
63
PU.1/DM
64
VBUS
65
VUSB
66
V18
67
AVss2
68
P5.2/XT2IN
69
P5.3/XT2OUT
70
TEST/SBWTCK
71
PJ.0/TDO
72
PJ.1/TDI/TCLK
73
PJ.2/TMS
74
PJ.3/TCK
75
!RST/NMI/SBWTDIO
76
P1.0/TA0CLK/ACLK
21
P1.1/TA0.0
22
P1.2/TA0.1
23
P1.3/TA0.2
24
P1.4/TA0.3
25
P1.5/TA0.4
26
P1.6/TA1CLK/CBOUT
27
P1.7/TA1.0
28
P2.6/RTCCLT/DMAE0
35
P8.0
15
P8.1
16
P8.2
17
P2.0/TA1.1
29
P2.1/TA1.2
30
P2.3/TA2.0
32
P2.4/TA2.1
33
P2.5/TA2.2
34
P2.2/TA2CLK/SMCLK
31
P3.5/TB0.5
42
P3.6/TB0.6
43
P3.7/TB0OUT/SVMOUT
44
P5.6/TB0.0
55
P5.7/TB0.1
56
P7.4/TB0.2
57
P7.5/TB0.3
58
P7.6/TB0.4
59
P7.7/TB0CLK/MCLK
60
P6.3/CB3/A3
80
P6.2/CB2/A2
79
P6.1/CB1/A1
78
P6.0/CB0/A0
77
R117 22RR117 22R
J12J12
1
2
R7
1.0M
R7
1.0M
R118 22RR118 22R
J70
JTAG
J70
JTAG
1
2
3
4
5
6
J11J11
1
2
R3 1k4R3 1k4
+
C15
10uF
+
C15
10uF
J72
HEADER1
J72
HEADER1
1
C79
4u7
C79
4u7
C3 220nFC3 220nF
C46
10PF
C46
10PF
SW3
SWPUSHB
SW3
SWPUSHB
R119 22RR119 22R
U7
TPD2E001DZD
U7
TPD2E001DZD
GND
1
IO1
2
IO2
3
Vcc
4
R108
0R0
R108
0R0
USB1
USB_MINI-B
USB1
USB_MINI-B
VBUS
1
D-
2
D+
3
IO
4
GND
5
Shield1
GND1
Shield2
GND2
Shield3
GND3
Shield4
GND4
C6
100nF
C6
100nF
+
C11
10uF
+
C11
10uF
C32
15pF
C32
15pF
C43
10PF
C43
10PF
Y1
4MHz
Y1
4MHz
R120 22RR120 22R
R105
33k
R105
33k
C31
15pF
C31
15pF
C14
10000PF
C14
10000PF
R9
47K
R9
47K
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Schematic
Figure 3. Schematic – (2 of 3)
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VCC_Adj_V
VCC_1.8V
VCC_1.8V
1.8V_Vdd_ANA
VCC_Adj_V
Adj_V
1.8V_Vdd_DIG
VCC_Battery
1.8V_Vdd_MSP
VCC_Battery
VBUS_4v3
ADC_0
ADC_1
MSP_EN_Adj
Note:
R73+R72=(Vout/1.25V-1)*R71
C61=((3*10^5)*((R73+R72)+R71))/((R73+R72)*R71)
C50
4.7uF
C50
4.7uF
C66
1uF
C66
1uF
C69
4.7uF
C69
4.7uF
C59
2.2uF
C59
2.2uF
C68
0.1uF
C68
0.1uF
R113
0R0
R113
0R0
C61
15pF
C61
15pF
P3
1.8V_ANA
P3
1.8V_ANA
R78
3.3k
R78
3.3k
C54
0.1uF
C54
0.1uF
L10
50Ohm@100MHz
L10
50Ohm@100MHz
1
2
U5
TPS71219
U5
TPS71219
IN
1
NC
2
OUT1
3
OUT2
4
GND
5
NR
6
FB2/NC
7
EN2
8
FB1/NC
9
EN1
10
T-PAD
11
C58
10nF
C58
10nF
R73
60k
R73
60k
P1
1.8V_DIG
P1
1.8V_DIG
L9
50Ohm@100MHz
L9
50Ohm@100MHz
1
2
J52
JUMPER
J52
JUMPER
1
2
R77
10
R77
10
12
L6
50Ohm@100MHz
L6
50Ohm@100MHz
1
2
L8
50Ohm@100MHz
L8
50Ohm@100MHz
1
2
C56
4.7uF
C56
4.7uF
C64
0.1uF
C64
0.1uF
D8
GREEN
D8
GREEN
1
2
R112
0R0
R112
0R0
L7
50Ohm@100MHz
L7
50Ohm@100MHz
1
2
J51
JUMPER
J51
JUMPER
12
R75
10
R75
10
12
R111
30k1
R111
30k1
R114
0R0
R114
0R0
R70
10
R70
10
12
D4
GREEN
D4
GREEN
1
2
R110
31k6
R110
31k6
J50
JUMPER
J50
JUMPER
12
C57
100nF
C57
100nF
C65
4.7uF
C65
4.7uF
R79
10k
R79
10k
D3
GREEN
D3
GREEN
1
2
C62
1uF
C62
1uF
R115
0R0
R115
0R0
C63
10nF
C63
10nF
C70
1uF
C70
1uF
J71
HEADER2
J71
HEADER2
1
2
C51
1uF
C51
1uF
C53
10nF
C53
10nF
C60
2.2uF
C60
2.2uF
C71
10nF
C71
10nF
C42
4.7uF
C42
4.7uF
P2
Adjustable_V
P2
Adjustable_V
C41
4.7uF
C41
4.7uF
C44
4.7uF
C44
4.7uF
P4
GND
P4
GND
R109
10k
R109
10k
C67
10nF
C67
10nF
C52
4.7uF
C52
4.7uF
D5
RED
D5
RED
12
C72
0.1uF
C72
0.1uF
R76
330
R76
330
12
C77
10u
C77
10u
Schematic
www.ti.com
Figure 4. Schematic – (3 of 3)
8
Quad Sine-Wave Clock Buffer Evaluation Board SCAU040–March 2010
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