Texas Instruments LMX2581EVM (Rev. C) User guide

Texas Instruments
Brand
Texas Instruments
Model
LMX2581EVM (Rev. C)
Category
Synthesizer
Type
User guide
LMX2581EVM
User's Guide
Literature Number: SNAU136C
November 2012–Revised November 2013
User's Guide
SNAU136C–November 2012–Revised November 2013
LMX2581EVM User's Guide
The Texas Instruments LMX2581EVM evaluation module (EVM) helps designers evaluate the operation
and performance of the LMX2581 Wideband Frequency Synthesizer. The EVM contains one Frequency
Synthesizer.
Converter: U1
IC: LMX2581
Package: LQA32A
Topic ........................................................................................................................... Page
1 Setup ................................................................................................................. 3
2 Using the EVM Software ...................................................................................... 5
3 Board Construction ............................................................................................. 9
4 PCB Layers ...................................................................................................... 15
5 Measured Performance Data ............................................................................... 20
6 Bill of Materials ................................................................................................. 39
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Setup
1 Setup
1.1 Input and Output Connector Description
Figure 1. Evaluation Board Setup
Table 1. Inputs and Outputs
Output Name(s) Input/Output Required? Function
These are two differential outputs. Connect any of the four
outputs to a spectrum analyzer or phase noise analyzer. It is
RFoutA+/RFoutA- recommended to put a 50 ohm terminator for the unused side of
Output Required
RFoutB+/RFoutB the differential output. Failure to do so will degrade
performance, especially output power and harmonics. The
Agilent E5052A was used for these instructions.
Connect to a 3.3 V Power Supply. Ensure the current limit is set
V CC Input Required
above 300 mA.
V CC Aux Input Optional This gives the option to supply power to an external VCO.
Programming
Input Required Connect the board to a PC using the provided cable.
Interface
The on-board 100 MHz XO has been enabled. To disable the
OSCin Input Optional XO and utilize the OSCin port move R13 to R12 and disconnect
R4 (removing power from the XO).
1.2 Installing the EVM Software
Go to http://www.ti.com/tool/codeloader and download and run the most current software.
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Noise before burning in.
Noise after burning in XO.
Setup
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1.3 Loop Filter Values and Configuration Information
Table 2. Loop Filter values and Configuration
Category Parameter Value
OSCin Frequency (MHz) 100 MHz
Phase Detector Frequency (MHz) 20 MHz
Configuration
VCO Frequency 1850 to 3760 MHz
Charge Pump Gain 2400 µA
VCO Core 1 15 to 25 MHz/V
VCO Core 2 18 to 32 MHz/V
VCO Gain
VCO Core 3 23 to 40 MHz/V
VCO Core 4 26 to 46 MHz/V
C1_LF 1.8 nF
C2_LF 56 nF
C3_LF Open
Loop Filter Components C4_LF 3.3 nF
R2_LF 390 Ω
R3_LF 270 Ω
R4_LF 0
Loop Bandwidth 28.7 kHz
Loop Filter Characteristics
Phase Margin 49.7°
Note that C4_LF is placed and C3_LF is left off because C4_LF is closer to the Vtune input. It is
recommended that the capacitor next to the VCO be at least 3.3 nF for optimal VCO phase noise. If this
constraint is violated, then there can be some degradation in the VCO phase noise in the 200kHz to 1
MHz region, depending on how much smaller than 3.3 nF this capacitor is.
1.4 Burning in the Crystal Oscillator
To get the best stability and phase noise from this XO, it is recommended to let the board run for several
in order burn in the crystal oscillator.
Figure 2. Impact of Burning in the XO
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Using the EVM Software
2 Using the EVM Software
2.1 Main Setup and Default Mode
NOTE: To restore the device to its default settings at any time, load the default mode from the “Modes”
menu.
Figure 3. Loading Default Mode for the Main Configuration Screen
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Although the GUI shows the
outputs being divided, the output
frequency will be the VCO
frequency unless the OUTx_MUX
bits on the Bits/Pins page are set
Using the EVM Software
www.ti.com
2.2 Loading the Device
To load the settings for the first time, you can either load this from the main menu as shown above or
press <CTRL>+L. When the frequency or programmable bit settings are changed, CodeLoader will
change the register associated with that programmable bit or change, but not all the registers.
Figure 4. Loading the device
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Using the EVM Software
2.3 Port Setup
On the Port Setup tab, the user may select the type of communication port (USB or Parallel) that will be
used to program the device on the evaluation board. If parallel port is selected, the user should ensure
that the correct port address is entered. CodeLoader does NOT auto detect the correct settings for this.
Also note that the BUFEN pin does not work with the USB2ANY board because pin location 5 is reserved
for other purposes. Be aware that the board has been revised and the port setup has changed.
Figure 5.
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The VCO Divider will be
ignored unless this is changed
to “Channel Divider”
If used with the USB2ANY
board, the BUFEN pin will not
work due to address conflict.
BUFEN_DIS chooses to ignore
this pin and always power up
buffer.
Right mouse click on any bit to
get a description of its function.
Using the EVM Software
www.ti.com
2.4 Bits/Pins Settings
To view the function of any bit on the CodeLoader configuration tabs, place the cursor over the desired bit
register label and click the right mouse button on it for a description.
Figure 6. Bits/Pins Settings
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Top Layer
Prepreg (16mil)
GND
Core (22mil)
Power
Prepreg (16mil)
Bottom Layer
Total Height (60.8mil)
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Board Construction
3 Board Construction
3.1 Board Layer Stack Up
The board is made on FR4 for the Prepreg and Core Layers. The top layer is 1 oz copper.
Figure 7. Board Layer Stack Up
FR4 material was chosen because of convenience, availability, and cost. If one was to use Rogers 4003
on the top Prepreg layer, the output power improves about 1 dB. Otherwise, the performance is very
similar.
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1
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B B
A A
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LMX2581
9/13/2013
SV601009A.SchDoc
Sheet Title:
Size:
Mod. Date:
File:
Sheet: of
B
http://www.ti.com
Contact:
http://www.ti.com
LMX2581EVMProject Title:
Designed for:Public Release
Assembly Variant: 001
© Texas Instruments 2013
Drawn By:
Engineer:
Not shown in title block
Dean Banerjee
Texas Instruments and/or its licensors do not warrant the accuracy or completeness of this specification or any information contained therein. Texas Instruments and/or its licensors do not
warrant that this design will meet the specifications, will be suitable for your application or fit for any particular purpose, or will operate in an implementation. Texas Instruments and/or its
licensors do not warrant that the design is production worthy. You should completely validate and test your design implementation to confirm the system functionality for your application.
Not in version controlSVN Rev:
SV601009Number: Rev: A
1
2
3
4
5
6
7
8
9
10
uWire
52601-S10-8LF
VccPlane
VccPlane
VccAux
VccPlane
100pF
C20
10k
R35
10k
R37
12k
R36
12k
R38
C105
DNP
DNP
0
R4_LF
0
R27
0
R22
18
R13
DNP
0.1µF
C10
0
R19
270
R3_LF
3300pF
C3_LF
DNP
DNP
R106
DNP
10k
R41
330
R31
0
R12
1µF
C1
0
R5
DNP
1
2
3
4
5
MUXout
142-0701-851
DNP
1
2
3
4
5
LD
142-0701-851
DNP
18
R109
DNP
18
R111
DNP
Vtune
100pF
C27
100pF
C26
1
2
3
4
5
RFoutB+
142-0701-851
1
2
3
4
5
RFoutB-
142-0701-851
VccPlane
100pF
C28
1
2
3
4
5
OSCin
142-0701-851
10
R6
VccPlane
1
2
3
4
5
Vcc
142-0701-851
Mechanical Information
- Standoffs are mounted in holes in the board
Power Information
- VccAux is an unregulated supply that can be used to run external components like the VCO and TCXO
- VccPlane can be regulated or direct from the SMA connector and is the main chip supply
External VCO
- An external VCO can be used to hit the most demanding phase noise specifications.
Vtune
Open
R101
DNP
Open
R102
DNP
Open
R104
DNP
C100
DNP
DNP
VccPlane
VccAux
C101
DNP
DNP
C102
DNP
DNP
C103
DNP
DNP
Vtune_TP
DNP
Loop Filter
0
R105
DNP
4
3
2
1
5
V+
V-
U101
LM6211MF
DNP
68
R110
DNP
330
R33
DNP
0
R30
390
R2pLF
DNP
10µF
C13
MUXout_TP
DNP
LD_TP
DNP
12k
R40
100pF
C18
100pF
C109
DNP
12k
R44
DNP
VccPlane
MUXout_uWire
18nH
L1
18nH
L2
Open
R100
DNP
390
R2_LF
0.056µF
C2_LF
1800pF
C1_LF
C104
DNP
DNP
Y1 is for a XO, but has
accomodations also for
VCXOs as well.
IN
4
ADJ
6
GND
3
NC
7
SD
8
DAP
9
OUT
5
BYP
1
NC
2
U2
LP3878SD-ADJ
DNP
51k
R8
DNP
0.01µF
C7
DNP
2.00k
R10
DNP
866
R9
DNP
4.7µF
C3
DNP
1µF
C5
2200pF
C4
DNP
10µF
C6
VccAux
1
2
3
4
5
VccAux
142-0701-851
DNP
0
R7
DNP
VccPlane
FLout_TP
DNP
1
2
Vcc_TB
1592820000
1.0k
R3
DNP
1.00k
R4
DNP
0.1µF
C2
DNP
VccAux
0
R2
DNP
Open
R1
DNP
VccPlane
0
R11
DNP
0
R34
DNP
LOGO
PCB
Texas Instruments
LOGO
PCB
ESD Susceptible
100pF
C17
0
R28
GND_OSC
GND_OSC
GND_OSC
GND_OSC
GND_OSC
GND_OSC
GND_OSC
2.2µF
C15
CLK
CLK
DATA
DATA
LE
LE
CE
LD_uWire
MUXout_uWire
0
R45
DNP
10k
R46
0
R39
CE
0
R112
DNP
100pF
C107
DNP
Fin
0
R25
100pF
C19
120 ohm
L4
120 ohm
L3
3300pF
C4_LF
47
R14
18
R15
33
R16
Open
R103
DNP
0.1µF
C30
100pF
C31
10µF
C29
VccPlane
0.1µF
C33
100pF
C34
10µF
C32
VccPlane
1µF
C22
DNP
10k
R42
12k
R43
Green
D1
DNP
22µF
C14
SV601009
A
PCB Number:
PCB Rev:
VCC
4
E/D
1
GND
2
OUT
3
100MHz
Y1
CWX813-100.0M
S1
TCBS-6-01
S2
TCBS-6-01
S3
TCBS-6-01
S4
TCBS-6-01
S5
TCBS-6-01
BUFEN
1µF
C21
DNP
12k
R47
GND
CLK
1
DATA
2
LE
3
CE
4
FLout
5
VCCCP
6
CPout
7
GND
8
GND
9
VCCPL
10
Fin
11
RFoutA+
12
RFoutA-
13
RFoutB+
14
RFoutB-
15
VCCBUF
16
VCCVCO
17
GND
18
VbiasVCO
19
Vtune
20
GND
21
VrefVCO
22
VbiasCOMP
23
VregVCO
24
LD
25
BUFEN
26
GND
27
VCCDIG
28
OSCin
29
MUXout
30
GND
31
VCCFRAC
32
PAD
U1
LMX2581SQ/NOPB
0
R24
100pF
C108
DNP
51
R23
51
R26
100pF
C24
100pF
C23
1
2
3
4
5
RFoutA+
142-0701-851
VccPlane
1
2
3
4
5
RFoutA-
142-0701-851
100pF
C25
Green
D2
0
R32
DNP
LD_uWire
0
R21
0
R20
VccPlane
100pF
C9
0
R18
100pF
C8
0
R17
100pF
C110
DNP
0
R29
10µF
C11
22µF
C12
2.2µF
C16
VccPlane
VccPlane
BUFEN
GND
3
Vtune
2
GND
1
GND
7
GND
6
GND
5
GND
8
GND
4
GND
9
RFout
10
GND
11
GND
12
GND
13
Vcc
14
GND
15
GND
16
U100
DNP
VccAux
VccPlane
0
R107
DNP
0
R108
DNP
100pF
C106
DNP
Board Construction
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3.2 Schematic
Figure 8. LMX2581 Schematic
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LMX2581
OSCin
Out+
Out-
100 Ω
0.1 Fμ 0.1 Fμ
51 Ω
VccAux
18
R13
DNP
0.1µF
C10
0
R19
1µF
C1
0
R5
DNP
1
2
3
4
5
MUXout
142-0701-851
DNP
1
2
3
4
5
OSCin
142-0701-851
10
R6
VccPlane
330
R33
DNP
MUXout_TP
DNP
100pF
C109
DNP
MUXout_uWire
Y1 is for a XO, but has
accomodations also for
VCXOs as well.
0
R34
DNP
GND_OSC
GND_OSC
GND_OSC
GND_OSC
CLK
120 ohm
L3
47
R14
18
R15
33
R16
Green
D1
DNP
VCC
4
E/D
1
GND
2
OUT
3
100MHz
Y1
CWX813-100.0M
CLK
1
BUFEN
26
GND
27
VCCDIG
28
OSCin
29
MUXout
30
GND
31
VCCFRAC
32
0
R21
0
R20
VccPlane
100pF
C9
0
R18
100pF
C8
0
R17
100pF
C110
DNP
VccPlane
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Board Construction
3.3 Comments and Recommendations for Evaluation Board Schematic
OSCin Input
The OSCin input has components of a series 47 Ω, shunt 18 Ω, and series 33 Ω, followed by a DC blocker
capacitor. This divides down the CMOS output level of the XO and also makes the impedance as seen
from the OSCin pin looking out to be about 50 Ω.
The OSCin input can also be driven by the OSCin SMA. To do this, remove R6 and R14; change R13,
R15, and L3 to 0 Ω; and make R15 51 Ω. Note that if L3 is not changed and left as a ferrite bead, this can
create degraded performance when used with an external signal generator.
Figure 9. OSCin Input Diagram
Complementary OSCin Input Recommendation
When the OSCin trace is differential, the approach shown in Figure 10 can also be used to convert it for
the single-ended input of the LMX2581. This circuit makes impedance seen from the LMX2581 OSCin pin
looking out to be 50 Ω as well as the termination for the differential trace to be 100 Ω. Note that only one
side of the 100 Ω differential trace can be grounded or it will change the desired 100 Ω termination for the
differential trace.
Figure 10. Complementary OSCin Input Recommendation Diagram
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VccPlane
VccPlane
0
R27
Vtune
100pF
C18
100pF
C17
0
R28
2.2µF
C15
120 ohm
L4
3300pF
C4_LF
VCCBUF
VCCVCO
17
GND
18
VbiasVCO
19
Vtune
20
GND
21
VrefVCO
22
0
R29
2.2µF
C16
Board Construction
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External VCO and Fin Input
An external VCO can be placed on the back side of the board and be driven by either a passive or active
loop filter. The output of this can be observed on the RFout pins, or the RFoutA- connector can be flipped
and used to see the VCO output directly.
Figure 11. External VCO and Fin Input Diagram
Vtune Input
The highest order loop filter should be placed capacitor next to the Vtune input pin without vias for optimal
spurs and VCO phase noise. A value of at least 3.3 nF will ensure that this will not impact the VCO phase
noise. If it is smaller, the phase noise of the VCO in the 200k-1MHz range may be degraded based on
how small this capacitor is. Smaller values for this capacitor, such as 1.5 nF, are possible, depending on
the circumstances.
Figure 12. Vtune Input Diagram
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VccPlane
VccPlane
0
R27
Vtune
100pF
C18
100pF
C17
0
R28
2.2µF
C15
120 ohm
L4
3300pF
C4_LF
VCCBUF
VCCVCO
17
GND
18
VbiasVCO
19
Vtune
20
GND
21
VrefVCO
22
0
R29
2.2µF
C16
VccPlane
VccPlane
100pF
C20
0
R27
0
R22
Vtune
100pF
C18
FLout_TP
DNP
100pF
C17
0
R28
2.2µF
CE
0
R25
100pF
C19
120 ohm
L4
3300pF
C4_LF
GND
CE
4
FLout
5
VCCCP
6
CPout
7
GND
8
GND
9
VCCPL
10
Fin
11
RFoutA+
12
RFoutA-
13
RFoutB+
14
RFoutB-
15
VCCBUF
16
VCCVCO
17
GND
18
VbiasVCO
19
Vtune
20
GND
21
PAD
U1
LMX2581SQ/NOPB
0
R24
0
R29
2.2µF
C16
VccPlane
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Board Construction
Power Supply Bypassing
The bypassing of the power supply pins does not have a large impact on fractional spurs, although placing
the ferrite bead L4 on the VccBUF pin improves the spurs at the phase detector frequency offset. This
board accommodates the possibility to change this bypassing to either filter noise coming to the pin, or by
preventing noise going out from the pin to the ground plane, as in the case of the VccBUF pin.
Figure 13. Power Supply Bypassing Diagram
Pins 18,19,22,23, and 24
For the best performance, it is best to have a solid ground connection between the grounds of these pins.
Larger value, higher quality capacitors are good for pins 23 and 24
Figure 14. Pins 18,19,22,23, and 24 Diagram
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VccPlane
VccPlane
0
R27
100pF
C27
100pF
C26
1
2
3
4
5
RFoutB+
142-0701-851
1
2
3
4
5
RFoutB-
142-0701-851
VccPlane
100pF
C28
100pF
C18
18nH
L1
18nH
L2
100pF
C17
0
R28
0
R25
100pF
C19
120 ohm
L4
GND
GND
8
GND
9
VCCPL
10
Fin
11
RFoutA+
12
RFoutA-
13
RFoutB+
14
RFoutB-
15
VCCBUF
16
VCCVCO
17
PAD
U1
LMX2581SQ/NOPB
0
R24
100pF
C108
DNP
51
R23
51
R26
100pF
C24
100pF
C23
1
2
3
4
5
RFoutA+
142-0701-851
VccPlane
1
2
3
4
5
RFoutA-
142-0701-851
100pF
C25
0
R29
VccPlane
Board Construction
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Outputs
The outputs can have either an inductor or resistor pull-up. The board has both values. The placement of
this pull-up component close to the chip is critical for output power. For this board, the routing of both
outputs compromised the output power a little because it forced this component a little farther away and
also it was done on FR4. If a single output was routed on a dielectric like Rogers4003, the output power
could have been slightly higher.
Figure 15. Outputs Diagram
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PCB Layers
4 PCB Layers
Figure 16 shows the assembly diagram that indicates where the components are placed.
Figure 16. Top Assembly Layer
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PCB Layers
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In the Top Layer, Figure 17, note the solid polygon on the northeast side of the chip, which gives solid
grounding to the VregVCO, VbiasVCO, as well as the closed capacitor on the loop filter. This is
recommended for optimal performance. On the output traces, the placement of the pull-up component also
needs to be as close to the device as possible for optimal output power. For this layout, about 1 dB of
power was sacrificed in order to route both outputs, thereby forcing this pull-up component farther away.
Figure 17. Top Layer
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PCB Layers
On the Ground Layer, Figure 18, notice there is a main region and a second region that is cut out below
the OSCin source. There is a connection through component L3 on the top layer. This reduces coupling
from the OSCin signal to the outputs that can potentially spurs at +/- Foscin offset.
Figure 18. Ground Layer
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PCB Layers
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The power layer, Figure 19, is used to route the power signals. There is a cutout below the OSCin signal
to reduce any coupling the OSCin frequency from nearby vias to the power plane.
Figure 19. Power Layer
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LMX2581EVM User's Guide SNAU136C–November 2012–Revised November 2013
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Copyright © 2012–2013, Texas Instruments Incorporated
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PCB Layers
The Bottom Layer, Figure 20, is used to route less critical functions. There are several optional
components on the bottom layer, including the option to use an external VCO.
Figure 20. Bottom Layer
19
SNAU136C–November 2012–Revised November 2013 LMX2581EVM User's Guide
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Measured Performance Data
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5 Measured Performance Data
5.1 Phase Noise in Default Mode
Figure 21 shows the phase noise in default mode. This was taken with a clean input (Wenzel 100 MHz
Oscillator), which shows that the device can achieve -99 dBc/Hz for a 2.7 GHz carrier at 1 KHz offset.
The 10 kHz number could be improved for a wider bandwidth. See section Section 5.7 for some examples
with a wider bandwidth filter.
Figure 21. Phase Noise (Default Mode)
Plot 1 of 3
Figure 22 shows the phase noise in default mode. The difference for this one is that it uses the on-board
XO. Comparing to the plot above, we see that the XO , not the LMX2581, is the dominant source of phase
noise at 100 Hz and 1 kHz.
Figure 22. Phase Noise (Default Mode)
Plot 2 of 3
20
LMX2581EVM User's Guide SNAU136C–November 2012–Revised November 2013
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Texas Instruments LMX2581EVM (Rev. C) User guide

Texas Instruments
Brand
Texas Instruments
Model
LMX2581EVM (Rev. C)
Category
Synthesizer
Type
User guide
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