COLOUR TELEVISION
TRAINING MANUAL
I
FILE NO. c-?/Ps60-uo /
Chassis Series ACI-A
ACI-B
ACI-C
CIRCUIT DESCRIPTION
BLOCK DIAGRAM OF
/~S
TROUBLE SHOOTING
I
REFERENCE NO. T1520009
i
Table of Contents
1.
2.
3.
4.
5.
6.
7.
8.
1.
2.
3.
4.
5.
1.
2.
3.
4.
5.
6.
7.
8.
Part 1 Chassis Description
Chassis Summary
........................................................................
3
CPU
. ......................................................................................
&-18
2.1 A. DKeyldentification ...............................................................................................6
2.2 Option Switches ...................................................................................................7.9
2.3 Power On/ Standby ................................................................................................lO
2.4 Power Protection ...................................................................................................ll
2.5 Band Switching .....................................................................................................l2
2.6 Am ...............................................................................................................l3.l4
2-7 TV/AV switch Output ..............................................................................................l5
2.8 Analogue Controls Output ............................................................................... .....l5.l6
2-9 System Switch Output ........................................................................................l7.l8
2-10 H/Vpulse input ...................................................................................................l9
IF/Video/Chroma/Deflection
......................................................
20-21
3-1 lFstage ................................................................. ............................................2O
3-2 Mdeo/Chroma stage .............................................................................................2l
3-3 Deflection Stage
..................................................................................................2l
System Switches
....................................................................
22-23
4-1 Sound Carrier Trap ...............................................................................................22
4.2 SIFFiltering ........................................................................................................23
Audio Output
.............................................................................
24
Vertical Output
...........................................................................
25
Horizontal Output
.......................................................................
26
Power Consumption Saving Circuit
................................................
27
Part 2 Block Diagram of K%
LA7687 cl F/Video/Chroma/Deflection>
.............................................
28
LC89950 <1 H Delay line>
..............................................................
29
LA7642 <SECAM Decoder>
...........................................................
29
LA7837 cVertical Output>
.............................................................
30
LA4285, LA4287 cAudio Output>
....................................................30
Part 3 Trouble Shooting Chart
Common start point
....................................................................
32
Dead
....................................................................................
33-35
No picture/No sound
................................................................
36-37
Uo picture-sound OK
...................................................................
38
No sound-picture OK
...................................................................
39
No colour
..................................................................................
Ao
ncorrect colour phase
.................................................................
Al
Uo vertical deflection
...................................................................
A2
Uo on-screen display
...................................................................
A3
-2-
.
Training Manual AC 1 Chassis
Part 1 Chassis Description
1. Chassis Summary
The following figure shows a basic block diagram of the AC1 chassis. This chassis is con-
structed by the following ICS;
LC864508, IC801, for the CPU (system control circuit) for AC I -A chassis
LC864512, IC801, for the CPU (system control circuit) for AC1 -B chassis
LC864516, IC801, for the CPU (system control circuit) for AC1 -C chassis
LA7687, IC201, for the IF, video, chroma de-modulation and deflection circuit
L
LC89950, IC271, for the 1H delay line circuit
LA7642, IC280, for the SECAM decoder circuit
LA7837, IC501, for the vertical deflection output circuit
LA4287, ICOO1, for the audio output circuit, for AC1 -B chassis
LA4285, ICOO1, for the audio output circuit, for AC1 -A and AC1 -C chassis
ST24C02AB, etc., IC802, for the control memory IC
......
......
..52n-m
1-
%..s:=~=~~
I
SASSEX
1
AUDIOIN
ESTERNM AUDIOIN
.
.
t
—.
All
L
FOWR SUPWY
CIRCUIT
—
-3-
Training Manual AC 1Chassis
i
2 CPU (System Control)
The following figure shows a block diagram of the CPU peripheral circuit.
—.— .—-— -—. — -—-—
-—-— -- —-— -—-— ,
,,,,,
Ii
L
,,,,,
I
2
C/3
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o
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T
MlII
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.—-—.
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L._-—-—.—.—.—-—-_-—; L.—.—.
—-— .—. J
-4-
Training Manual ACl Chassis
The following table shows pin descriptions of the CPU for AC1-A, AC1-B and ACI-C,
L
L
Pin Description
Pin Description
—
1
Inhibit output & Option switch
27 Red signal output for OSD
(AC1 -A)
28 Green signal output for OSD
Bass expander switch output &
29 Blue signal output for OSD
Option switch (AC I -B, AC1 -C)
30 Blanking signal output for OSD
2 12Cbus SDA line 31
Not used
3 12Cbus SCL line
32 Not used (AC1 -A, AC1 -B)
4 AV/SECAM switch output
AV1/AV2 switch output (AC1 -C)
5 Option switch (Tuner type)
33 Not used (AC1 -A, AC1 -B)
6 Option switch (No. of positions)
Ignore input (AC1 -C)
(AC1 -A)
34 Not used (AC1 -A)
Option switch (Blue back on/off) System switch output-VIF.M (AC1 -B,
(AC1-B)
AC1 -C)
Option switch (No. of positions& AV 35 AFT defeat switch output
modes) (AC1 -C)
36 Band switch output 1-VHF Low
7 Power& option switch (RC status)
37 Band switch output 2-VHF High
8 Tuning voltage output
38 Band switch output 3-UHF
9 GND (Digital)
39 Volume control output
10 Oscillator input for CPU 40 TV/AV switch output(TV:Low)
11
Oscillator output for CPU
41 Power error detection input
12 +5 power supply (Digital)
42 Sync identification input(No sync: Hi)
13 AFT-S signal input
43 Colour killer input
14 Key scan input (DC) 2
44 RC signal input
15 Key scan input (DC) 1
45 SECAM killer input
16 Option switch (Colour system)
46 IF identification input
17 Reset pulse input
47 Not used (AC1 -A, AC1 -B)
18 Oscillator input for OSD
AV1 Start function input(ACl -C)
19 Oscillator output for OSD
48 Option switch (No.of positions)
20 Charge pump output
(AC1 -A)
21 +5 power supply (Analogue)
Not used (AC1-B)
22 GND (Analogue) Option switch (No of positions & AV
23 Data-Analogue bus line
modes) & AV2 Start function
24 Address-Analogue bus line
input(AC1-C)
25 Vertical pulse input
49 SIF system output-DK & option SW.
26 Horizontal pulse input
50 SIF system output-1 & option SW.
51 SIF system output-BG & option SW.
52 SIF system output-M & option SW.
“-s-
training Manual ACIChassis
2-1 A-D Key Identification Circuit
The key identification circuit used in this chassis uses a switched resistive ladder network in
a A-D conversion circuit to generate and send a voltage to the CPU when a key is pressed.
The CPU uses this voltage to determine which key was pressed. This resistive circuit elimi-
nates the need for encoder/decoder devices, simplifying design and adding to the reliability
of the TV.
The table shows the voltages input to CPU pin 14 and 15, when a given key is pressed.
CPU
15
14
L
3-
K1 5“ ~
+—
~:j
27k K2
&
27k
10k
&3
!W
10k
5.6k
&
KJ
5.6k
3.9k
~
K~
3.9k
2.2k
~
K~3
2.2k
2.7k K7
K~4
2.7k
0.27k
0.27k
lrwut voltaqe to pin 15
—
7+
Intro It vnltarie to nin 14
.----- --..-=- .- . ... . .
1
Ke
K1
K2
K3
K4
K5
K6
K7
OFF
● Range of voltage
0.5V-1.1 V
l.l V- 1.7V
1.7V - 2.3V
2.3V - 3.OV
3.OU- 3.6V
3.6V - 4.2V
more than 4.2V
Less than 0.5V
Function
Position Up
Postion Up
Position Down
Level Up
Level Down
Undefined
Undefined
No Key pressed
-t
Ke
K8
K9
KI O
K11
K12
K13
K14
OFF
* Range of voltage
0.5V-1.1 V
I.lv- 1.7V
1.7V - 2.3V
2.3V - 3.OV
3.OV- 3.6V
3.6V - 4.2V
more than 4.2V
Less than 0.5V
Function
-rvlAv
TVIAV
SIF System
Colour System
Undefined
Preset
Function
No Key pressed
4
.
“ When the supply voltage is 5.OV.
-6-
Training Manual AC 1 Chassis
L
.
L
2-2 Option switches
This chassis uses the option function switches to determine several different specifications
of the TV set.
The CPU determines the specification of TV by detecting the voltage level on option switch-
es pins, pins, 1, 5, 6, 7, 16,49 to 52.
Following table shows the option functions and assigned pins of the CPU for each chassis.
Option functions
&lcl-A
AC1-B AC1-C
Inhibit
pin 1
nla nla
Bass expander
nla
pin 1 pin 1
Type of tuner
pin 5
pin 5 pin 5
No.s of positions
pins 6,48 nfa nla
No.s of positions & AV modes
nla
nla pins 6, 48
RC status
pin 7
nla nla
Blue back in
TV mode
nla
pin 6 nla
Colour system
pin 16
pin 16 pin16
SIF system
pins 49-52 pins 49-52 pins 49-52
* n/a = not available
Inhibit function (AC1-A chassis)
Buss
CPU
10
1
‘9
expander function ( AC1-B and AC1-C
IN.SW
Specification
off
w/o Inhibit function
on
w/ Inhibit function
chassis)
CPU
Rx
EX.SW
Specification
off w/o Bass expander function
1
‘9
on
w/ Bass expander function
Type of tuner
CPU
10
TU.SW
Specification
off Normal tuner
5
‘Y
on
CATV channel or hyper tuner
-7-
Training Manual AC I Chassis
i
Numbers of programme positions (AC1-A chassis)
9
CPU , 5“
k“
10k
10k
POS2 Sw
6
48
poa
Posl Sw
‘ off
on
off
on
POS2 Sw
Specification
off 60 programme positions
off
30 programme positions
on 100 programme positions
on 100 programme positions
Numbers of programme positions and AV modes (AC1-C chassis)
CPU
6
48
$%A
5“
10k
10k
POS2 Sw
poa
Remote control status (AC1-A chassis)
CPU
Rx
7
‘9
Blue Back function in TV mode (AC1-B chassis)
CPU
Posl Sw
off
on
off
on
on
off
off
Specification
60 programme positions
1 AV mode
100 programme positions
1 AV mode
100 programme positions
2 AV modes
100 programme positions
2 AV modes
RC SW. Specification
off
w/o remote control function
on
w/ remote control function
BL.SW
I
Specification
off
w/ Blue back function in TV mode
on
w/o Blue back function in TV mode
-8-
Training Manual AC1 Chassis
Colour system
CPU
J-1
5V
Rx
16
10k
SIF system
Pin16 Rx
Specification
more 4.53V
0.15K
Not used
3.9V-4.53V
1.8k
Not used
3.28V-3.9V 3.9k
Not used
2.66V-3.28V 6.8k
China, Indonesia(ACl-B/C)
2.03V-2.66V
12k Multi-system(AC l-B/C)
1.41V-2.03V 18k
3 system
0.78V-I .41V 33k
VMT system
O.15V-O.78V
10Ok PAL system
less O.15V
Open
PAL system
● When the supply voltage is 5.OV.
I
J7
11.sw
BG.SW I.sw
DK.SW
Specification
off
off
off
off Multi-system
off off on
off
Px
off off on
on
Indonesia 1
on
off
off
off 3 system
(ACI -A)
on
off on
off
East Europe
off
on off off
China 1
off on on
off
China 2
on
on
off
off China 3
(ACI-A)
off
in on on
Indonesia 2
on on on
on
No system
(AC1 -A)
-9-
Training Manual AC I Chassis
ii
2-3 Power/ stand-by circuit
O Power On/stand-by
The power on/stand-by signal is output from pin 7 of the CPU.
When the stand-by mode is selected the voltage of pin 7 changes from Hi(5V) to Low(OV)
to turn off Q682. Q682 turning off causes Q683 and Q684 to turn off. +24V supply for ver-
tical and horizontal output circuit, +7.8V supply for lF/Video/Chroma circuit and +12V for
tuner circuit are all cut off, resulting in the TV set going into the stand-by mode.
When the TV is switched back into the power on mode, Q683 and Q684 are turned on
and the relevant voltages are supplied back to each circuit.
,-.,-.,-.,-. .. . ..
Q683
● mmmmmmm. mmm mm.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
:
supply :
.
:
.
.
.
.
.
.
.
.
...................................
.
.
.
.
.
.
.
.
R681
15k
7
AAA
7
5v --------
Power On
t
““sEd’by-””-”’”o’ ~
Q682
CPU
-1o-
Traming Manual AC I Chassis
ii
2-4 Protection circuit
L
This chassis employs two kinds of protection circuit, one controlled by software through the
CPU and the other by hardware.
L
Protection circuit (software)
The protection circuit is provided to disable the operation of the TV set in case of a circuit
malfunction.
When an abnormality occurs during TV reception it causes pin 41 of the CPU to go con-
tinually Low (less than 0.8V) for about one second. The CPU detects that this has
occurred and outputs the signal to cut off Q683 and Q684.
Protection circuit (hardware)
When a power failure is detected by diodes D643, D644 and D645, this protection circuit
operates causing the power oscillation to stop.
If one of the above diodes is turned on, the voltage of Q631 -emitter decreases, and it
turns on completely. Photo-coupler D615 is driven by this and generates a current which
drives Q612 on. As a result, the operation of the power oscillation circuit is stopped.
Under normal circumstances these parts, D615, Q631, D641, R635, R636, VR631 are
operating as the error detection and regulation circuit for +130V power supply.
D445
Heater
D201 ,
5V
D492
I
180V
, -.,-.,-.! -. 0-..,
=a
i
.
.
■
✎
■
✎
✎
✎
✎
✎
✎
✎
✎
✎
✎
✎
✎
✎
✎
✎
✎
✎
✎
✎
✎
✎
✎
✎
✎
✎
✎
Power
supply
circuit
● mmmmmmmmmmmmmd
.
.
.
.
.
.
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.
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(2683
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! Vert.&Horiz.
;
L1
Jlllll18!o.slllllll.!lL
................
*@;
& output
i
- circuit
‘j
FBT j
................
Q684 . “--’ --’--’=-’-J ,
.. . . . . .
:,,,,,...,,,,,,.,,..,,,,,..%
., -.,-.,-., -- i---
................ I
+-@ ~
- lF/Video/Chroma R
I
.- . .- 1-------- ,.1
.m-. a-. .-. m-. *-. .
:
i
“m-, --}.-,.- ,.-,4
D655 ;
. [ 1/ I
.
.
.
.
.
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.
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.
.
.
.
+...
mmmm. mmm. m
CPU
Protect
41
Power 7
R681
...........
................,,. ...
as...,,,,
.
R635
VR631
.
.
.
.
Rf=$ :$\ :
Power
oscillation
.
.
.
.
■
h
ADfj41 E
)
circuit
:
.
P................*. . . . . . . . . . . ..
130V
Regulator
circuit
_ power
15k
iAA
operation ~ failuer
Training Manual AC 1Chassis
-11-
i
2-5 Band switching circuit
The band switching control signals are output from pins 36, 37 and 38 of the CPU and fed
to the base of Q103, Q104 and Q105, band switching transistors.
The one of these transistors then supplies the drive voltage(+l 2V) to the tuner according to
the output signal from the CPU as shown below table.
Antenna
I._
Tuner
VL
VH
u
Cllo3
●
12k
Q104
●
12k
Q105
●
R898
12k
Band Switching Logic
output
Pin36 Pin 37 Pin 38
Q103 Q104
Q105
Selected Band
LH
H on
off off
VHF-Low
HL
H off
on off
VHF-High
HHL
off
off
on
UHF
36 VL
37 VH
38 UHF
CPU
-12-
Tmining Manual AC1 Chassis
2-6 AFT
This chassis employs two kinds of the AFT circuit, it’s called the Digital AFT and the Trace
AFT.
The digital AFT operates as the hardware AFT in the tuner circuit. Every channel selection,
the CPU reads out the tuning data from the memory and then changes tuning voltage output
from pin 8 to obtain the best tuned picture.
The trace AFT is to prevent the drifting of receiving condition caused by the temperature
etc. The CPU monitors the AFT S-curve signal input to pin 13 and maintains the correct
tuned picture by controlling the output tuning voltage.
.
Digital An
(1)
‘w
(2)
(3)
(4)
The CPU outputs tuning voltage(Start value) which is subtracted with the step as table-1
from the stored tuning voltage data in the memory and waits for 240ms.
II* When the AFT voltage is less than 1.5V, go to step (4).
III* Other than the above, go to step (2).
Increase the tuning voltage along with table-2a until the AFT voltage reaches less than
1.5V. Go to next step.
Decrease the tuning voltage along with table-2b until the AFT voltage reaches more than
2.OV. Go to next step.
The CPU judges that the sync. signal is existing or not by detecting the voltage on pin
46,
If the CPU detects a low voltage on pin 46, go to step (2).
If the CPU detects a high(5V) voltage on pin 46, complete the digital AFT operation and
go to the Trace AFT stage.
Trace Am
After completing the digital AFT operation, the CPU switches to the trace AFT mode.
(1)
(2)
‘L
(3)
If the AFT v;ltage ii more than 3.OV and the IF ident. signal is detected, the CPU
increases the tuning voltage along with table-3.
If the AFT voltage is less than 2.OV and the IF ident. signal is detected, the CPU
decreases the tuning voltage along with table-3.
In the preset mode and fine tuning mode, this function does not operate.
‘“L
Tablel Substructed steps
Table-3 Tuning spesd of Trace AFT
~=
Table-2 Tuning apeed of digital AFT
(a) High spead (steps/10msec.)
~
(b) Mid spead (steps/10msec.)
~
-13-
Training Manual AC I Chassis
Tuning
CPU
IC201
Tuner
lF&VIDEO
Q184
IF IDENT IN
TU
‘ 8
46 w
2 IF IDENT
TUNING OUT
R858
150
R177
120k
R176
I
7 AFT
39k
J? %::
AFTIN 13
4
F
l\
RI 75
J? $:”
82k
Input Signal
Pin 13
AFT S-Curve
of IC801
Input
Pin 8
of IC801
Pin 46
of IC801
Tuning Voltage
3.5V
3.OV
-,:!
2.OV
!,,
A
IF Ident.
Signal Input
‘ Tuned point
Input Voltage Level of Pin 13
Judgement
LL(OV-1.5V)
Tuning Voltage Down
L (1.5V-2.OV)
Tuning Voltage
Down
M (2.O-3.OV)
Tuned Centre
H (3.OV-3.5V)
Tuning Voltage Up
HH(3.5V-5V)
Tuning Voltage Up
-14-
Training Manual AC 1 Chassis
2-7 TV/AV switching circuit
The TV/AV switching signal output from pin 40 of the CPU is supplied to pin 4 of ICOO1,
audio output, and pin 1 of IC201 to select the internal or external source. The SECAM
switching signal output from pin 4 is sent to pin 1 of IC201. The output of each mode and
system is shown in the table below.
40
TVIAV
CPU
AV/SECA;
L
To SECAM IC
pin12
I
Icool
I
AUDIO OUTPUT
R861
5.6k
-“4
5V
R803
5.6k
R815 R804
680
15k
d?
4 lNT./EXT. SW.
Q016
IC201
lV/VIDEO
“1
1 AVISECAM
RI 71
SIF IN
lk
TV I Av I
OUTPUT PAUNTSC SECAM
PAUNTSC SECAM
pin 4
Hz L Hz
H
Din
40 L L
H H
● Hz= High impedance
2-8 Analogue control circuit
The colour saturation, brightness, contrast, tint, and sharpness for picture controls and
selection of crystal control are controlled via the analogue bus lines connected from pins 23
and 24 of the CPU to pins 18 and 19 of IC201, LA7687. The CPU outputs the data and
L
address signals during a vertical retracing period, and the control address and data of crys-
tal are represented in 8 bits and data of picture controls are represented in 7 bits.
The timing charts and specifications of bus lines are described on next page.
The sound volume control is output from pin 39 as 7 bits PWM (Pulse Width Modulation)
signal. This signal is applied to the audio output IC as DC control voltage through the filter-
ing circuit
IC201
lF/VIDEO
CPU
23
DATA
\
I
19 Data
R219
220
24
ADDRESS
18 Address
39
R218
lk
Icool
AUDIO OUTPUT
VOLUME
Filtering
circuit
*
5 VOL
-15-
Traming Manual AC I Chassis
‘L
i
Output Value
(1) Address voltaae (8 bits= 255 steDs)
.,
“. ,,
Control Item Specification of
LA7687
1
Crystal O- O.17V
Brightness 0.77V - 1.OIV
Contrast
1.68V -1 .93V
Colour
2.59V - 2.83V
Sharpness 3.50V - 3.74V
Tint 4.40V - 5.00V
Reference output
voltage of CPU
O.oiv (02/255)
0.86V (44/255)
1.76V
(90/255)
2.67V (136/255)
3.57V (182/255)
4.51V (230/255)
(2) Data voltage
a) Crystal (8 bits= 255 steps)
Control Item Specification of
Reference output
LA7687 voltage of CPU
PAL4.43
I
O - 1.48V 0.04V (02/255)
PAL3.58
1.70V - 2.70V
NTSC3.58 2.90V - 3.90V
NTSC4.43 4.1 Ov - 5.00V
2.20V (1
12/255)
3.22V (164/255)
5.00V (255/255)
b) Picture control (7 bits=l 27 steps)
Control Item
Reference output voltage of
CPU
Minimum I
Maxmum
Brightness
Contrast
Colour
Sharpness
Tint
0.43V
(11/127)
2.48V (63/1 27)
Ov (0/1 27)
0.95V (24/1 27)
1.22V
(31/127)
2.91V (74/1 27)
4.96V (126/1 27)
4.96V (126/127)
3.43V (87/1 27)
3.7V (94/1 27)
Output timing chart
1 Field
V-Sync
.-
Address
Data
5V
//
//
—
I
-16-
Training Manual AC] Chassis
ii
2-9 System switch output
The outputs from pins 4,40and 340fthe CPUselect thecolour system and the outputs
from pins 49 to 52 the SIF system. These outputs drive the colour and SIF system switching
circuits. The operation of each switching circuit is shown in the table below.
Colour system switching output
Output pins
System
Xtal/lD
~oltage(V) 4 40 34
PAL
0- 1.0
HzLL
TV
SECAM
0- 1.0
LLL
NTSC4.43
4.0- 5.0
HzLL
NTSC
2.7- 3.6
HzLH
I I PAL !
0- 1.0
ll-fz I-1*
II
AV
SECAM 0- 1.0
HH*
NTSC4.43
4.0 -5.0 Hz H *
I
I
NTSC
I
2.7- 3.6
I
HzH*
“It dependsonreceivingTV system
HZ= High impedance
SIF system switching output
1.
Multi system
SIF system
r
Auto
5.5 MHZ
6.OMHZ
6.5MHz
4.5MHZ
Output pins
Display
52 51 50 49
*
HHH
S1
LHLL
S2
LLHL
S3
LLLH
S4
HLLL
S5
“ The output level of pin 52 in the AUTO mode is determined by
the followingcondition
~
AUTO BAN
50
L
TV
. AUTO B/W
H
PAL
50 or 60
L
SECAM
500r60
L
NTSC4.43
50 or 60
L
NTSC
50 or 60
H
AV
It maintains the conditionof TV mode.
2. PX system
6.5MHz
LLLH S3
4.5MHZ HLLL S4
‘
Same condition with Multi-system
3.
Indonesia a system
SIF system Output pins Display
52 51 50 49
Auto
*
HLL
S1
5.5MHZ
LHLL S2
4.5MHZ
HLLL S3
“ Same condition with Multi-system
-17-
Training Manual AC 1Chassis
i
L 3 system
SIF system Output pins
Display
52 51 50 49
Auto
LHH
H
S1
5.5MHZ
LHLL
S2
6.OMHZ
LLHL
S3
6.5 MHz
LLL H
S4
5. a) East Europe systam(ACl -A/B)
S1F system Output pins
Display
52 51 50 49
Auto
LHL
H
SI
5.5MHZ
LHL
L
S2
6.5MHz
LLL
H
S3
b) East Europe system(AC1-C)
S1F system
I
Output pins
I
Display
52 51 50 49
Auto
LHL
H
SI
16.5MHz ILLL HI.52 I
5.5 MHZ
I
LHL L
I
S3
I
6. No system
SIF system
Output pins
Display
52 51 50 49
----
LLLL
No Display
7. China a svstem
S1F system Output pins
Display
52 51 50 49
Auto
●
LHH
S1
6.5MHz
LLLH
S2
6.OMHZ
LLHL
S3
4.5MHZ
HLLL
S4
8. China b system
. SameconditionwithMultisystem
SIF system
I
Output pins
Display
52 51 50 49
Auto
●
LLH
S1
6.5MHz
LLLH
S2
4.5MHZ
I
HLLL
I
S3
I
‘ Same condition with Multi system
9.
Chinac system
SIF system
Output pins
Display
52 51 50 49
Auto
LLHH
SI
6.5MHz
LLLH
S2
6.OMHZ I I
H L w?
10. Indonesia b system
Colour system
Pin 34
Auto
*
PAL
L
No Display
NTSC4.43
L
NTSC H
-18-
Trainitig Manual AC) Chassis
2-10 Horiz./Vert. pulse input
‘.-
The vertical and horizontal pulses from the deflection circuits are input to pins 25 and 26 in
order to synchronise the On Screen Display.
The vertical pulse is supplied from pin 20 of IC201 through the buffer and inverter circuit
(Q845 and Q837).
The horizontal pulse is supplied from pin 4 of the flyback transformer through the inverter
circuit Q836.
If one of these pulses is not supplied to the CPU, the on-screen display cannot be dis-
played.
CPU
H-SYNC. 2f
V-SYNC. 2!
?
Ul_bv 5VR883
/
Horiz.
3.3k
JL--l’l
Hnriz
\
I
\
I
Vert.
u.
u
Vert
I
T471
FBT
IC201
lF/Video/Chroma
20 V-DRIVE
V-Dfive pulse to V-OUTPUT IC
Training Manual AC 1Chassis
-19-
3. lF/Video/Chroma/Deflection
The following figure shows a block diagram of the lF/Video/Chroma/Deflection IC <LA7687>
peripheral circuit.
3-1 IF stage
The IF signal output from the tuner is amplified by the pre-amplifier Q101, then sent to the
SAW(Sutface Acoustic Wave) filter Xl 61. The output signal of the SAW filter Xl 61, is input
to pins 47 and 48. The IF signal thus input to the IC is then amplified by the IF amplifier, and
is detected by the video detector with the VCO(Voltage Controlled Oscillation) circuit con-
sisted of Xl 71 9,725 MHz oscillator and peripheral resistors, and it is output as a composite
video signal at pin 8.
This composite video signal passes through the 6.0MHZ(l)/6.5MHz( D/K) and 4.5 MHz(M)
sound bandpass filtering circuit, and it is input into pin 1 of IC201. In the IC, this sound IF
signal passes through the SIF amplifier, FM detector and audio output circuit, and it is then
output from pin 51 as audio drive signal.
IC201
X161
lF/VIDEO/CHROMA/DEF.
IC271
TUNER Q101
SAW
lH DELAYLINE
IF PREAMP.
X171
9.725MH
J#o
1---
SIF CARRIER(4.516.016 .5MHZ
..............................
~i$:MHJ+
:.,.,
,..,,,,.,,.,.,,,.,.,,,.,.,r
J
:,,,,..,,.,,.,..,,.,,.,,.,,.,.
~Tr%qE~
!4.5/6.0/6.5fvll-tz!
x,,.,..,..,. ,.,,..,,,,,.,,,.
+$7-
VIDEO-OUT
I
EXT. VIDEO-IN
.
AUDIO-OUT
-
ANALOGUE BUS
\\
.
.
=-+=+-L
‘#
AUDIO
47
48
5
1
8
10
14
51
18
19
28
il
3f
37
3E
3~
33
:5
32
42
41
25
20
23
a
113
5ff
CRT
R-YIG-YIB-Y
\\\
A
>
-Y
Q261
X242
~ H-DRIVE
m
~ V-DRIVE
in
-20-
Training Manual ACI Chassis
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