Sanyo C21ZM45 Training manual

COLOUR TELEVISION

TRAINING MANUAL

FILE NO.

Chassis Series A7-A

Table of Contents

Part 1 Chassis Description .................................................................................

2-29

1.

Circuit Function Description

....................................................................................................

2-4

2. CPU ..........................................................................................................................................

5-21

2-1 A-DKey Identification .........................................................................................................................7

2-2 Option Switches ..................................................................................................................................8

2-3 System Switch Output .................................................................................................................l O.ll

2-4 Chroma ID ........................................................................................................................................l2

2-5 ldent ..................................................................................................................................................l2

2-6 Sync. ID

13

2-7 ,2C Bus ............................................................................................................................................13

.............................................................................................................................................

2-8 Band Switching .................................................................................................................................l4

2-9 Linear A~ ........................................................................................................................................l5

2-10 Digital AFT .................................................................................................................................l6.l7

2-11 Power& Proteti ..............................................................................................................................l8

2-12 Power On/Off (RCtransformerless model).....................................................................................l9

2-13 Protection (RC transformerless model) ..........................................................................................2O

2-14 Horiz.Nert. Pulse............................................................................................................................2l

3. System Switches

...................................................................................................................

22-27

3-1 Sound Carrier Trap ...........................................................................................................................24

3-2 SIF Filtering ......................................................................................................................................25

3-3 Chroma Crystal SelWtion .................................................................................................................26

3-4 SECAM Switch

.................................................................................................................................27

4. lF/Video/Chroma/Def

. ................................................................................................................

28

5. Audio ...........................................................................................................................................29

Part 2 Block Diagram of ICS

.............................................................................30-32

1.

TDA8361/8362 AF/Video/Chroma/Def lection>

........................................................................30

2. TDA4661/V2 <1H Delay>

............................................................................................................

31

3. TDA8395 cSECAM Decoder>

....................................................................................................

32

4. LA78321LA7833 <Vertical Output>

...........................................................................................

32

Part 3 Trouble Shooting Chart

.........................................................................34-46

1.

Dead

.......................................................................................................................................

35-37

Dead (RC transformerless model)

......................................................................................38-40

2. No picture/No sound

............................................................................................................

41-42

3. No picture-sound OK

.................................................................................................................

43

4. No sound-picture OK.................................................................................................................

44

5. No colour

...............................................................................................................................

45-46

L

REFERENCE NO. TI 520003

\

Part 1 Chassis Description

1. Circuit Function Description

The following figure shows a block diagram of the A7-A chassis.

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-2-

A7-A

1. POWER SUPPLY

The power supply circuit of the A7-A chassis

comprises a primary rectifier smoothing

circuit, an oscillation circuit, a control circuit

and an output rectifier circuit.

The AC input voltage is full-wave rectified by

the primary rectifier smoothing circuit, and an

unstable DC voltage is generated at both

terminals of the smoothing capacitor C507.

This voltage is supplied to the oscillation

circuit, which is composed of a blocking

oscillator circuit that switches the switching

transistor Q513 ON and OFF.

A square-wave oscillation is generated in the

input winding according to operation of the

control circuit. A square-wave with amplitude

dependent on the turns ratio of the input and

output windings is obtained in the output

winding. This is rectified in the output rectifier

circuit, and the desired DC voltage is

produced.

2. IF& DEFLECTION (TDA8361/8362)

The IF output signal from the tuner passes

through the SAW filter, and it is inputted into

pins 45 and 46 of IC101.

Within the IC, the IF signal passes through

the IF amplifier, video detection and video

amplifier circuits, and is outputted from pin 7

as a composite video signal.

This composite video signal passes through

the 5.5 MHz(B/G)/6.0MHz( l)/6.5MHz(D/K)/

4.5 MHz(M) sound bandpass filtering circuit,

and it is inputted into pin5 of IC101. In the

L

IC, this sound IF signal passes through the

SIF amplifier, FM detector, external audio

switch and audio output circuit, and it is then

outputted from pin 50 as audio drive signal.

The video signals applied to pins 13 or 15

are separated into vertical- and horizontal-

sync. signals respectively by the sync.

separator in the IC.

.

The horizontal oscillator requires no external

components and is fully integrated. This

oscillator is always running when the start-

pin 36 is supplied with 8V, and the horizontal

drive signal is outputted from pin 37. VR401

is used for horizontal centring adjustment.

The separated vertical sync. signal from the

sync. separation circuit passes through the

vertical-separation circuit, and is applied to

trigger divider circuit.

The horizontal oscillation pulse and vertical

sync. pulse are monitored by the trigger

divider circuit to select either the 50Hz or

60Hz system, and automatically adjust the

vertical amplitude.

The output signal from the trigger divider

triggers the vertical oscillator circuit whose

external timing components consist of R401,

C402 to pin 42, and the vertical ramp signal

is outputted from pin 43. VR451 is for

controlling the amount of AC feedback

applied to pin 41 for adjustment of the

vertical amplitude.

3. VIDEO CHROMA (TDA8361/8362)

The composite video signal output from the

pin 7 of IC101, passes through Q122, Q124,

and the sound traps X124, X125, X126,

Xl 27 to reject the sound carrier components,

is then supplied to pin 13. The external video

signal from SCART or other AV terminals is

supplied to pin 15.

The video signal input to pin 13 or pin 15 is

separated into luminance (Y) signal and

chroma signal in ICI 01. These pins are also

common to the H/V-sync. separation circuit

input already described.

The peaking of Y signal is adjusted by DC

voltage on pin 14.(’’SHARPNESS” control)

The chroma signal is divided into R-Y and B-

Y chroma signals, which are demodulated

and output from pin 30 (R-Y) and pin 31 (B-

Y). These chroma signals pass through the

1H delay line circuit (IC270), and are re-

inputted at pin 29 (R-Y) and pin 28 (B-Y).

These R-Y/B-Y signals pass through the

RGB matrix circuit and the RGB selector

circuit of IC1 01. The internal RGB signals

are generated in the RGB matrix circuit and

the RGB selector, consisting of linear

amplifiers, clamps and selects either the

internal RGB signals or the external RGB

signals input from pin 22 (R) , pin 23 (G), pin

24 (B). Selection is controlled by the voltage

-3-

A7-A

at the RGB switch control (pin 21) and mixed

RGB modes are possible since the RG13

switching is fast.

The RGB switch also functions as a fast

blanking pin by blanking the RGB output

stages; here internal and external RGB

signals are overruled.

The saturation of colour gain is controlled by

the DC voltage of pin 26. (“COLOUR”

control)

The contrast control voltage present at pin

25, controls the RGB signal gain, and the

brightness control voltage present at pin 17,

controls DC level of RGB signals.

The RGB signals are finally buffered before

being presented to the RGB output pins [pin

20 (R), pin 19 (G), pin 18 (B)].

4. AUDIO OUTPUT

The audio signal output from pin 50 of ICI 01

is inputted to pin 2 of IC171 and passes

through the pre-amplifier circuit and the drive

circuit into the audio amplifier. The audio

amplifier is the SEPP (Single-Ended Push

Pull) type and the output from pin 8 drives

the speaker directly.

5. VERTICAL OUTPUT

An LA7832 is used for the vertical output

circuit in this chassis. The vertical ramp

signal from pin 43 of ICI 01 is inputted to pin

4 of IC451. This ramp drives IC451, and

vertical scanning is performed. In the first

half of scanning a deflecting current is

outputted from pin 2 and passes through the

following path:

VCC(B4)+D451+ pin 3+ pin 2+ DY+

C461 + VR451 /R459.

An electric charge is then stored in C461. In

the last half of scanning the current path is:

C461 + DY+ pin 2+ pin 1+ VR451/R459 +

C461

In this way, an increasing sawtooth

waveform current flows directly to the DY to

perform electron beam deflection. During the

first half of the blanking period the vertical

ramp signal suddenly turns OFF. Since there

is no longer any current flowing into the DY,

the magnetic field collapses causing an ‘-

induced current to flow as follows:

DY+ pin 2+ pin 1+ VR451 /R459+ C461 +

DY

Once the magnetic field in DY has

dissipated, the current path becomes:

Vcc+ pin 6+ pin 7+ C452+ pin 3+ pin 2 +

DY+ C461 + VR451 /R459

and when the prescribed current value is

reached, the vertical drive ramp signal turns

ON. This completes one cycle.

6. HORIZONTAL OUTPUT

The horizontal oscillation signal is outputted _

from pin 37 of IC101 and used to switch the

drive transistor Q431. This switching signal

is current amplified by the drive transformer

T431 and drives the output transistor Q432.

When Q432 turns ON, an increasing current

flows directly to the DY through

C441/C442+ L441/R441 + DY+ Q432-C +

Q432-E

and the deflection occurs during the last half

of the scanning period. When Q432 turns

OFF, the magnetic field stored in the DY up

to that point causes a resonant current to

flow into the capacitors C435 and C436 and

charges them. The current stored in C435

and C436 then flows back to the DY causing <

an opposite magnetic field to be stored in the

DY. This field then collapses increasing a

current which switches the dumper diode in

Q432 ON. The resonance state is

completed, and an increasing current then

flows again directly to the DY through the

dumper diode.

By this means, the deflection in the first half

of the scanning period is performed. When

Q432 turns ON at the end of the first half of

the scanning period, the deflection during the

last half is begun, thus completing one cycle.

-4-

A7-A

w

2. CPU

The following figure shows a block diagram of the CPU peripheral circuit.

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-5-

The following table shows pin descriptions of the CPU.

Pin Description

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

Horizontal sync. signal input

Vertical sync. signal input

Colour control output

Brightness control output

Contrast control output

Sharpness control output

Tint control output

N/AV switch output 1(TV:Hi)

N/AV switch output 2(TV:Hi)

TV/AV switch output 3(TV:Hi)

---

IZC bus SCL line

12C bus SDA line

.-.

Ident signal input

RC signal input

AV1 start input(VCR Play: Lo)

AV2 start input(VCR Play: Lo)

AV1 Ignore signal input

50/60Hz switch output (60 Hz:Hi)

GND

Oscillator input for CPU

Oscillator output for CPU

GND

Pin Description

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

+5V power supply

Oscillator 2 for OSD

Oscillator 1 for OSD

Reset input

Detection power failure (Error: Lo)

Sync. ID signal input

AFT-S signal input

Option switch

Key scan input (DC)

Picture On output (On: Lo)

S-VHS output (S-VHS:Hi)

GND

BG/ I or DK switch output (BG:Lo)

UL’ switch output (L’:Hi)

Positive/Negative output (Nega.:Hi)

GND

16:9/4:3 switch output (16:9:Hi)

GND

Sound mute output (Mute on: Hi)

Power on/off output (P-On: Hi)

Blanking signal output for OSD

Open

OSD green signal output

OSD red signal output

A7-A

-6-

-

2-1 A-D Key Identification Circuit

The key identification circuit used in this chassis uses a switched resistive ladder network in a

A-D conversion circuit to generate and send a voltage to the CPU when a key is pressed.

The CPU uses this voltage to determine which key was pressed. This resistive circuit

eliminates the need for encoder/decoder devices, simplifying design and adding to the

reliability of the TV.

The table shows the voltages input to CPU pin 34 and 35, when a given key is pressed.

CPU

35

34

[${

10Ok K1

g

100k

18k K2

~

18k

6.8k K3

~

6.8k

—

4.7k

~ &o

4.7k

2.7k

~

&l

2.7k

2.2k K6

K12

2.2k

0.27k

10k

‘w

Inputvoltagetopin34

Inputvoltagetopir _

Key

● Rangeof Voltages Function

K1

0.7V- 1.5V

Pos.+

K2

1.5V-’2.lV

Pos.-

K3

2.1V --2.9V

vol. +(Tuslow)

K4

2.9V- 3.5V

vol.

-(Tuslow)

K5

3.5V--4.3V

Vol.+(TuFast)

morethan4.3V

Vol.

-(TuFast)

::F

lessthan0.7V

NoKey

-.

Kev I

● RangeofVoltages

I Function

K7

0.7V-1 .5V

Function

K8

1.5V-2.lV

Preset1

K9

2.lV - 2.9V

Preset2

K1O

2.9V- 3.5V

ColourSystem

K11 3.5V--4.3V

SIFSystem

K12

morethan4.3V

TV/AV

OFF

lessthan0.7V

NoKey

● When the supply voltage is 5.OV.

A7-A

-7-

A7-A

2-2 Option switches

This chassis uses the option function switches to determine several different specifications of

the TV set.

The CPU determines the specification of TV by detecting the voltage level on the following

pins.

Tuner type: pins 17 and 18, Colour system: pin 11, SIF system: pins 36 to 40, Remote control

status: pin 46, Blue back function: pin 45.

Pins 36 to 40 also operate as SIF system selection outputs.

Tuner type

CPU

17

18

Colour system

CPU

11

5

10k

4

5

Rx

10k

Swl SW2 Pinl7 Pinl8

St3ecification

off off H

H 3 band

on

off L

H UHF only

off on H

L

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on on

L L

UHF only

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“ ““lo, ”La,, ”! .

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open

I Colour system A(w/o tint VR)

1.16V

2.00V

2.98V

3.76V

4.95V

33k

Colour system B(w/ tint VR)

15k Colour system C(for VMT)

6.8k

Colour system D(for East Europe)

3.3k

Colour system E(for multi system)

100 Colour system F(for Indonesia, China,)

A7-A

-8-

SIF system

CPU

Iokx

40

39

38

37

36

~W~ I .SWA I SW!i ] SW6 ] .SW7 I .Sn@cification

-..

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---- -----

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- r .-- . . . ..- . . . . .

off off

on

SIF system a(multi system)

off off

off on

on

SIF system b(China, PX)

off off

on on

on

SIF system c(lndonesia)

on off

off off

on

SIF system d(3 system)

on

off

on off

on

SIF system e(lndonesia)

on on

on

SIF system f(No system)

off off

off

SIF system g(France)

Remote control status

1?

5

CPU

46 ,

1

10k

SW8

Specification

*

off

w/ remote centrol function

on

w/o remote centrol function

A7

J

1

Blue back function status

SW9 Specification

off

w/o blue back function

on

w/ blue back function

-9-

A7-A

2-3 System switch output

The outputs from pins 41 to 44 of the CPU select the colour system and the outputs from pins

36 to 40 the SIF system. These outputs drive the colour and SIF system switching circuits.

The operation of each switching circuit is shown in the tables below.

Colour system switching output

Colour system

Output pins Display

44 43 42 41

Auto

LHHL

Auto

PAUNTSC4.43

LLHH

PAUNTSC4.43

SECAM

HLHL

SECAM

NTSC

LHLH NTSC

SIF system switching output

1. Multi system(SIF

system a option)

SIF system

I

Output pins

Display

I

40 39 38 37 36

I

Auto

5.5MHZ

6.OMHZ

6.5MHz

●

HHHL

S1

LHLLL

S2

LLHLL

S3

LLLHL

S4

4.5MHZ IHLLLLIS5

● It dependson receiving TV system

2. China, Px. (SIF system b option)

SIF system

Auto

5.5 MHZ

6.OMHZ

4.5 MHZ

Output pins

I

Display

I

40 39 38 37 36

I

●

HHLL

S1

LHLLL

S2

LLHLL

S3

HLLL LIS4

I

● ItdependsonreceivingTVsystem

.

3. Indonesia (SIF system c option)

SIF system

Output pins

Display

40 39 38 37 36

Auto

●

HHLL

S1

5.5MHZ

LHLLL

S2

4.5MHZ

HLLLL

S3

● Itdepends on receiving TV system

-10-

A7-A

4.3 system (SIF system d option)

L

SIF system Output pins

40 39 38

37 36

Auto

LHHHL

5.5MHZ

LHLLL

6.OMHZ

LLHLL

6.5MHz

LLLHL

Display

S1

S2

S3

S4

5. East Europe (SIF system e option)

SIF system Output pins Display

40 39 38

37 36

Auto

LHLHL

S1

5.5MHZ

LHLLL

S2

6.5MHz

LLLHL

S3

6. No system (SIF system f option)

SIF system Output pins

Display

40 39 38 37 36

----

LLLHL

--

7. France (SIF system g option)

SIF system

Output pins

40 39 38 37 36

IA’

LLLLL

5.5MHZ

LHLLH

6.OMHZ

LLHLH

Display

S1

S2

S3

-11-

A7-A

2-4 Chroma ID

The identification of a colour or black/white broadcast is achieved by sensing the voltage

level input at pin 20. This voltage is supplied from pin 26 of ICI 01 through the inverter circuit,

Q719. When there is a black/white broadcast the voltage on pin 26 goes low.

Normally, pin 26 operates as colour control function, and the control voltage is from pin 4 of

the CPU.

To identify the colour system during a black/white broadcast, the CPU judges that the system

is NTSC when the following conditions are detected at same time.

(1) The colour system is “AUTO” or “NTSC” system.

(2) The field frequency is 60 Hz.

(3) TV/AV mode is “TV” mode.

CPU

Pin20 Judgement

L

Colour broadcast

[H

I BW

broadcast I

20

—

i

R778

5.6k

●

AA

,.

R778

5.6k

t

C742

1

Colour control from pin4 of

CPU

A

ICI 01

Chroma/Def.

26

2-5 Ident (Identification)

The identification of the receiving signal status is done by the CPU sensing the voltage level

at the input pin 15, as shown below. The ident signal is presented at pin 4 of IC101 and fed to

pin 15 of the CPU through the converter circuit consisting of Q708, R765 and R764.

When the CPU judges that the system is 4.43MHz, it outputs a “Low” signal from pin 40 to

select PAIJSECAM system.

CPU

15

4C

Q

8V

I

Iclol

Chroma/Def.

Q708

R767

100

w

4

Y&”

I

:::: I I

10k

C718

C132

0.01 0.1

Pin40

Pin15

Judgement

Signal status

L

O-1.8V

4.43MHZ No sync.

H

1.8V - 4.3V

3.58MHz

Signal present

L

4.3 v - 5.OV

4.43MHZ

Signal present

I

_.

A7-A

-12-

A7-A

2-6 Sync. ID

When no signal is received the voltage on pin 14 of IC101 changes to “Low”. As a

consequence, D804 and Q718 are turned on, and a “High” is supplied to pin 32 of the CPU.

As a result, the CPU judges that no signal is being received. In the AV mode, the CPU

outputs a “High” signal from pin 51 to drive the blue back function.

CPU

32

Pin32

I Judgement

I

L(O-2.OV)

Signal present

H(4.OV-5.OV)

No signal

0718

4

Q

R765

5.6k

Sharpness control from

CPU~

Iclol

Chroma/Def,

14

A7-A

2-7 Bus control

This chassis uses the IPC bus as the interface for operation control between ICS, and the

CPU is used as the master for operation control of the Teletext decoder IC and Memory IC

(i.e. Teletext and memory functions).

The IPC bus is composed of the SCL(Serial Clock Line) and SDA(Serial Data Line) lines.

Data is transmitted over the SDA line in 8-bit units in synchronisation with the SCL line.

CPU

12

13

IC790

R742

Memory

IC

4.7k

6

c

5

‘OTe’e’ex’demdejGdJ

-13-

A7-A

2-8 Band switching circuit

The band switching control signals are outputted from pins 21 and 22 of the CPU and fed to

pins 3 and 4 of the band switching IC.

This IC then outputs the drive voltage(+l 2V) to the tuner from either pins 1, 2, 7 or 8

according to input signal.

The table below shows the input/output logic of the band switching IC.

Antenna

L

Tuner

IC710<LA791 o>

VL

VH

HP

u

Band swit[

4

1

4

2

3

4

7

4

●

8

Band Switching IC Logic

1

CPU

21

22

I

Input

I

output

I I

I Pin 3 Pin 4 I Pin 1 Pin 2 Pin 7 Pin 8 I Selected Band I

w

LL

H---

VHF-LOW

HL -H --

VHF-High

LH --H-

Hyper

HH ---H

UHF

-14-

A?-/l

w

2-9 Linear AFT

The AFT-S signal which is outputted from pin 44 of ICI 01 is supplied to the AFT pin on the

tuner through the AFT defeat circuit consisting of Q704, Q705, Q706 and Q707. The AIT

defeat circuit is driven by the AFT defeat signal output from pin 10 of the CPU, which is AFT

ON (L) or AFT OFF (H).

During normal operation, the AFT-S signal is supplied to AFT pin on the tuner through Q706

and Q705.

During tuning or channel changing, Q704 is turned on by the “High” signal from pin 10 of the

CPU. When Q704 is turned on, Q705, Q706 and Q707 are turned off. As a result, the AFT-S

signal is prevented from reaching the tuner, and the DC voltage from divider R754 and R753

.

is supplied to the AFT pin on the tuner instead.

Once the tuning or channel operation is completed, the AFT-S signal is supplied to the AFT

pin on the tuner again.

For this reason it is called Linear AFT.

Iclol

lF/Video/chroma

-–8” L -–Y i ‘“ner ,

J1#19t##91#1111,,,,a, #,m,,*,,*,,m,,,,,,,,,,,,,,,,#

AFT

Q706

.—-—. —-

44

we*999aa188n88s9aaau11*.ammmanmam.m80s08n8w88,

1

R756

4.7k

C741

0.1

Q707

/

AFTON 1AFTOFF

CPU

10

AFTDefeat

-15-

A7-A

2-10 Digital AFT

The tuning system of this chassis also utilises a digital AFT system.

In this operation, the tuner is automatically adjusted to the required tuning point of the

broadcast signal by increasing and decreasing the tuning voltage within the synchronisation

range, whilst checking the 2 signals from the lF/Video decoder IC, ICI 01 cTDA8361/8362z.

The signals which are outputted from pins 4 and 44 of ICI 01 are fed to pins 15 and 33 of the

CPU via the impedance and voltage converter circuit.

The CPU checks the voltage level of the Ident signal at pin 15 and the AFT-S signal at pin

33, and controls the tuning voltage which is supplied to the tuner.

The CPU determines that the correct tuning point is achieved when the Ident signal is Hi(5V)

and the AFT-S signal is 2.OV to 3.OV.

When the Ident signal is Hi(5V) and AFT-S signal is greater than 3.OV, the CPU judges that

the tuning point is incorrect and increases the tuning voltage output from pin 14 of CPU to

correct the tuning point.

When the Ident signal is Hi(5V) and AFT-S signal is less than 2.OV, the CPU again judges

that the tuning point is incorrect and decreases the tuning voltage output from pin 14 of CPU _

to correct the tuning point.

This function only operates during the channel changing and the presetting modes.

-16-

A7:A

runer

TU

AFT

Q711

CPU

IDENT IN

14

15

TUNING OUT

AFTIN 33

10AFT Defeat

o

8V

C746 R764

0.01 10k

o

8V

&“’”-

R121

Q781

47k

R781

z vi”

4.7k

7.

[

X8V

...............................

..al...b..b

:

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AFT

;

:

Defeat

:

Circuit

Iclol

lF&VIDEO

$

IDENT(T.B.)

44 AFT

Input Signal

Pin 33

AFT S-Curve

of IC701

Input

A \

,;!

,,1

,,,

,;1

#c

,

,.,

,1

.“:1

Pin 14

of IC701

Pin 15

of IC701

Tuning

Ident

Signal

Voltage

Input

‘ Tuned point

Input Voltage Level of Pin 33

Judgement

LL(OV-1.5V)

Tuning Voltage Down

L (1.5V-2.OV)

Tuning Voltage Down

M (2.O-2.5V)

Tuned

H (2.5V-3.OV)

Tuning Voltage Up

HH(3.5V’5V)

Tuning Voltage Up

3.5V

3.OV

2.OV

1.5V

Ov

-17-

A7-A

2-11 Power On/stand-by and Protection circuit

6)

@

Power On/Stand-by

The power on/stand-by signal is outputted from pin 48 of CPU.

When the stand-by mode is selected the voltage of pin 48 changes from Hi(5V) to

Low(OV), which turns on Q703 and Q715. Q715 drives the photo-coupler D515 which in

turn drives Q512 on. Finally Q512 stops the oscillation of power circuit switching the TV

into the stand-by condition.

At the same time, Q703 drives the LED, D803 to illuminate and indicate the stand-by

mode.

Protection circuit

A protection circuit is provided to protect the TV set in case of a circuit malfunction.

When an abnormality occurs during TV reception it causes pin 31 of the CPU to go

continually Low (less than 0.8V). After one second, the CPU detects that a power failure

has occurred on the TV set, and the CPU turns the TV into the stand-by condition.

CPU

D591

:

~

...

..................................

....:

\

-....”..................................

- POwerfailure

D486

D485 ~-—

5V

FBT

i=~ Power fail

operation

-----------------------------------Ov

:

z

r:

. . . . h R807

:

-~

I

:

330

.—-—. —-—

:

5v—-—-

7

Power On Stand:By

D803& \powerm {

.............................Ov

s.,...............n.......c“....”.............””.0.00.!

—

*’

-18-

A7-A

2-12 Power On/stand-by circuit (RC Transformerless model)

O Power On/Stand-by

The power on/stand-by signal is outputted from pin 48 of CPU.

When the stand-by mode is selected the voltage of pin 48 changes from Hi(5V) to Low(OV)

to turn on Q703 and Q715, and turns off Q552. Q552 turning off causes Q551 and Q554

to turn off. B4 +24V supply for vert. & horiz. output circuit, B7 +8V supply for

lF/Video/Chroma circuit and B6 +12V for tuner circuit are all cut off, resulting in the TV set

going into the stand-by mode.

At the same time, Q703 causes LED D803 to illuminate and indicate the stand-by mode.

When the TV is switched back into the power on mode, Q551 and Q554 are turned on and

the relevant voltages are supplied back to each circuit.

.—. —.— .—

.,.....................

...”

0551

~

:... ..-..y .

VerL&Horiz

;

i

~

output

●“.”+....* ,

circuit

i

0554

; ..........7 k. —.—. —.—;

..... .......... ;

05

.—. —.— .—

;

::

:

15V

7

;:

:.....+....... :

:

:<

~ Power ~

.—. —.— .—.

~ supply

-

‘--I

; circuit :

.—. —.—. —.

;

~

I-Gacb ~

s.................................

l......1....._....l-m

f=+=

I

CPU

R808

330

/’

D803

5v—-—-

1

fi ‘p”e-

Power On Stand-By

.............................Ov

-19-

A7-A

2-13 Protection circuit (RC transformerless model)

This chassis employs two kinds of protection circuit, one controlled by software through the

CPU and the other by hardware.

Protection circuit (software)

The protection circuit is provided to disable the operation of the TV set in case of a circuit

malfunction.

When an abnormality occurs during TV reception it causes pin 31 of the CPU to go

continually Low (less than 0.8V) for about one second. The CPU detects that this has

occurred and outputs the signal to cut off Q551 and Q554.

Protection circuit (hardware)

When a power failure is detected by diodes D565, D566 and D564, this protection circuit

operates causing the power oscillation to stop.

If one of the above diodes is turned on, the voltage of Q553-emitter decreases, and it turns

on completely. Photo-coupler D515 is driven by this and generates a current which drives -

Q512 on. As a result, the operation of the power oscillation circuit is stopped.

Under normal circumstances these parts, D515, Q553, D561, R552, R553, VR551, are

operating as the error detection and regulation circuit for B1 +130V power supply.

-=—.—=— ■ 

1.,., . . . . . . . . . . . . . . . . . . . . . “~

0551

!

Vert.&Horiz:.... ........

:

L.—.—.—.—m

T511 j

.—. —.— .—

:...-......: :

.

:

Power ~

.—. —.—. —

supply j

circuit ~

.—. —.— .—.

;

:

..........“........”M..”

CPU

Protect 31

Power 4S

Normal

Power faiiuer

operation

I

T

v

R780

lOOk

I

~ Power On ~.aoo,...........,

...............................

~ Stand-By ,

circuit

;

:

;

~

DS93

:

..................

g1m#a8a81*a#f*9a*aam11#11a11*99#66*sl@11# 11m1am11m11:

—

D515 :

:

~

:

~

R552

VR551

:

R553

~

:111n#8##1n111111

o#ta809##1#11988BB1a18Ba11aIlalaI*

Regulator

circuit

Norma

operation

-

-20-

A7-A

w

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Sanyo C21ZM45 Training manual

Sanyo C21ZM45 Training manual

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