Freescale Semiconductor
Addendum
MSC8158ERMAD
Rev. 0, 12/2010
© 2011 Freescale Semiconductor, Inc.
CONTENTS
1 Reset....................................................................2
2 SC3850 DSP Subsystem.....................................2
3 DDR SDRAM Memory Controller.....................3
4 High Speed Serial Interface (HSSI) Complex....4
5 Serial RapidIO Controller and Enhanced Message
Complex..............................................................4
6 Common Public Radio Interface (CPRI)..........11
7 QUICC Engine Subsystem ...............................16
8 Debugging, Profiling, and Performance
Monitoring........................................................20
9 Security Engine (SEC)......................................21
This document provides updates to revision 0 of the
MSC8158E Reference Manual (MSC8158ERM). The changes
are organized by the chapters that are affected.
MSC8158E
Reference Manual Addendum
MSC8158E Reference Manual Addendum, Rev. 0
2 Freescale Semiconductor
Reset
1 Reset
) In Table 5-5 on page 5-13, replace the rows for bits 16 and 17 with the following:
) In Table 5-7 on page 5-15, replace the row for bit 16 with the following:
) In Table 5-9 on page 5-17, replace the row for SCLK0 {16] with the following:
) In Table 5-11 on page 5-18, delete the row for mode 22 (0010110).
2 SC3850 DSP Subsystem
) On page 10-13, add the following new subsection:
10.12 Programming Restrictions
The MSC8158E has the following programming restrictions when using the SC3850 DSP Subsystem:
When performing a write operation to the cache when combined with a DFLUSH/DSYNC, the write hit
can be lost and data is not written for the following scenarios:
— Write hist lost after DSYNC/DFLUSH with parallel WRITE/FETCH with no match.
— Write hit before DSYN is lost when the entrance to LWB is delayed by contentions.
Use the following steps to prevent the write hit loss:
1. Insert a SYNCM instruction between a READ/WRITE/DFETCH/DMALLOC to the same 256 bytes
followed by a DFLUSH/DSYNC command.
2. Use a SYNCM instruction after the last DFLUSH/DSYNC instruction.
3. No write is allowed between the first DFLUSH/DSYNC and the last DFLUSH/DSYNC SYNCM.
17 SCLK1 RC14 SerDes PLL1 reference clock. A 0 selects 100 Mhz (SRIO/PCI
Express/SGMII) and a 1 selects 125 MHz (SRIO/PCI
Express/SGMII)/122.88 MHz (CPRI). See Table 5-9 for details
and limitations.
16 SCLK0 RC14 SerDes PLL0 reference clock. A 0 selects 100 Mhz (SRIO/PCI
Express/SGMII) and a 1 selects 125 MHz (SRIO/PCI
Express/SGMII). See Table 5-9 for details and limitations.
16 SCLK0 1 SerDes PLL0 reference clock. A 0 selects 100 Mhz (SRIO/PCI
Express/SGMII) and a 1 selects 125 MHz (SRIO/PCI
Express/SGMII). See Table 5-9 for details and limitations.
SCLK0
16
0 SerDes0 Reference Clock
Selects the SerDes0 reference clock. 100 MHz
clock can work for all protocols and frequencies
except for 3.125 Gbaud RapidIO; 125 MHz
works for all protocols and frequencies with no
exceptions.
0 SerDes reference clock = 100 MHz (SRIO/PCI
Express/SGMII).
1 SerDes reference clock = 125 MHz (SRIO/PCI
Express/SGMII).
DDR SDRAM Memory Controller
MSC8158E Reference Manual Addendum, Rev. 0
Freescale Semiconductor 3
Always configure the Subsystem Port Priority Control Register (TSPPCR) general configuration register
to high priority. The L2 cache arbiter does not treat the slave port access as part of the Round Robin
arbitration scheme. Therefore, when the slave port accesses the cache with high priority, it always wins the
arbitration. Because the slave port operates at half the frequency of the L2 and L1 caches, the cumulative
L1 (I$ and D$) theoretical bandwidth can drop to 50% versus 33% in full Round Robin. When the slave
port accesses the cache at low priority, the L1 (I$ and D$) always wins the arbitration and the slave port
performance can decrease significantly. Arbitration between I$ and D$ is round robin with priority as
defined.
3 DDR SDRAM Memory Controller
) Add the following in Section 12.3.8 after Figure 12-11 on page 12-18:
To guarantee that the t
STAB
timing requirement is met for registered DIMMs, you must modify the automatic
Register Control Word (RCW) sequence enabled by DDR_SDRAM_CFG_2[RCW_EN] that modifies RC10. This
does not apply to SODIMMs. Use the following steps to modify RC10 for higher frequency registered DIMM
operation to meet the JEDEC specification requirements:
1. Write all DDR registers, but leave DDR_SDRAM_CFG[MEM_EN] cleared. Note that address parity should also be
enabled if writing to the RCWs.
2. Disable automatic CPO by ensuring that TIMING_CFG_2[4:8] are not set to all 1s.
3. Write 0x00000400 to the register at address 0xFFF20F08.
4. Disable ZQ calibration by clearing DDR_ZQ_CNTL[ZQ_EN].
5. Disable write levelling by clearing DDR_WRLVL_CNTL[WRLVL_EN].
6. Disable the automatic RCW sequence by clearing DDR_SDRAM_CFG_2[RCW_EN].
7. Ensure that DDR_SDRAM_CFG_2[D_INIT] is cleared and the memory test is disabled (DDR_MTCR[MT_EN] is
cleared).
8. Write 0x00000015 to the register at address 0xFFF20F30.
9. Write 0x24000000 to the register at address 0xFFF20F54.
10. Disable refreshes by clearing DDR_SDRAM_INTERVAL[REFINT].
11. Set DDR_SDRAM_CFG[BI].
12. Enable the DDR controller by setting DDR_SDRAM_CFG[MEM_EN].
13. Poll until bit 1 of the register at address 0xFFF20F04 is asserted by hardware. This indicates that the controller is idle.
14. Use the DDR_SDRAM_MD_CNTL register to write RC10 for any DIMMs that are used. Note that if two registered
DIMM modules are used, this requires two separate writes to the DDR_SDRAM_MD_CNTL register. Ensure that either
a decoding of 0b100 or 0b101 is used for the CS_SEL field, and WRCW should be set by the controller. After each write
to the DDR_SDRAM_MD_CNTL register, DDR_SDRAM_MD_CNTL[MD_EN] should be polled until it is cleared by
hardware.
15. Wait for t
STAB
as defined by the register specifications.
16. Clear DDR_SDRAM_CFG[MEM_EN].
17. Clear DDR_SDRAM_CFG[MEM_EN].
18. Restore all registers back to the original settings. This may also include enabling DDR_SDRAM_CFG_2[RCW_EN] if
more RCWs will be modified. If this bit is set, ensure that DDR_SDRAM_RCW_2[RCW10] is programmed to provide
the same value as that programmed via the DDR_SDRAM_MD_CNTL register in step 14.
19. Set DDR_SDRAM_CFG[MEM_EN].
20. The DDR controller should now be operational.
) Add the following note after the first sentence of Section 12.4.2 on page 12-31:
Note: The DDR controller has an internal adjustment circuit use for automatic calibration. To prevent
degradation of DDR transfer performance, disable this circuit before enabling the DDR memory using the
following steps:
MSC8158E Reference Manual Addendum, Rev. 0
4 Freescale Semiconductor
High Speed Serial Interface (HSSI) Complex
1. Write a value of 0x00000015 to the register at address 0xFFF20F30.
2. Write a value of 0x24000000 to the register at address 0xFFF20F54.
) Replace the MEM_EN row of Table 12-23 on page 12-50 with the following:
4 High Speed Serial Interface (HSSI) Complex
Add the following note after the note in Section 15.10.13 on page 15-45:
Note: For some configurations, using the OCN2MAG bridges for both reads and writes can yield write
transactions that write bad data. To preclude this scenario, use one bridge for Write transactions and the
other bridge for read transactions by setting the C1ATD[DEN] and C1ATD1[SPRW] bits.
5 Serial RapidIO Controller and Enhanced Message
Complex
) Add the following note after Table 16-1 on page 16-8:
Note: Transferring high data rates at 5 Gbaud in x1 mode is not recommended and can result in excessive errors
(including CCS, CRC, DE, and PE) and dropped data. For high data rates, use 5 Gbaud in x2 or x4 mode.
For lower data rates, use 3.125 Gbaud in x1, x2, or x4 mode.
) Add the following subsection before Section 16.2 on page 16-9:
16.1.3 Link Training
During port initialization, the serial RapidIO port performs lane synchronization (detecting valid symbols on a
lane) and lane alignment (coordinating multiple lanes to receive valid data across lanes). Internal errors in lane
synchronization and lane alignment may cause failure to achieve link initialization at the configured port width. An
SRIO port configured as an x4 port may see one of three scenarios:
One or more lanes fail to achieve lane synchronization. Depending on which lanes fail, this may result in
downtraining from x4 to x2, x4 to x1 on lane 0, x4 to x1 on lane R, x2 to x1 on lane 0, or x2 to x1 on lane
R. (R indicates a lane other than lane 0).
The link may fail to achieve lane alignment as a x4, even though all four lanes achieve lane
synchronization, and downtrain to x2 or x1 mode.
MEM_EN
31
0 DDR SDRAM Interface Logic Enable
Enables/disables SDRAM interface logic. This bit
must not be set until the initialization code has
appropriately configured all other memory
configuration parameters.
Note: Before enabling the DDR memory, always
disable the internal adjustment circuitry
using the following steps:
1. Write a value of 0x00000015 to the register
at address 0xFFF20F30.
2. Write a value of 0x24000000 to the register
at address 0xFFF20F54.
0 SDRAM interface logic is disabled.
1 SDRAM interface logic is enabled.
Serial RapidIO Controller and Enhanced Message Complex
MSC8158E Reference Manual Addendum, Rev. 0
Freescale Semiconductor 5
If the link downtrains to x2, it may fail to complete link initialization (that is, PnCCSR[PU]=0, indicating
that the port initialized, but [PO]=0, indicating that the port is not OK).
A serial RapidIO port configured as x2 may downtrain to x1 on lane 0 or lane R because of the first scenario. A
serial RapidIO port configured as n x1 may fail to complete port initialization (PnCCSR[PU] will never deassert)
because of the same scenario. Once a port completes link initialization successfully, it will operate normally.
To facilitate proper training, perform the following software sequences on each serial RapidIO port prior to
initiating any traffic to that port.
16.1.3.1 Initialize Link
1. Ensure that the configured port width matches the actual port width in the system.
a. If the configured port width is wider than the width supported by the link partner or system, the SRIO port
will train down to the highest common denominator, causing a false detection of a training issue.
b. The configured port width per port is readable in SERDES SRDSPCCR0.
2. Start a counter set to ~2 ms after the SERDES reset is complete (SERDES SRDSBnRSTCTL[RST_DONE]=1
for n corresponding to the SERDES bank/PLL for the SRIO port).
3. Poll the port uninitialized status (SRIO PnESCSR[PO]) until PO=1 or the counter expires. If the counter
expires, the port has failed initialization: go to Reset Link
4. Read SRIO PnCCSR
a. For a port configured as a x4, if IPW≠b010, the port has failed initialization: go to Reset Link.
b. For a port configured as a x2, if IPW≠b011, the port has failed initialization: go to Reset Link
5. Continue with normal SRIO initialization procedures or software retraining sequence
16.1.3.2 Reset Link
1. Set SRIO PnCCSR[PD]=1
2.
Wait 50 µs.
3. Set SERDES LmGCR0BnGCRm0[RRST]=0 for each bank n and lane m used by the SRIO port
4. The lanes used by the SRIO port are readable in SERDES SRDSPCCR0.
5. Read SERDES LmGCR0BnGCRm0 for each bank n and lane m in step 3
6. Wait ≥ 100 ns.
7. Set SERDES LmGCR0BnGCRm0 [RRST]=1 for each bank n and lane m in step 3
8. Read SERDES LmGCR0BnGCRm0 for each bank n and lane m in step 3
9. Wait ≥ 300 ns.
10. Write 1s to clear all bits in SRIO PnSLCSR
11. Set SRIO PnCCSR[PD]=0.
12. Go to Initialize Link (Section 16.1.3.1).
MSC8158E Reference Manual Addendum, Rev. 0
6 Freescale Semiconductor
Serial RapidIO Controller and Enhanced Message Complex
16.1.3.3 Software Retraining
If the serial RapidIO port needs to retrain for any reason (for example, link partner reset), execute the following
modified software retraining sequence:
1. Software on the host must ensure that all RapidIO transactions have completed and link activity has stopped.
2. Set SRIO PnCCSR[PD]=1
3. Set SRIO PnPCR[OBDEN] on the host to enable the discarding of any pending packets. (There should be none
if proper steps were taken to ensure there was no link activity.)
4. Clear SRIO PnPCR[OBDEN] on the host.
5. Configure new operating width (via PnCCSR[PWO]) or any other new configurations.
6. Go to Reset Link
Note: Step 1 of the Reset Link procedure is redundant with step 2 of Software Retraining sequence, but is not
harmful to repeat.
Note: The retraining sequence resumes at step 7 after completing the Initialize Link sequence.
7. Poll PnESCSR[PO] on the host until it is set, which indicates the link has attained port and link initialization.
8. Poll PnESCSR[PO] on the agent until it is set, which indicates the link has attained port and link initialization.
9. Poll PnESCSR[OES] on the agent until it is clear, which indicates the link has completed the error recovery
sequence initiated from the port disable.
10. Poll PnESCSR[OES] on the host until it is clear, which indicates the link has completed the error recovery
sequence initiated from the port disable.
11. Clear the agent error and status registers.
12. Clear the host error and status registers.
13. Begin normal packet transfer.
16.1.3.4 Special Case of x2/x1 Modes
The Freescale RapidIO controller may fail to complete training if it tries to connect to a RapidIO device that
supports x2 mode and x1 mode if the devices transmits the same data on lanes 0 and 1 when in x1 mode.
Note: Freescale Serial RapidIO controllers transmit only on lane 0 if initialized as x1 on lane 0 and only transmit
on lane 1 when initialized as x1 on lane 1.
Always ensure that the serial RapidIO controller is configured to match the configured width of the link partner.
The preferred mechanism is through the RCW configuration. To recover after detecting a training failure due to
mismatched width configuration and before restarting traffic, execute the Software Retraining sequence
documented in Section 16.1.3.3 and disable x2 operation by configuring PnCCSR[PWO] equal to 0b010, 0b011, or
0b110.
) Add the following note after the last bullet on page 16-87:
Note: No more than one PDU from a given RapidIO flow should be segmented at a time.
) Add the following after the first paragraph in Section 16.3.8.2 on page 16-118:
Serial RapidIO Controller and Enhanced Message Complex
MSC8158E Reference Manual Addendum, Rev. 0
Freescale Semiconductor 7
Note: A non-Freescale RapidIO Type9 destination endpoint may be unsuccessful in correctly reassembling two
or more PDUs from the same source with the same RapidIO flow when interleaving is done based on CoS.
The eMSG segmentation engine includes the RapidIO field CoS (Class-of-Service) field when determining
segmentation interleaving dependencies, thus PDUs of the same flow but different CoS may be
interleaved. Use one of the following two methods to avoid this problem.
1. Assign outbound Type9 PDUs of the same flow with the same CoS to force a dependency between the
PDUs, thus avoiding segmentation interleaving.
2. Set register bit MUMR[OSID] = 1 to disable segmentation interleaving on a destination ID basis.
However, this affect all supported types and may affect performance.
) Add the following note after the paragraph in Section 16.3.4 on page 16-94:
Note: Do not use the scatter/gather table format for Type5, Type6, or Type9 messages during outbound
segmentation. Using this format can result in segmentation unit counters being corrupted by a descriptor
error (DE).
) In Section 16.3.4 on page 16-95, replace the last paragraph with the following:
The overall data payload length as defined by the command descriptor is also used to determine the end of a
scatter/gather table. If the length has been reached, regardless of the final bit setting, the last data segment has been
reached. The following occurs when the length has been reached, but the final bit is not set, and a buffer release
was requested (BR=1):
Any subsequent data buffer pointer(s) are not released
Current and subsequent S/G table pointer(s) are not released
If software requires all pointers to be released, the final bit must be set for the last data entry as determined by the
length field.
) Add the following note after the paragraph in Section 16.3.8.3 on page 16-124:
Note: Do not use the scatter/gather table format for Type9 messages during outbound segmentation. Using this
format can result in segmentation unit counters being corrupted by a descriptor error (DE).
) In Table 16-72 on page 16-199, replace the PWO [26–24] row with the following:
PWO
26–24
0b000 Port Width Override
Soft port configuration to control the width modes
available for port initialization. The meaning of bits
25–24 is determined by the value of bit 26. When bit
26 = 0b1, bit 25 controls enabling x4 mode and bit 24
controls enabling of x2 mode.
Note: This field should be changed only when the
port is uninitialized. To achieve this, first set
PnCCSR[PD] to 1 (port disabled). Then
change PWO to any legal value. Finally, set
PD back to 0 (enabled)
000 No override (the default).
001 Reserved.
010 Force single lane, lane reversal
not forced.
011 Force single lane and lane
reversal.
100 x2 and x4 mode disabled.
101 x2 mode enabled, x4 mode
disabled.
110 x2 mode disabled, x4 mode
enabled.
111 x2 mode enabled, x4 mode
enabled.
MSC8158E Reference Manual Addendum, Rev. 0
8 Freescale Semiconductor
Serial RapidIO Controller and Enhanced Message Complex
) In Table 16-72 on page 16-199, replace the OPE [22] row with the following:
) Replace the SIZE row in Table 16-134 on page 16-260 with the following:
OPE
22
1 Output Port Transmit Enable
Specifies whether the port is enabled to issue
packets. If OPE = 0, the following conditions apply:
• Inbound non-maintenance requests packets can
generate responses.
• If the device configuration allows outbound requests
to be pending in the controller, inbound maintenance
requests do not generate responses.
• Outbound maintenance requests are not be
transmitted.
Set the bit (1) to allow transmission of any request or
response packet. To allow responses to inbound
maintenance requests when OPE = 0, disable any
LAWs with a RapidIO target to prevent outbound
request packets from being sent to the RapidIO
controller. The initial value of OPE is read from
configuration pins.
0 Port is stopped and not enabled
to issue packets.
1 Port is enabled to issue packets.
31–16 SIZE
Buffer size. Indicates the buffer size for the Buffer Pool used.
0x0000 64K bytes
0x0040 64 bytes
0x0041 65 bytes
...
0x0080 128 bytes
0x0081 129 bytes
...
0x0100 256 bytes
...
0xFFFF 64K bytes – 1
Minimum buffer size is 64 bytes.
Note: If 0xFFFF is selected, the inbound buffer size is interpreted as 0 bytes and not 64Kbytes.
Therefore, do not select this value. If the buffer size is 64Kbytes, the software can set
IBmT9CnhDBPR[SIZE] to anything less than 64Kbyte, but larger than the required
message size to avoid a buffer size error.
Serial RapidIO Controller and Enhanced Message Complex
MSC8158E Reference Manual Addendum, Rev. 0
Freescale Semiconductor 9
) Replace the SIZE row in Table 16-136 on page 16-262 with the following:
) Replace the SIZE row in Table 16-153 on page 16-277 with the following:
31–20 SIZE
Buffer size. Indicates the buffer size for the Buffer Pool used.
0x000 64K bytes
0x004 64 bytes
0x005 80 bytes
...
0x008 128 bytes
0x009 144 bytes
...
0x010 256 bytes
0x011 272 bytes
...
0xFFF 64K bytes - 16
Minimum buffer size is 64 bytes. The 4 least significant bytes in the size field are unused since the
S/G record size is 16 bytes
Note: If 0xFFF is selected, the inbound buffer size is interpreted as 0 bytes and not 64Kbytes.
Therefore, do not select this value. Normally, scatter/gather data buffers are much
smaller than 64Kbytes. If the actual data payload size is 64Kbytes, software must also
account for the descriptor size, which will not fit in a single 64Kbyte buffer. The software
can set IBmT9CnSGBPR[SIZE] to indicate anything less than 64Kbyte, but larger than
the required scatter/gather size to avoid a buffer size error.
31–16 SIZE
Buffer size. Indicates the buffer size for the Buffer Pool used.
0x0000 64K bytes
0x0040 64 bytes
0x0041 65 bytes
...
0x0080 128 bytes
0x0081 129 bytes
...
0x0100 256 bytes
...
0xFFFF 64K bytes – 1
Minimum buffer size is 64 bytes. Although larger buffer sizes are supported, message data payload
is maximum 4K bytes plus descriptor size. The minimum buffer size must account for the last
segment being equal to the segment size. For example, if the message has 4 segments and the
segment size is 256 bytes, the buffer size must accommodate the maximum data payload of 1 KB,
regardless of the last segment size.
Note: If 0xFFFF is selected, the inbound buffer size is interpreted as 0 bytes and not 64Kbytes.
Therefore, do not select this value. If the buffer size is 64Kbytes, the software can set
IBmT11CnhDBPR[SIZE] to anything less than 64Kbyte, but larger than the required
message size to avoid a buffer size error.
MSC8158E Reference Manual Addendum, Rev. 0
10 Freescale Semiconductor
Serial RapidIO Controller and Enhanced Message Complex
) Add the following new section after Table 16-243 on page 16-350:
16.5 Programming Restrictions
The MSC8158E has the following programming restrictions regarding the programming of the eMSG unit:
The message manager performs pre-fetching of descriptors when sending outbound RapidIO Type5,
Type6, or Type9 transactions. This occurs as a fetch of the first scatter/gather table entry followed by the
message descriptor when the format is defined as scatter/gather. The message manager allows for out-of-
order pre-fetching between transactions such that a Type9 may fetch the scatter/gather table entry,
followed by a Type11 fetching the message descriptor. In this case, the Type11 transaction is ready for
segmentation before Type 9. In the event a scatter/gather type transaction receives the message descriptor
at the same time a newer transaction is sent to an outbound segmentation unit, there is a possibility the
scatter/gather transaction is lost. The loss is due to using multiple arbitration groups and mixing data
formats. Limiting to a single arbitration group, however, can affect performance. If an application must
mix data formats, use a single arbitration group. If only one type of data format is used, there are no other
restrictions.
The eMSG unit can transmit a duplicate message segment when the same arbitration group (typically
equals the SRIO flow level) is allowed to use more than one segmentation unit and the messages are not all
multicast type. For a single segment message, the duplication does not produce an error during eMSG
inbound reassembly. For multi-segment messages, eMSG inbound reassembly produce a time-out error
when only a single segment is received for a multi-segment message. Use one of the following two options
to avoid this situation:
1. Restrict messages to single segment and enable multicast. Messages intended for only one destination
must be set to a multicast of one with the correct bit set in the multicast list.
2. Restrict a given arbitration group to use only one segmentation unit. For example, Arb group 0 uses
SU 0, Arb group 1 uses SU 1, and so on. There is a varying performance impact when using fewer Arb
groups than the number of segmentation units. Execution privileges can be set in MMSEPR. This
option also requires the following rules:
a. A message context cannot be reused across arbitration groups.
b. A dummy message must be sent through all segmentation units used for messages OR you must
avoid the use of mailbox 0, letter 0, or destination 0.
Common Public Radio Interface (CPRI)
MSC8158E Reference Manual Addendum, Rev. 0
Freescale Semiconductor 11
6 Common Public Radio Interface (CPRI)
) Replace Figure 17-4 on page 17-10 with the following:
Figure 17-4. Autonegotiation Setup Flow
autonegotiation reset
Error occurred that needs resetting the CPRI block
(A reason for it can be a CPRI Error Interrupt)
The new line rate shall be selected:
if current line rate = 3.072 GHz ---> new line rate = 2.457 GHz
if current line rate = 2.457 GHz ---> new line rate = 1.2288 GHz
.
if current line rate = 4.914 GHz ---> new line rate = 3.072 GHz
if current line rate = 6.144 GHz ---> new line rate = 4.914 GHz
Write the receive divider value for the active cpri lanes:(LnGCR0[RRAT_SEL)
Write the transmit divider value for the active cpri_lanes:(](LnGCR0[TRAT_SEL])
Reset the SerDes by writing to SRDSB2RSTCTL[RSTREQ].
Write the cpri_link_rate in the HSSI_CR2[CPRI_LINK_RATE]
Reset the CPRI by writing to HSSI_CR2[CPRI_RESET].
Write new rate to CPRI PLL rate register (SRDSB2PLLCR0[FRATE_SEL])
Disable the CPRI clocks by clearing the CPRICCR register
The core polling CPR_STATUS status register for 10 ms to see that the link is synchronized
CPRI_STATUS[3:0] != 0xe after 1ms
- Init registers CPRInRGCM and CPRInTGCM - max number of AxCs
CPRI_STATUS[3:0] = 0xe
Read HSSI_SR[SERDES2_RST_DONE] bit and GSR3[SD2_RST_ERR] bits
SERDES2_RST_DONE=0b1 &
Enable the CPRI clocks by writing to the CPRICCR
Wait for 1ms.
SD2RST_ERR =0b0
no
yes
REMARKS:
1 When SFP signals (CP_LOSi) are not connected (e.g. in loopback configuration during
Development phase) the GCR6[RMII2_SEL] bit must be set.
2. When SFP signals (CP_LOSi) are connected (as CPRI standard implies) the GCR6[RMII2_SEL] bit should be
set according to which pins the LOS signals are connected to (GPIO or RGMII). Default is RGMII.
- Init register CPRInTCFBS - Transmit buffer size (if needed)
- Reset the Transmit Control Table (See
- Reset Configuration Memories (RCM and TCM)
- Enable auxiliary mode and mask (if needed)
- Enable RX-TX operation in register CPRI_CONFIG after the other configurations
Autonegotiation flow for link rate finished successfully
Continue to Stage C
Section 18.3.1.5.1)
3. Lane J must always be configured to the same speed as all the other active lanes (even if lane 9 is not active).
That is, LJGCR0[RRAT_SET] and [TRAT_SEL] must be configured as the active lanes.
MSC8158E Reference Manual Addendum, Rev. 0
12 Freescale Semiconductor
Common Public Radio Interface (CPRI)
) Replace the first paragraph in Section 17.3.1.5.3 on page 17-25 with the following:
The Ethernet MAC is connected to the Ethernet interface of the CPRIn_RX and CPRIn_TX modules with a
synchronous MII. The number of CPRI control words used for Ethernet frame transfer is controlled by the Fast
C&M pointer, which is mapped into control byte Z.194.0. This pointer can be set to values from 0x14 to 0x3F.
When the Ethernet channel is not used, set the pointer to 0x3F, which means that 4 control words are dedicated for
Ethernet and 188 for VSS. To block reception of Ethernet packets, write all zeros to register
CPRIn_ETH_CONFIG_1. To prevent transmission of Ethernet packets, do not prepare any BDs. The size of each
control word depends on the link rate. Ethernet transfer uses all the bytes of the relevant control words so the
achieved Ethernet bit rate depends on both the link rate and the Fast C&M pointer.
) Replace the third paragraph in Section 17.3.1.5.3 on page 17-25 with the following:
When an Ethernet packet is received, the Ethernet MAC destination address is checked, and, if it does not pass the
address filter, the BD reflects that the packet is aborted. The MAC address check can be disabled using the
MAC_CHECK field of the CPRIn_ETH_CONFIG_1 register.
) On page 17-26, at the end of Section 17.3.1.5.3, replace the last paragraph with the following:
The size of the Ethernet buffers is indicated by the CPRInRETHBS register. If the size of an arrived Ethernet
packet is larger than the defined Ethernet buffer size, the current received packet is aborted and the ABORT bit is
set in the buffer descriptor. If the size of an arrived Ethernet packet is equal to the defined Ethernet buffer size, the
current received packet is accepted, but the ABORT bit is set in the buffer descriptor and the packet is aborted. If
start of packet has been already read by the DMA from the Framer, abort is indicated the next time the
CPRIn_ETH_RX_STATUS register is read; otherwise, the previously received part of the packet is just removed
without further notice. The CPRIn_ETH_RX_STATUS register indicates if a packet was aborted and the reason of
it (for example, CRC error, buffer overflow, and so forth).
Note: Always make sure that the Ethernet buffer size definition in the CPRInRETHBS register is larger than the
expected Ethernet packet size.
) Replace the first paragraph in Section 17.3.3.6 on page 17-36 with the following:
The CPRI Framer extracts the Ethernet packets from the CPRI frame and transfers them to an integrated Ethernet
MAC in the CPRI Framer. The MAC decodes the 4B5B Ethernet frame and checks the destination MAC address.
If the destination MAC address passes the address filter, the data is transferred to system memory via the MBus.
Otherwise, the Buffer Descriptor reflects an aborted packet.
) Replace the last paragraph in Section 17.3.3.6 on page 17-36, with the following:
Each Ethernet packet is stored in a different buffer in the system memory where the Ethernet data buffer location is
described by RDBP pointer field of CPRInRETHBD register. The size of the receive Ethernet buffers is indicated
by the CPRInRETHBS register. If the size of an arrived Ethernet packet is equal to or greater than the Ethernet
buffer size, the packet is aborted and the ABORT bit in the buffer descriptor is set. If a CRC error occurs, the CRC
error bit is set. Bit OV is set if overrun occurs.
Common Public Radio Interface (CPRI)
MSC8158E Reference Manual Addendum, Rev. 0
Freescale Semiconductor 13
) Replace the first paragraph in Section 17.3.3.7 on page 17-38, with the following:
The receive DMA can notify the cores each time that a packet is transferred to the system memory or after a
programmable number of packets are transferred to the system memory. The number of packets is determined by
the CPRInRETHCT register. The number of packets transferred is indicated by the coalescing counter status
register (CPRInRETHCS). In unicast and multicast MAC address filtering, an interrupt is generated not only when
a programmed number of packets are transferred to system memory, but also when part or all of the packets do not
fit the MAC filter. In this case, the BD of the packets reflects that the packet is aborted.
) Add the following to the end of Section 17.3.10 on page 17-56:
The REC master can send a reset request to the REC slave or RE through the CPRIn_HW_RESET register. The
REC slave cn send a reset acknowledge to the master, but this configuration has the following restraints:
If the REC slave is an end-point, it can generate the reset acknowledge.
If the REC slave is not an end-point (but between the REC master and the RE), it must be configured as a
master (to support the 10 ms chaining) and the reset request/ack must be managed outside the CPRI
protocol.
) In Section 17.4 on page 17-62, change the second sentence of the first paragraph to the following:
All the read and write accesses are executed through a 32-bit bus interface; reads and writes always access all the
bits of the register.
) Replace Section 17.4.1.2 on page 17-67 with the following:
17.4.1.2 CPRI Configuration (CPRIn_CONFIG)
address 0x8 (CPRIn_CONFIG)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R —
W
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R — RX_E
NABL
E
—
TX_ENA
BLE
—
SYNC_
MODE
TX_CTR
L_INSER
T_EN
W
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 17-36. CPRIn_CONFIG
Table 17-14. CPRIn_CONFIG Bit Descriptions
Name Reset Description Setting
—
31–9
0 Reserved. Write to zero for future compatibility.
RX_ENABLE
9
0 Receive Enable
Enables or disables receive operations.
0 Disable receive operations
1 Enable receive operations.
—
8–6
0 Reserved. Write to zero for future compatibility.
MSC8158E Reference Manual Addendum, Rev. 0
14 Freescale Semiconductor
Common Public Radio Interface (CPRI)
) Replace Section 17.4.1.6 on page 17-69 with the following:
17.4.1.6 CPRI Hardware Reset from Control Word (CPRIn_HW_RESET)
This register is used to control and monitor reset request or acknowledges mapped to bit 0 of
Z.130.0 CPRI control word. The register is used to transmit reset request to RE nodes.
A reset request can be sent by setting RESET_GEN_EN and RESET_GEN_FORCE signals. The
reset generation request will be hold as long as RESET_GEN_FORCE is asserted and until reset
acknowledge have been received from the RE. However reset generation request can always be
aborted by clearing the RESET_GEN_EN signal.
TX_ENABLE
5
0 Transmit Enable
Enables or disables transmit operations.
0 Disable transmit operations.
1 Enable transmit operations.
—
4–2
0 Reserved. Write to zero for future compatibility.
SYNC_
MODE
1
0 End Point Slave Mode
When this bit is cleared, the lane operates in Master
Mode. As a master, it can generate a reset request to the
Slave and receive a reset acknowledge. It uses the 10 ms
pulse generated by the Timer for transmission. When the
bit is set, the lane operates in Slave Mode, in which it can
receive a reset request from the Master and generate a
reset acknowledge. It uses the recovered 10 ms pulse for
transmission.
0Master Mode
1 Slave Mode
TX_CTRL_
INSERT_EN
0
0 CPRI Control Word Insertion l Enable
Transmit Control Word insertion enable.
0 Transmit control word insertion
disabled.
1 Transmit control word insertion
enabled,.
address 0x2C (CPRIn_HW_RESET)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R —
W
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R —
RESET_
GEN_D
ONE_H
OLD
RESET_
GEN_D
ONE
RESET_D
ETECT_H
OLD
RESET_
DETECT
—
RESET_
OUT_
EN
RESET_
GEN_F
ORCE
RESET_
GEN_E
N
W
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 17-40. CPRIn_HW_RESET
Table 17-18. CPRIn_HW_RESET Bit Descriptions
Name Reset Description Setting
—
31–8
0 Reserved. Write to zero for future compatibility.
Table 17-14. CPRIn_CONFIG Bit Descriptions
Name Reset Description Setting
Common Public Radio Interface (CPRI)
MSC8158E Reference Manual Addendum, Rev. 0
Freescale Semiconductor 15
) Replace the RETHBS row in Table 17-65 on page 17-104 with the following:
) In Table 17-19 on page 17-71, replace the TX_FAST_CM_PTR [5–0] row with the following:
RESET_
GEN_DONE_
HOLD
7
0 Hold Reset Done
This bit holds the Reset Generation Done value.
Note: This bit is sticky read-to-clear.
0 Reset generation not done.
1 Reset generation done.
RESET_
GEN_DONE
6
0 Reset Generation Done
Indicates whether the reset request or acknowledge is
done. Set when CPRI completes sending 10 consecutive
reset request or acknowledge indications
0 Reset request/ acknowledge is not
done.
1 Reset request/ acknowledge is
done.
RESET_
DETECT_
HOLD
5
0 Hold Reset Detected
This bit holds the Reset Detected value.
Note: This bit is sticky read-to-clear.
0 Reset request not detected.
1 Reset request detected.
RESET_
DETECT
4
0 Reset Detected
Indicates that a reset request/acknowledge was detected
on the CPRI RX side.
0 Reset request/acknowledge not
detected.
1 Reset request/acknowledge
detected.
—
3
0 Reserved. Write to zero for future compatibility.
RESET_OUT
_EN
2
0 Reset Indication Output Enable
Used to enable the reset output request.
0 Disable reset indication output
1 Enable reset indication output
RESET_
GEN_
FORCE
1
0 Forces Reset Request/Acknowledge
Setting this bit forces a reset request/acknowledge on the
CPRI TX side.
0 Disable reset request/acknowledge.
1 Force reset request/acknowledge.
RESET_
GEN_EN
0
0 Reset Request/Acknowledge Generation Enable
Setting this bit enables generation of a reset
request/acknowledge on the CPRI TX side via the
dedicated control word (Z.130.0).
0 Generation of reset
request/acknowledge disabled.
1 Generation of reset
request/acknowledge enabled.
RETHBS
15–0
0 Receive ETH Buffer Size
The RETHBS field is equal to the receive Ethernet buffer
size in bytes minus 1. The buffer size should be aligned to
16 bytes. (The 4 LSBs are always ones)
Note: Always make sure that the definition is larger
than the expected Ethernet packet size.
0x000F–0xFFBF
TX_FAST_
CM_PTR
5–0
0x24 Pointer to First CPRI Control Word
Contains the pointer to the first CPRI control word used for
fast Control and Management. This value is inserted into
the CPRI control byte Z.194.0.
Valid values: 0x14–0x35
Table 17-18. CPRIn_HW_RESET Bit Descriptions (Continued)
Name Reset Description Setting
MSC8158E Reference Manual Addendum, Rev. 0
16 Freescale Semiconductor
QUICC Engine Subsystem
) Add the following note before Table 17-106 on page 17-138:
Note: Occasionally, the number of received packets reported by the CPRI does not correspond to the number of
updated BDs. If the core detects this condition when reading the BDs, program the core to request a
retransmission of the missing packets.
) Replace the ABORT row in Table 17-127 on page 17-158 with the following:
7 QUICC Engine Subsystem
) Add the following before the first sentence on page 18-15:
18.6.1 UCC Functionality
)
Add the following after the end of Section 18.6 on page 18-15:
18.6.1 UCC Programming Restrictions
The following sections describe programming restrictions for the UCCs.
18.6.1.1 Tx Virtual FIFO
Due to the structure of the Tx Virtual FIFO, it is possible for the Tx Virtual FIFO to contain part of a frame when
there is no room for the remainder of the frame (that is, when the frame size is in the scale of magnitude of the Tx
Virtual FIFO size). If the Tx Virtual FIFO contains a partial frame, the transmission of the frame may start, even if
there are fewer bytes of data than defined by the UCC Tx Virtual FIFO Threshold (UTFTT) value in the Tx Virtual
FIFO. The only reason the frame might not begin to transmit is that it meets a specific sequence (which is rare, but
possible) in which the UCC transmit-start condition is not met for the frame. The erroneous behavior is a result of
incorrect recovery after the pausing data-retrieve phase from the BD buffer to the Tx Virtual FIFO in a certain
internal stage. Reaching the UTFTT watermark in the Tx Virtual FIFO for each transmit frame prevents this
sequence. UTFTT has an upper limit value that is less than the UCC Tx Virtual FIFO Size (UTFS) value. For each
UTFS value, there is a maximum UTFTT value that corresponds to it. Configuring UTFTT higher than the
suggested value can result in a UCC halt and Ethernet transmission stops.
Note: UTFTT refers to the payload of a single Ethernet frame. Transmission may start (this is the correct
behavior) before surpassing the threshold if there is no space for additional data in the Tx Virtual FIFO
The UCC may stop transmitting when a large frame is partially stored in the Tx Virtual FIFO before the
transmission of the frame starts. Note that the Tx BD ring buffer configuration (data allocation to the BD buffers)
may adversely affect Tx Virtual FIFO usage, thus preventing the Tx Virtual FIFO from reaching the threshold for
transmission in the Tx Virtual FIFO.
Use one of the following options to avoid this condition:
ABORT
16
0 Receive Packer Aborted
The receive packet is aborted due either to an error in the
packet or if the packet size is greater than or equal to the
Receive Ethernet Buffer Size (CPRInRETHBS).
Note: This bit is written by the receive DMA
0 Normal operation
1 Ethernet packet aborted.
QUICC Engine Subsystem
MSC8158E Reference Manual Addendum, Rev. 0
Freescale Semiconductor 17
1. To prevent the failure, configure UTFS and UTFTT so that it is possible to store UTFTT data (pay-
load) bytes in the Tx Virtual FIFO.
For a single buffer per frame, the maximum allowable UTFTT values are:
Ethernet Controller: Set UTFTT < [(0.9375 × UTFS) – 128]
For example, for an Ethernet controller with UTFS = 1024, set UTFTT < 832.
For multiple buffers per frame, the maximum allowable UTFTT values are:
Ethernet Controller: Set UTFTT < [(UTFS × (M – 8)/M –128]
For example, for an Ethernet controller with UTFS = 1024 and M = 64, set UTFFT < 768.
2. To recover from a possible failure, the application code should configure UTFTT to 0x40 and then
restore it to its original value. The sequence triggers transmission from the point at which it stopped.
Detection of such a UCC halt is done by monitoring Tx BD vacancy. A full Tx BD ring may indicate
that the UCC has halted.
18.6.1.2 Multi-Threading Configuration
The Ethernet receiver might become stuck while in a multi-threaded configuration in case of heavy traffic. This
condition is influenced by both the VFIFO size and the number of threads that are enabled.
Use at least one of the following measures to avoid the situation described above:
Enable only one Rx thread. The Rx VFIFO size should be equal to 0.5 Kbytes.
If the Rx VFIFO size is between 0.5 to 1.1 Kbytes, at least 4 threads must be enabled.
If the Rx VFIFO size is between 1.1 to 1.6 Kbytes, at least 6 threads must be enabled.
If the Rx VFIFO size is between 1.6 to 2.2 Kbytes, at least 8 threads must be enabled.
If the Rx VFIFO size is between 2.2 to 4.5 Kbytes, the user must allocate 512 bytes (must be initialized to
zero) in the Multiuser RAM. The base address for this area must be 512 bytes aligned. Immediately after
the Ethernet Rx INIT command is ended (and before the UCC receiver is enabled), this address (24 bits)
must be written to the Rx GPRAM in offsets 0x09–0x0b and 0x11–0x13. The user must write the value
0x3F to offsets 0x08 and 0x10. For example, if the base address for this new structure is 0x123400, the Rx
GPRAM[0x08–0x0b and 0x10–0x13] will be equal to 0x3F123400. Note: In this case, there is no
limitation to the number of threads that must be enabled.
) Add the following before Section 18.8 on page 18-23:
18.7.5 Ethernet Programming Restrictions
The Ethernet implementation in the MSC8158E has the programming restrictions defined in the following
sections.
18.7.5.1 RMON Statistics
Because there are a number of conditions that can cause the statistics to be inaccurate, do not use the TX CRC
counter values for statistics.
MSC8158E Reference Manual Addendum, Rev. 0
18 Freescale Semiconductor
QUICC Engine Subsystem
18.7.5.2 Unreported Overrun
An Overrun status for a received frame is a notification that is was not fully received because the Ethernet
controller is temporarily overloaded and that the frame should be discarded. In rare cases, such as when two
sequential frames that cause an Overrun are received, the second frame is discarded but not reported as causing an
overrun. The frame loss can be detected by a higher level protocol (such as TCP/IP). Make sure that the software
requests a retransmission of the frame if the higher level protocol reports a frame loss.
18.7.5.2 Broadcast Status after an In-Band CRS Event
In RGMII mode, the Ethernet can erroneously indicate a Broadcast status for the previous frame (wrong
RxBD[BC]) is generated after an in-band CRS event. To make sure a real broadcast event has occurred, program
the application to ignore the RxBD[BC] bit and check the Broadcast address instead.
18.7.5.4 Pause Frame End
A pause frame is used to restrict flow control when the Ethernet controller is being overloaded. To end the pause,
the application sends an XON receive pause frame with a Pause Time Value (PTV) = 0, which should cause the
transmitter to exit the pause frame immediately. However, in the MSC8158E, the controller decrements that
counter after clearing it before performing the compare to zero. As a result, the XON actually causes the transmitter
to continue in the pause state for 65535 pause quantas (3353920 bit-times). To prevent this occurrence, use a pause
frame with a PTV = 1 to force an exit from a pause state.
Note: In the case of connecting to another QUICC Engine device, the programmer may not use the QUICC
Engine Automatic Flow Control (AUFC) because in this mode, the Ethernet Controller generates Pause
Commands with Pause Time Value = 0 in order to exit pause state. The programmer must configure the
QUICC Engine block to use either of the following flow control modes:
— Lossless Flow Control: The Ethernet controller always uses the value of the UEMPR[PT] register
when generating pause frames. It never automatically generates a pause frame with a pause time value
of 0 when the receiver recovers from being above the RxFIFO threshold or below the free RxBDs
threshold.
— Host Enabled Flow Control: Use the following guidelines for the specified QUICC Engine commands:
• START FLOW CONTROL. Sends pause frames with the Pause Time Value in the UEMPR[PT]
field. The programmer may configure UEMPR[PT] for pause time and use the START FLOW
CONTROL command for sending pause frames For exiting pause state, the programmer may
configure UEMPR[PT] to 1 and use the START FLOW CONTROL command.
• STOP FLOW CONTROL. Sends a Pause Time Value of 0 and should be avoided.
18.7.5.5 Pause Frame Time
If a transmit is in progress, the pause time may be shorter than specified. When the Ethernet controller receives a
pause frame with PTV not equal to 0 and MACCFG1[Rx Flow] = 1, it completes transmitting any current frame in
progress; then it should pause for PTV × 512 bit-times. The MAC, however, does not take the full transmission
time of the current frame into account when calculating the Tx pause time, and it may pause for 1–2 pause quanta
(512–1024 bit-times) less than the PTV value. This can cause the Ethernet controller to pause transmission for up
to 1024 bit-times less than the pause frame request value. If the PTV does not contain at least 2 pause quanta worth
of margin, it may allow receive buffer overflows to occur in the link partner. Because the transmit pause does not
take effect until after the current frame completes transmitting, the link partner pause frame generator must already
QUICC Engine Subsystem
MSC8158E Reference Manual Addendum, Rev. 0
Freescale Semiconductor 19
include the maximum frame size as margin when calculating the pause time value to use to prevent overflow of the
receiver buffers. To prevent this condition, always add 2 pause quanta to the pause time value when generating
pause frames to prevent buffer overflow.
18.7.5.6 Transmit During Pause Frame
After receiving a PAUSE frame, the UCC Ethernet controller may transmit a frame although it has entered the
PAUSE state. As a consequence, the pause duration is shortened by the length of the transmitted frame. The
UCCS[BPR] and UCCE[CBPR] bits reflect the PAUSE state (A PAUSE frame with Pause Time Value of zero ends
the PAUSE state). A frame may be transmitted on the line during this PAUSE window. If this transmitted frame
does not consume the entire PAUSE window, the following frame is suspended until the pause duration is over and
only then it will be transmitted. If the short PAUSE frame can impact system performance, consider increasing the
PAUSE frame time. The increased Pause frame should large enough so that the minimum pause requirement is
always met. Make sure that by enlarging the PAUSE frame, all the PAUSEs are affected, not just the short ones.
18.7.5.7 Magic Packet Handling
The Ethernet MAC should recognize Magic Packet sequences by identifying an Ethernet frame containing a valid
Ethernet header (Destination and Source Addresses) and valid FCS (CRC-32), and whose payload includes the
specific Magic Packet byte sequence at any offset from the start of data payload. The specific byte sequence
comprises an unbroken stream of 102 bytes, the first 6 bytes of which are 0xFFs, followed by 16 copies of the
MACs unique IEEE station address in the normal byte order for Ethernet addresses.
The following are example partial sequences followed by the start of a complete sequence for station address
01_02_03_04_05_06:
FF_FF_FF_FF_FF_FF_FF_01_02_03_04_05_06_01...
Seventh byte of 0xFF does not match next expected byte of Magic Packet sequence (01). Pattern search
restarts looking for 6 bytes of FF at byte 01.
FF_FF_FF_FF_FF_FF_01_FF_FF_FF_FF_FF_FF_01_02_03_04_05_06_01...
First FF byte following 01 does not match Magic Packet sequence. Pattern search restarts looking for 6
bytes of FF at second byte of FF following 01.
The following is an example partial sequence followed by the start of a complete sequence which is erroneously
not recognized for station address 01_02_03_04_FF_06:
FF_FF_FF_FF_FF_FF_01_02_03_04_FF_FF_FF_FF_FF_FF_01_<complete sequence> 11th byte (0xFF)
is seen as the 11 byte of the partial pattern and is not recognized as the start of a complete sequence. Pattern
search restarts looking for 6 bytes of 0xFF at 12th byte, but sees only 5.
18.7.5.7.1 Failure to Exit Magic Packet Mode
If a complete Magic Packet sequence (including 6 byes of 0xFF) immediately follows a partial Magic Packet
sequence, however, the complete sequence is not recognized and the MAC does not exit Magic Packet mode.
To prevent this occurrence, place one byte of data that is not 0xFF and does not match any bytes of Destination
Address before the start of the Magic Packet sequence in the frame. Because the Magic Packet sequence pattern
search starts at the 3rd byte after Destination Address, the Magic Packet sequence can be placed at the start of the
data payload as long as the second byte of the length/type field follows the placement rule.
MSC8158E Reference Manual Addendum, Rev. 0
20 Freescale Semiconductor
Debugging, Profiling, and Performance Monitoring
18.7.5.7.2 Malformed Magic Packet Mode Triggers Exit
The following describes these scenarios:
1. Any Ethernet frame containing a valid Ethernet header (Destination and Source Addresses) and valid
FCS (CRC-32), and whose payload includes the specific Magic Packet byte sequence at any offset
from the start of data payload. The specific byte sequence comprises an unbroken stream of 102 bytes,
the first 6 bytes of which are 0xFFs, followed by 16 copies of the MACs unique IEEE station address
in the normal byte order for Ethernet addresses.
2. Once the Ethernet MAC has recognized a valid Destination Address for one frame, it continues search-
ing for valid 102-byte Magic Packet sequences through multiple frames without checking for a valid
Destination Address on each frame. The only events that cause the MAC to go back to check for valid
Destination Address before checking for a Magic Packet sequence on new frames are:
— A frame containing a recognized full Magic Packet sequence (with valid or invalid FCS)
— Software disable of Magic packet mode (MACCFG2[MPE] = 0)
— Perform soft reset via MACCFG1[Rx_EN] and MACCFG1[Tx_EN].
3. The Ethernet controller may exit Magic Packet mode if it receives a frame with Destination Address
not matching station address, or invalid unicast or broadcast address in a valid Magic Packet sequence
for the device.
If an erroneous recognition of a Magic Packet can affect system functionality, avoid the use of Magic Packets.
18.7.5.8 Ethernet Transmit Scheduler
If the data in the buffer is all 00s (bmax) or FFs (bmin), it results in an incorrect offset/address result, causing the
Ethernet scheduler to select an arbitrary queue. To avoid incorrect behavior of the Ethernet Tx scheduler (including
a possible stuck condition), always us all even values for the Weight Factor in the scheduling parameters.
8 Debugging, Profiling, and Performance Monitoring
) Replace the second paragraph of Section 24.2.8.2 on page 24-25 with the following:
All serial interfaces (SGMII, Serial RapidIO, PCI Express, and CPRI) support digital loopback mode. See Section
15.10.59 for details.
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