LXD381 — Evaluation Board for
Octal E1 Applications
Developer Manual
January 2001
As of January 15, 2001, this document replaces the Level One document Order Number: 249213-001
LXD381 — Evaluation Board for Octal E1 Applications User Guide.
LXD381 — Evaluation Board for Octal E1 Applications Developer Manual
Information in this document is provided in connection with Intel
®
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Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The LXD381 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current
characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
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Copyright © Intel Corporation, 2001
*Third-party brands and names are the property of their respective owners.
LXD381 — Evaluation Board for Octal E1 Applications Developer Manual iii
Contents
1.0 General Description ..................................................................................................5
1.1 Features ................................................................................................................5
2.0 Evaluation Board Set-Up.........................................................................................7
2.1 LXD381 Packing List.............................................................................................7
2.2 Equipment Requirements......................................................................................7
2.3 Power Connections ...............................................................................................7
2.4 Loopback Mode Selection .....................................................................................7
2.5 Receive Polarity Selection.....................................................................................8
2.6 Output Enable Selection........................................................................................8
2.7 Unused Switches...................................................................................................8
2.8 Back-End Interface Connection.............................................................................8
2.9 Line Interface Connection .....................................................................................9
2.10 Line Interface Circuit .............................................................................................9
2.11 Board Protection....................................................................................................9
3.0 Evaluation Board Schematics.............................................................................10
Figures
1 LXD381 Evaluation Board .....................................................................................6
2 S2 Factory Switch Settings ...................................................................................8
3 Typical Back-End Connector.................................................................................9
4 Evaluation Board Schematic — Data/Control .....................................................10
5 Evaluation Board Schematic — Digital I/O..........................................................11
6 Evaluation Board Schematic — Analog 1 ...........................................................12
7 Evaluation Board Schematic — Analog 2 ...........................................................13
Tables
1 LOOP0 - 7 Switch Settings....................................................................................7
Evaluation Board for Octal E1 Applications — LXD381
Developer Manual 5
1.0 General Description
The LXD381 evaluation board is a versatile tool for engineers designing E1 short haul applications
using the LXT381.
The evaluation board operates in Hardware mode only. All device and channel controls are set
using jumper blocks and DIP switches.
The board provides banana jacks for both power and line interface connections. Connectors are
provided for each framer or back-end ASIC interface. An E1 pattern generator/analyzer may be
used to provide external signals for evaluation.
1.1 Features
• Hardware controllable
• ZIF LQFP socket for easy swapping of LXT381
• Banana jacks for power and line interfaces
• 10-pin connectors for framer/ASIC interface
• Socketed termination components for easy experimentation
• Built-in overvoltage protection for line interface and power supply
LXD381 — Evaluation Board for Octal E1 Applications
6 Developer Manual
Figure 1. LXD381 Evaluation Board
Evaluation Board for Octal E1 Applications — LXD381
Developer Manual 7
2.0 Evaluation Board Set-Up
Caution: CMOS devices are static (ESD) sensitive. Take all industry standard precautions when handling the
evaluation board, the LXT381 chip and other sensitive electronic components.
Before proceeding with any evaluation board operations, review the specifications for the LXT381
transceiver.
2.1 LXD381 Packing List
The evaluation board kit contains the following components:
• LXD381 board with LXT381 device installed.
• LXD381 User Guide.
• LXT381 Data Sheet.
2.2 Equipment Requirements
The evaluation board kit includes all the circuit components needed for a successful evaluation.
However, the following lab equipment is required:
• Power Supply (+3.3 VDC).
• Telecom cable or cable simulator (optional).
• E1 pattern generator/analyzer
2.3 Power Connections
The evaluation board has two power planes (VCC and TVCC) each of which is tied to a separate
red colored banana jack. Connect the +3.3 VDC power supply to both the VCC (B1) and TVCC
(B3) banana jacks. Connect the power supply ground lead to the black banana jack (B2).
2.4 Loopback Mode Selection
The LXT381 LOOP signals for channels 0 through 7 are set by the switches in switch block S1. As
shown in Table 1, these switches have three positions to select Remote Loopback, Analog
Loopback or No Loopback.
Table 1. LOOP0 - 7 Switch Settings
S1 Switch Position Operation
High Analog Loopback
Center No Loopback
Low Remote Loopback
LXD381 — Evaluation Board for Octal E1 Applications
8 Developer Manual
2.5 Receive Polarity Selection
The polarity of RPOS/RNEG is determined by the CLKE switch in switch block S2. When the
CLKE switch is OFF, RPOS/RNEG are active Low. When set to the ON position, RPOS/RNEG
are active High. Note that the CLKE switch controls the LXT381’s RPOL pin.
2.6 Output Enable Selection
The OE switch in switch block S3 controls the operation of the LXT381 output drivers. For normal
operation (driver outputs enabled), set the OE switch to the ON position. Setting the OE switch to
OFF forces the output drivers to the high impedance state.
2.7 Unused Switches
Switches 3 and 4, in switch block S2, have no function on the LXD381 and should be set to the
OFF position. Figure 2 shows the factory default settings for switch block S2.
2.8 Back-End Interface Connection
Eight 10 pin connectors (JP1 - JP8) provide access to the LXT381 digital signals to allow
interfacing the back-end Framer/Mapper or ASIC with an external pattern generator. Figure 3
shows a typical connector (JP1 for channel 0) with the factory installed jumper connecting RCLK
to TCLK. This jumper is normally installed when feeding analog test data from the line interface
(TIP and RING).
Figure 2. S2 Factory Switch Settings
1 2 3 4
O
F
F
CLKE
OE
S2
NOTE: OFF position = Low
Evaluation Board for Octal E1 Applications — LXD381
Developer Manual 9
2.9 Line Interface Connection
Access to the line interface is provided through the green and white banana jacks. The TIP signal is
routed to the white jacks for both transmit and receive directions. The RING signal is routed to the
green jacks for both directions.
2.10 Line Interface Circuit
Two octal transformers are used for channels 0 to 3 and 4 to 7. Transformers, resistors and
capacitors for channels 0 and 4 are socketed for easy swapping (see the LXT381 data sheet for line
interface information). Jumper blocks are provided to configure the receive transformer operation
for 1:1 or 1:2 turns ratio (see “Evaluation Board Schematics” on page 10). Factory installed
jumpers configure the transformers for a 1:1 ratio.
2.11 Board Protection
The evaluation board provides line surge protection for both the power supply and the line. Two
transient voltage suppressors (TVS) are included for power supply protection. The E1 line interface
transmitters are protected with Schottky diodes and the receivers are protected by series input
resistors. This protection is sufficient for G.703 Annex B compliance.
Figure 3. Typical Back-End Connector
12
34
56
78
GND
RCLK 0
RPOS 0
RNEG 0
TCLK 0
TCLK 0
TPOS 0
TNEG 0
JP1
9
10
GNDLOS 0
LXD381 — Evaluation Board for Octal E1 Applications
10 Developer Manual
3.0 Evaluation Board Schematics
Figure 4. Evaluation Board Schematic — Data/Control
VCC
VCC
TVCC
VCC
VCC
VCC
VCC
LOS0
LOS1
LOS2
LOS3
LOS4
LOS5
LOS6
LOS7
RN1_7
RN1_8
RN1_9
RN1_6
RN1_2
RN1_7
RN1_4
RN1_3
RN1_1
RN2_8
RN2_9
RN2_9
CLKE
RN2_8
OE
RN1_1
RN1_2
RN1_3
RN1_4
RN1_6
CLKE
OE
S3_9
S3_9
RN2_1
RN2_2
RN2_2
RN1_9
RN1_8
RN2_1
C1 0.1uF
C3 0.1uF
C2 0.1uF
BN3
RED
1
C7
68 uF
C8
.01uf
C6
.01uf
C5
68 uF
BN1
RED
1
BN2
BLACK
1
C4 0.1uF
+
-
S3
TriState9
118
2
10
3
4
5
6
7
8
9
R1
4.7K
RN1
R.NETWORK 4.7K
10
2
1
3
4
6
7
8
9
5
CM1
R2
R1
R3
R4
R5
R6
R7
R8
CM2
S2
SW DIP-4
1
2
3
4
8
7
6
5
RN2
R.NETWORK 4.7K
10
2
1
3
4
6
7
8
9
5
CM1
R2
R1
R3
R4
R5
R6
R7
R8
CM2
D2
TVS 3.3V
D1
TVS 5V
U1A
BOPx
10
11
115
43
88
84
85
86
87
114
21
22
23
24
25
26
27
28
97
42
35
75
68
113
106
3
140
94
12
20
18
89
91
19
17
90
92
13
14
15
16
RPD
MODE
CLKE
GND
GND
GND
GND
GND
GND
OE
LOOP0/D0
LOOP1/D1
LOOP2/D2
LOOP3/D3
LOOP4/D4
LOOP5/D5
LOOP6/D6
LOOP7/D7
GND
LOS0
LOS1
LOS2
LOS3
LOS4
LOS5
LOS6
LOS7
GND
GND
GND0
GNDIO0
GND1
GNDIO1
VCC0
VCCIO0
VCC1
VCCIO1
GND
GND
GND
GND
+
BANANA JACK
3.3 VOLTS
TVCC
BANANA JACK
+
-
GROUND
JA CONTROL
Evaluation Board for Octal E1 Applications — LXD381
Developer Manual 11
Figure 5. Evaluation Board Schematic — Digital I/O
RNEG1/BPV1
RPOS1/RDATA1
RCLK1
RNEG0/BPV0
RPOS0/RDATA0
RCLK0
TCLK1
TPOS1/TDATA1
TCLK2
RCLK3
RNEG2/BPV2
TPOS3/TDATA3
RNEG3/BPV3
TPOS2/TDATA2
RCLK2
RPOS2/RDATA2
TCLK3
RPOS3/RDATA3
TPOS4/TDATA4
TCLK4
RCLK4
RPOS4/RDATA4
RNEG4/BPV4
RNEG5/BPV5
RPOS5/RDATA5
RCLK5
TCLK5
TPOS5/TDATA5
TPOS6/TDATA6
TPOS7/TDATA7
RCLK6
RPOS6/RDATA6
RNEG6/BPV6
RCLK7
RPOS7/RDATA7
RNEG7/BPV7
TCLK7
TCLK6
TNEG0/UBS0
TNEG1/UBS1
TNEG2/UBS2
TNEG3/UBS3
TNEG4/UBS4
TNEG5/UBS5
TNEG6/UBS6
TNEG7/UBS7
TCLK0
TPOS0/TDATA0
LOS0
LOS1
LOS2
LOS3
LOS5
LOS7
LOS6
LOS4
TCLK7
TCLK5
TCLK4
TCLK6
TCLK1
TCLK2
TCLK3
TCLK0
TPOS0/TDATA0
TPOS4/TDATA4
TPOS2/TDATA2
TPOS3/TDATA3
TPOS1/TDATA1
TPOS7/TDATA7
TPOS6/TDATA6
TPOS5/TDATA5
TNEG1/UBS1
TNEG2/UBS2
TNEG5/UBS5
TNEG7/UBS7
TNEG4/UBS4
TNEG3/UBS3
TNEG0/UBS0
TNEG6/UBS6
JP3
HEADER 5X2
12
34
56
78
910
JP1
HEADER 5X2
12
34
56
78
910
JP5
HEADER 5X2
12
34
56
78
910
JP7
HEADER 5X2
12
34
56
78
910
JP2
HEADER 5X2
12
34
56
78
910
JP4
HEADER 5X2
12
34
56
78
910
JP6
HEADER 5X2
12
34
56
78
910
JP8
HEADER 5X2
12
34
56
78
910
RN3
R.NETWORK 100K
10
2
1
3
4
6
7
8
9
5
CM1
R2
R1
R3
R4
R5
R6
R7
R8
CM2
RN4
R.NETWORK 100K
10
2
1
3
4
6
7
8
9
5
CM1
R2
R1
R3
R4
R5
R6
R7
R8
CM2
RN5
R.NETWORK 100K
10
2
1
3
4
6
7
8
9
5
CM1
R2
R1
R3
R4
R5
R6
R7
R8
CM2
CHANNEL 1
CHANNEL 0
CHANNEL 2
CHANNEL 3
CHANNEL 4
CHANNEL 5
CHANNEL 6
CHANNEL 7
LXD381 — Evaluation Board for Octal E1 Applications
12 Developer Manual
Figure 6. Evaluation Board Schematic — Analog 1
TVCC
TVCC
TVCC
TVCC
TVCC
TVCC
TVCC
TVCC
RTIP1
TRING1
RRING1
TTIP1
TTIP0
TRING0
RTIP0
RRING0
RTIP3
RTIP2
TRING2
TTIP3
RRING2
TRING3
RRING3
TTIP2
TTIP1x
TRING1x
RRING1x
RTIP1x
RTIP0x
TRING0x
TTIP0x
RRING0x
TRING2x
TTIP3x
RTIP3x
RTIP2x
RRING3x
TTIP2x
TRING3x
RRING2x
R21
1K
C30
560pF
C26
0.22uF
R20
60
R17
1K
B15
GREEN
1
B16
WHITE
1
R25
11
B13
WHITE
1
B11
GREEN
1
R19
60
R23
11
T1B
TG-49-1505-NX
10
9
6
7
8
33
32
35
34
31
JP16
3
2
1
JP20
JP18
C29 ?pF
JP10
3
2
1
C20
0.22uF
JP12
B4
WHITE
1
B8
WHITE
1
R9
1K
B6
GREEN
1
R5
60
R13
11
C22 ?pF
JP14
T1A
TG-49-1505-NX
4
5
3
2
1
36
37
39
40
38
R11
11
R7
60
C24
560pF
B2
GREEN
1
R3
1K
D13
D18
D4
D6
R14
1K
D17
C21 ?pF
T1D
TG-49-1505-NX
20
19
16
17
18
23
22
25
24
21
B12
GREEN
1
C23
560pF
D14
B14
WHITE
1
R10
11
B1
GREEN
1
B7
WHITE
1
D12
B9
GREEN
1
D10
JP9
3
2
1
JP13
JP19
D15
D16
R2
1K
JP11
R16
60
D3
B5
GREEN
1
B3
WHITE
1
C28
560pF
JP15
3
2
1
C19
0.22uF
C27 ?pF
R8
1K
D9
JP17
T1C
TG-49-1505-NX
15
14
11
12
13
28
27
30
29
26
R4
60
D5
R18
1K
R22
11
R15
60
D8
C25
0.22uF
R6
60
R24
11
R12
11
D7
D11
B10
WHITE
1
Evaluation Board for Octal E1 Applications — LXD381
Developer Manual 13
Figure 7. Evaluation Board Schematic — Analog 2
TVCC
TVCC
TVCC
TVCC
TVCC
TVCC
TVCC
TVCC
RRING5
RTIP5
TRING5
TTIP5
RTIP6
RRING6
TTIP6
TRING6
RRING7
RTIP7
TRING7
TTIP7
TTIP4
TRING4
RTIP4
RRING4
RRING6x
TTIP6x
TRING6x
TTIP7x
TRING7x
RRING7x
TRING5x
RRING5x
TTIP5x
RTIP5x
RTIP7x
RTIP6xRTIP4x
TRING4x
RRING4x
TTIP4x
C36
560pF
R29
60
R35
11
R31
60
R27
1K
R33
1K
R37
11
R48
11
R39
60
R38
1K
R42
1K
C40
560pF
C37
0.22uF
R40
60
R46
11
R43
60
R49
11
C42
560pF
R47
11
R44
60
R41
1K
R45
1K
B32
WHITE
1
B31
GREEN
1
B29
WHITE
1
B27
GREEN
1
B30
WHITE
1
B24
WHITE
1
B26
WHITE
1
B18
GREEN
1
B20
WHITE
1
B22
GREEN
1
B28
GREEN
1
B25
GREEN
1
T2C
TG-49-1505-NX
15
14
11
12
13
28
27
30
29
26
T2D
TG-49-1505-NX
20
19
16
17
18
23
22
25
24
21
T2B
TG-49-1505-NX
10
9
6
7
8
33
32
35
34
31
JP28
3
2
1
JP27
3
2
1
JP22
3
2
1
JP26
JP31
JP32
JP30
JP29
JP24
C39 ?pF
C41 ?pF
C34 ?pF
C38
0.22uF
C32
0.22uF
R28
60
R36
11
R34
11
C35
560pF
B17
GREEN
1
JP23
C31
0.22uF
JP21
3
2
1
B19
WHITE
1
R32
1K
R30
60
JP25
B21
GREEN
1
B23
WHITE
1
R26
1K
T2A
TG-49-1505-NX
4
5
3
2
1
36
37
39
40
38
C33 ?pF
D24
D22
D32
D20
D26
D27
D28
D31
D34
D29
D30
D33
D19
D23
D25
D21
/
