Artemis Development Kit Reference guide

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Reference guide

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Freescale Semiconductor, Inc.
Reference Manual
Document Number: KL26P121M48SF4RM
Rev. 3.3, 4/2015
KL26 Sub-Family Reference Manual
with Addendum
© Freescale Semiconductor, Inc., 2015. All rights reserved.
Rev. 3.3 of the KL26 Sub-Family Reference Manual has two parts:
The addendum to revision 3.2 of the reference manual, immediately following this cover page.
Revision 3.2 of the reference manual, following the addendum.
Freescale Semiconductor, Inc.
Reference Manual Addendum
Document Number: KL26P121M48SF4RMAD
Rev. 0, 4/2015
Addendum to Rev. 3.2 of the KL26
Sub-Family Reference Manual
© Freescale Semiconductor, Inc., 2015. All rights reserved.
This addendum lists changes to revision 3.2 of the KL26 sub-family reference manual.
1 Add a 36-pin WLCSP package offering with the part
number: MKL26Z128CAL4R
The signal multiplexing and pin assignments for the MKL26Z128CAL4R are:
Location:
Section 10.3.1, Page 180
Section 10.3.2, Page 185
36
WLCSP
Pin Name DEFAULT ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7
A6 PTE0 DISABLED PTE0 SPI1_MIS
O
UART1_TX RTC_CLK
OUT
CMP0_OU
T
I2C1_SDA
C3 VSS VSS VSS
C4 USB0_DP USB0_DP
C5 USB0_DM USB0_DM
C6 VOUT33 VOUT33
D4 VREGIN VREGIN
D5 PTE16 ADC0_DP
1/ADC0_S
E1
ADC0_DP
1/ADC0_S
E1
PTE16 SPI0_PCS
0
UART2_TX TPM_CLKI
N0
D6 PTE17 ADC0_DM
1/ADC0_S
E5a
ADC0_DM
1/ADC0_S
E5a
PTE17 SPI0_SCK UART2_R
X
TPM_CLKI
N1
LPTMR0_
ALT3
D3 PTE18 ADC0_DP
2/ADC0_S
E2
ADC0_DP
2/ADC0_S
E2
PTE18 SPI0_MOS
I
I2C0_SDA SPI0_MIS
O
Add a 36-pin WLCSP package offering with the part number: MKL26Z128CAL4R
Addendum Rev. 0 to the KL26 Sub-Family Reference Manual, Rev. 3.2
Freescale, Inc. 3
D2 PTE19 ADC0_DM
2/ADC0_S
E6a
ADC0_DM
2/ADC0_S
E6a
PTE19 SPI0_MIS
O
I2C0_SCL SPI0_MOS
I
E6 VDDA/
VREFH
VDDA/
VREFH
VDDA/
VREFH
F6 VSSA/
VREFL
VSSA/
VREFL
VSSA/
VREFL
E5 PTE30 DAC0_OU
T/ADC0_S
E23/CMP0
_IN4
DAC0_OU
T/ADC0_S
E23/CMP0
_IN4
PTE30 TPM0_CH
3
TPM_CLKI
N1
F5 PTA0 SWD_CLK TSI0_CH1 PTA0 TPM0_CH
5
SWD_CLK
E4 PTA1 DISABLED TSI0_CH2 PTA1 UART0_R
X
TPM2_CH
0
F4 PTA2 DISABLED TSI0_CH3 PTA2 UART0_TX TPM2_CH
1
E3 PTA3 SWD_DIO TSI0_CH4 PTA3 I2C1_SCL TPM0_CH
0
SWD_DIO
F3 PTA4 NMI_b TSI0_CH5 PTA4 I2C1_SDA TPM0_CH
1
NMI_b
F2 VDD VDD VDD
E2 VSS VSS VSS
F1 PTA18 EXTAL0 EXTAL0 PTA18 UART1_R
X
TPM_CLKI
N0
E1 PTA19 XTAL0 XTAL0 PTA19 UART1_TX TPM_CLKI
N1
LPTMR0_
ALT1
D1 PTA20 RESET_b PTA20 RESET_b
C2 PTB0/LLW
U_P5
ADC0_SE8
/TSI0_CH0
ADC0_SE8
/TSI0_CH0
PTB0/LLW
U_P5
I2C0_SCL TPM1_CH
0
C1 PTB1 ADC0_SE9
/TSI0_CH6
ADC0_SE9
/TSI0_CH6
PTB1 I2C0_SDA TPM1_CH
1
B1 PTC1/LLW
U_P6/RTC
_CLKIN
ADC0_SE1
5/TSI0_CH
14
ADC0_SE1
5/TSI0_CH
14
PTC1/LLW
U_P6/RTC
_CLKIN
I2C1_SCL TPM0_CH
0
I2S0_TXD
0
B2 PTC2 ADC0_SE1
1/TSI0_CH
15
ADC0_SE1
1/TSI0_CH
15
PTC2 I2C1_SDA TPM0_CH
1
I2S0_TX_F
S
B3 PTC3/LLW
U_P7
DISABLED PTC3/LLW
U_P7
UART1_R
X
TPM0_CH
2
CLKOUT I2S0_TX_B
CLK
A1 PTC4/LLW
U_P8
DISABLED PTC4/LLW
U_P8
SPI0_PCS
0
UART1_TX TPM0_CH
3
I2S0_MCL
K
36
WLCSP
Pin NameDEFAULTALT0ALT1ALT2ALT3ALT4ALT5ALT6ALT7
Addendum Rev. 0 to the KL26 Sub-Family Reference Manual, Rev. 3.2
Add a 36-pin WLCSP package offering with the part number: MKL26Z128CAL4R
Freescale, Inc. 4
Below is the KL26 36-pin WLCSP pinout diagram:
B4 PTC5/LLW
U_P9
DISABLED PTC5/LLW
U_P9
SPI0_SCK LPTMR0_
ALT2
I2S0_RXD
0
CMP0_OU
T
A2 PTC6/LLW
U_P10
CMP0_IN0 CMP0_IN0 PTC6/LLW
U_P10
SPI0_MOS
I
EXTRG_IN I2S0_RX_
BCLK
SPI0_MIS
O
I2S0_MCL
K
A3 PTC7 CMP0_IN1 CMP0_IN1 PTC7 SPI0_MIS
O
audioUSB_
SOF_OUT
I2S0_RX_
FS
SPI0_MOS
I
A4 PTD4/LLW
U_P14
DISABLED PTD4/LLW
U_P14
SPI1_PCS
0
UART2_R
X
TPM0_CH
4
A5 PTD5 ADC0_SE6
b
ADC0_SE6
b
PTD5 SPI1_SCK UART2_TX TPM0_CH
5
B5 PTD6/LLW
U_P15
ADC0_SE7
b
ADC0_SE7
b
PTD6/LLW
U_P15
SPI1_MOS
I
UART0_R
X
SPI1_MIS
O
B6 PTD7 DISABLED PTD7 SPI1_MIS
O
UART0_TX SPI1_MOS
I
36
WLCSP
Pin NameDEFAULTALT0ALT1ALT2ALT3ALT4ALT5ALT6ALT7
$
37&
//:8B3
%
37&
//:8B3
57&B&/.,1
&
37%
'
37$
(
37$
)
37$
37&
//:8B3
37&
37%
//:8B3
37(
966
9''
37&
37&
//:8B3
966
37(
37$
37$
37'
//:8B3
37&
//:8B3
86%B'3
95(*,1
37$
37$
37'
37'
//:8B3
86%B'0
37(
37(
37$
$
37(
%
37'
&
9287
'
37(
(
9''$
95()+
)
966$
95()/
Add an MCG block diagram for the missing figure
Addendum Rev. 0 to the KL26 Sub-Family Reference Manual, Rev. 3.2
Freescale, Inc. 5
2 Add an MCG block diagram for the missing figure
Add the following figure for Figure 24-1, “Multipurpose Clock Generator (MCG) block diagram.”
Location: Section 24.1.1, Page 389
MCGOUTCLK
MCGIRCLK
MCGFFCLK
DCOOUT
/(24,25,26,...,55)
Phase
Detector
Charge
Pump
Internal
Filter
VCO
VCOOUT
PLL
Multipurpose Clock Generator (MCG)
VDIV0
Lock
Clock
Monitor
IRCLKEN
CME0
PLLS
LOLS0 LOCK0
Detector
/ 2
5
IREFST
FLL
DMX32
MCGFLLCLK
Crystal Oscillator
FRDIV
n=0-7
/ 2
n
Internal
Reference
Slow Clock
Fast Clock
Clock
Generator
PRDIV0
LOLIE0
Sync
Auto Trim Machine
IRCST
PLLST
CLKST
AT M S
SCTRIM
SCFTRIM
FCTRIM
ATMST
IREFSTEN
OSCINIT0
EREFS0
HGO0
RANGE0
External
DRS
Clock
Valid
Peripheral BUSCLK
PLLCLKEN0
IRCSCLK
IRCS
CLKSCLKS
DCO
LP
Filter
/(1,2,3,4,5....,25)
IREFS
STOP
CLKS
PLLCLKEN0
IREFS
PLLS
MCG Crystal Oscillator
Enable Detect
External Reference Clock
n=0-7
/ 2
n
FLTPRSRV
LOCRE0
LOCS0
MCGPLLCLK
KL26 Sub-Family Reference Manual
Supports: MKL26Z32VFM4, MKL26Z64VFM4, MKL26Z128VFM4,
MKL26Z32VFT4, MKL26Z64VFT4, MKL26Z128VFT4,
MKL26Z32VLH4, MKL26Z64VLH4, MKL26Z128VLH4,
MKL26Z256VLH4, MKL26Z256VMP4, MKL26Z128VLL4,
MKL26Z256VLL4, MKL26Z128VMC4, MKL26Z256VMC4
Document Number: KL26P121M48SF4RM
Rev. 3.2, October 2013
KL26 Sub-Family Reference Manual, Rev. 3.2, October 2013
2 Freescale Semiconductor, Inc.
Contents
Section number Title Page
Chapter 1
About This Information
1.1 Overview.......................................................................................................................................................................35
1.1.1 Purpose.........................................................................................................................................................35
1.1.2 Audience......................................................................................................................................................35
1.2 Conventions..................................................................................................................................................................35
1.2.1 Numbering systems......................................................................................................................................35
1.2.2 Typographic notation...................................................................................................................................36
1.2.3 Special terms................................................................................................................................................36
Chapter 2
Introduction
2.1 Overview.......................................................................................................................................................................39
2.1.1 Kinetis L series.............................................................................................................................................39
2.1.2 KL26 sub-family introduction.....................................................................................................................42
2.2 Module functional categories........................................................................................................................................43
2.2.1 ARM Cortex-M0+ core modules.................................................................................................................44
2.2.2 System modules...........................................................................................................................................45
2.2.3 Memories and memory interfaces................................................................................................................45
2.2.4 Clocks...........................................................................................................................................................46
2.2.5 Security and integrity modules....................................................................................................................46
2.2.6 Analog modules...........................................................................................................................................46
2.2.7 Timer modules.............................................................................................................................................47
2.2.8 Communication interfaces...........................................................................................................................47
2.2.9 Human-machine interfaces..........................................................................................................................48
2.3 Orderable part numbers.................................................................................................................................................48
Chapter 3
Chip Configuration
3.1 Introduction...................................................................................................................................................................51
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Freescale Semiconductor, Inc. 3
Section number Title Page
3.2 Module to module interconnects...................................................................................................................................51
3.2.1 Interconnection overview.............................................................................................................................51
3.2.2 Analog reference options.............................................................................................................................53
3.3 Core modules................................................................................................................................................................54
3.3.1 ARM Cortex-M0+ core configuration.........................................................................................................54
3.3.2 Nested vectored interrupt controller (NVIC) configuration.........................................................................57
3.3.3 Asynchronous wake-up interrupt controller (AWIC) configuration............................................................61
3.4 System modules............................................................................................................................................................62
3.4.1 SIM configuration........................................................................................................................................62
3.4.2 System mode controller (SMC) configuration.............................................................................................63
3.4.3 PMC configuration.......................................................................................................................................64
3.4.4 Low-Leakage Wake-up Unit (LLWU) Configuration.................................................................................65
3.4.5 MCM configuration.....................................................................................................................................66
3.4.6 Crossbar-light switch configuration.............................................................................................................67
3.4.7 Peripheral bridge configuration...................................................................................................................69
3.4.8 DMA request multiplexer configuration......................................................................................................70
3.4.9 DMA Controller Configuration...................................................................................................................72
3.4.10 Computer operating properly (COP) watchdog configuration....................................................................73
3.5 Clock modules..............................................................................................................................................................76
3.5.1 MCG configuration......................................................................................................................................76
3.5.2 OSC configuration.......................................................................................................................................77
3.6 Memories and memory interfaces.................................................................................................................................77
3.6.1 Flash memory configuration........................................................................................................................78
3.6.2 Flash memory controller configuration........................................................................................................81
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4 Freescale Semiconductor, Inc.
Section number Title Page
3.6.3 SRAM configuration....................................................................................................................................81
3.6.4 System Register File Configuration.............................................................................................................84
3.7 Analog...........................................................................................................................................................................84
3.7.1 16-bit SAR ADC configuration...................................................................................................................85
3.7.2 CMP configuration.......................................................................................................................................88
3.7.3 12-bit DAC configuration............................................................................................................................90
3.8 Timers...........................................................................................................................................................................92
3.8.1 Timer/PWM module configuration..............................................................................................................92
3.8.2 PIT Configuration........................................................................................................................................94
3.8.3 Low-power timer configuration...................................................................................................................96
3.8.4 RTC configuration.......................................................................................................................................98
3.9 Communication interfaces............................................................................................................................................99
3.9.1 Universal Serial Bus (USB) FS Subsystem.................................................................................................99
3.9.2 SPI configuration.........................................................................................................................................103
3.9.3 I2C configuration.........................................................................................................................................104
3.9.4 UART configuration....................................................................................................................................106
3.9.5 I2S configuration..........................................................................................................................................107
3.10 Human-machine interfaces (HMI)................................................................................................................................110
3.10.1 GPIO configuration......................................................................................................................................110
3.10.2 TSI configuration.........................................................................................................................................113
Chapter 4
Memory Map
4.1 Introduction...................................................................................................................................................................115
4.2 System memory map.....................................................................................................................................................115
4.3 Flash memory map........................................................................................................................................................116
4.3.1 Alternate non-volatile IRC user trim description.........................................................................................117
4.4 SRAM memory map.....................................................................................................................................................117
4.5 Bit Manipulation Engine...............................................................................................................................................117
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Freescale Semiconductor, Inc. 5
Section number Title Page
4.6 Peripheral bridge (AIPS-Lite) memory map.................................................................................................................118
4.6.1 Read-after-write sequence and required serialization of memory operations..............................................118
4.6.2 Peripheral bridge (AIPS-Lite) memory map................................................................................................119
4.6.3 Modules restricted access in user mode.......................................................................................................122
4.7 Private Peripheral Bus (PPB) memory map..................................................................................................................123
Chapter 5
Clock Distribution
5.1 Introduction...................................................................................................................................................................125
5.2 Programming model......................................................................................................................................................125
5.3 High-level device clocking diagram.............................................................................................................................125
5.4 Clock definitions...........................................................................................................................................................126
5.4.1 Device clock summary.................................................................................................................................127
5.5 Internal clocking requirements.....................................................................................................................................129
5.5.1 Clock divider values after reset....................................................................................................................130
5.5.2 VLPR mode clocking...................................................................................................................................130
5.6 Clock gating..................................................................................................................................................................131
5.7 Module clocks...............................................................................................................................................................131
5.7.1 PMC 1-kHz LPO clock................................................................................................................................133
5.7.2 COP clocking...............................................................................................................................................133
5.7.3 RTC clocking...............................................................................................................................................133
5.7.4 LPTMR clocking..........................................................................................................................................134
5.7.5 TPM clocking...............................................................................................................................................134
5.7.6 USB FS OTG Controller clocking...............................................................................................................135
5.7.7 SPI clocking.................................................................................................................................................135
5.7.8 I2C clocking.................................................................................................................................................136
5.7.9 UART clocking............................................................................................................................................136
5.7.10 I2S/SAI clocking..........................................................................................................................................136
KL26 Sub-Family Reference Manual, Rev. 3.2, October 2013
6 Freescale Semiconductor, Inc.
Section number Title Page
Chapter 6
Reset and Boot
6.1 Introduction...................................................................................................................................................................139
6.2 Reset..............................................................................................................................................................................139
6.2.1 Power-on reset (POR)..................................................................................................................................140
6.2.2 System reset sources....................................................................................................................................140
6.2.3 MCU resets..................................................................................................................................................144
6.2.4 RESET_b pin ..............................................................................................................................................145
6.2.5 Debug resets.................................................................................................................................................145
6.3 Boot...............................................................................................................................................................................146
6.3.1 Boot sources.................................................................................................................................................146
6.3.2 FOPT boot options.......................................................................................................................................147
6.3.3 Boot sequence..............................................................................................................................................148
Chapter 7
Power Management
7.1 Introduction...................................................................................................................................................................151
7.2 Clocking modes............................................................................................................................................................151
7.2.1 Partial Stop...................................................................................................................................................151
7.2.2 DMA Wakeup..............................................................................................................................................152
7.2.3 Compute Operation......................................................................................................................................153
7.2.4 Peripheral Doze............................................................................................................................................154
7.2.5 Clock gating.................................................................................................................................................155
7.3 Power modes.................................................................................................................................................................155
7.4 Entering and exiting power modes...............................................................................................................................157
7.5 Module operation in low-power modes........................................................................................................................158
Chapter 8
Security
8.1 Introduction...................................................................................................................................................................163
8.1.1 Flash security...............................................................................................................................................163
KL26 Sub-Family Reference Manual, Rev. 3.2, October 2013
Freescale Semiconductor, Inc. 7
Section number Title Page
8.1.2 Security interactions with other modules.....................................................................................................163
Chapter 9
Debug
9.1 Introduction...................................................................................................................................................................165
9.2 Debug port pin descriptions..........................................................................................................................................165
9.3 SWD status and control registers..................................................................................................................................165
9.3.1 MDM-AP Control Register..........................................................................................................................167
9.3.2 MDM-AP Status Register............................................................................................................................169
9.4 Debug resets..................................................................................................................................................................170
9.5 Micro Trace Buffer (MTB)...........................................................................................................................................171
9.6 Debug in low-power modes..........................................................................................................................................171
9.7 Debug and security.......................................................................................................................................................172
Chapter 10
Signal Multiplexing and Signal Descriptions
10.1 Introduction...................................................................................................................................................................173
10.2 Signal multiplexing integration....................................................................................................................................173
10.2.1 Port control and interrupt module features..................................................................................................174
10.2.2 Clock gating.................................................................................................................................................175
10.2.3 Signal multiplexing constraints....................................................................................................................175
10.3 Pinout............................................................................................................................................................................176
10.3.1 KL26 Signal Multiplexing and Pin Assignments........................................................................................176
10.3.2 KL26 pinouts................................................................................................................................................180
10.4 Module Signal Description Tables................................................................................................................................185
10.4.1 Core modules...............................................................................................................................................185
10.4.2 System modules...........................................................................................................................................186
10.4.3 Clock modules..............................................................................................................................................186
10.4.4 Memories and memory interfaces................................................................................................................186
10.4.5 Analog..........................................................................................................................................................187
10.4.6 Timer Modules.............................................................................................................................................187
KL26 Sub-Family Reference Manual, Rev. 3.2, October 2013
8 Freescale Semiconductor, Inc.
Section number Title Page
10.4.7 Communication interfaces...........................................................................................................................188
10.4.8 Human-machine interfaces (HMI)...............................................................................................................190
Chapter 11
Port control and interrupt (PORT)
11.1 Introduction...................................................................................................................................................................191
11.2 Overview.......................................................................................................................................................................191
11.2.1 Features........................................................................................................................................................191
11.2.2 Modes of operation......................................................................................................................................192
11.3 External signal description............................................................................................................................................192
11.4 Detailed signal description............................................................................................................................................193
11.5 Memory map and register definition.............................................................................................................................193
11.5.1 Pin Control Register n (PORTx_PCRn).......................................................................................................199
11.5.2 Global Pin Control Low Register (PORTx_GPCLR)..................................................................................201
11.5.3 Global Pin Control High Register (PORTx_GPCHR).................................................................................202
11.5.4 Interrupt Status Flag Register (PORTx_ISFR)............................................................................................202
11.6 Functional description...................................................................................................................................................203
11.6.1 Pin control....................................................................................................................................................203
11.6.2 Global pin control........................................................................................................................................204
11.6.3 External interrupts........................................................................................................................................204
Chapter 12
System Integration Module (SIM)
12.1 Introduction...................................................................................................................................................................207
12.1.1 Features........................................................................................................................................................207
12.2 Memory map and register definition.............................................................................................................................207
12.2.1 System Options Register 1 (SIM_SOPT1)..................................................................................................209
12.2.2 SOPT1 Configuration Register (SIM_SOPT1CFG)....................................................................................210
12.2.3 System Options Register 2 (SIM_SOPT2)..................................................................................................211
12.2.4 System Options Register 4 (SIM_SOPT4)..................................................................................................213
12.2.5 System Options Register 5 (SIM_SOPT5)..................................................................................................215
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Freescale Semiconductor, Inc. 9
Section number Title Page
12.2.6 System Options Register 7 (SIM_SOPT7)..................................................................................................216
12.2.7 System Device Identification Register (SIM_SDID)...................................................................................218
12.2.8 System Clock Gating Control Register 4 (SIM_SCGC4)............................................................................220
12.2.9 System Clock Gating Control Register 5 (SIM_SCGC5)............................................................................222
12.2.10 System Clock Gating Control Register 6 (SIM_SCGC6)............................................................................224
12.2.11 System Clock Gating Control Register 7 (SIM_SCGC7)............................................................................226
12.2.12 System Clock Divider Register 1 (SIM_CLKDIV1)...................................................................................226
12.2.13 Flash Configuration Register 1 (SIM_FCFG1)...........................................................................................228
12.2.14 Flash Configuration Register 2 (SIM_FCFG2)...........................................................................................229
12.2.15 Unique Identification Register Mid-High (SIM_UIDMH)..........................................................................230
12.2.16 Unique Identification Register Mid Low (SIM_UIDML)...........................................................................231
12.2.17 Unique Identification Register Low (SIM_UIDL)......................................................................................231
12.2.18 COP Control Register (SIM_COPC)...........................................................................................................232
12.2.19 Service COP (SIM_SRVCOP).....................................................................................................................233
12.3 Functional description...................................................................................................................................................233
Chapter 13
System Mode Controller (SMC)
13.1 Introduction...................................................................................................................................................................235
13.2 Modes of operation.......................................................................................................................................................235
13.3 Memory map and register descriptions.........................................................................................................................237
13.3.1 Power Mode Protection register (SMC_PMPROT).....................................................................................238
13.3.2 Power Mode Control register (SMC_PMCTRL).........................................................................................239
13.3.3 Stop Control Register (SMC_STOPCTRL).................................................................................................241
13.3.4 Power Mode Status register (SMC_PMSTAT)...........................................................................................242
13.4 Functional description...................................................................................................................................................243
13.4.1 Power mode transitions................................................................................................................................243
KL26 Sub-Family Reference Manual, Rev. 3.2, October 2013
10 Freescale Semiconductor, Inc.
Section number Title Page
13.4.2 Power mode entry/exit sequencing..............................................................................................................245
13.4.3 Run modes....................................................................................................................................................248
13.4.4 Wait modes..................................................................................................................................................249
13.4.5 Stop modes...................................................................................................................................................250
13.4.6 Debug in low power modes.........................................................................................................................253
Chapter 14
Power Management Controller (PMC)
14.1 Introduction...................................................................................................................................................................255
14.2 Features.........................................................................................................................................................................255
14.3 Low-voltage detect (LVD) system................................................................................................................................255
14.3.1 LVD reset operation.....................................................................................................................................256
14.3.2 LVD interrupt operation...............................................................................................................................256
14.3.3 Low-voltage warning (LVW) interrupt operation.......................................................................................256
14.4 I/O retention..................................................................................................................................................................257
14.5 Memory map and register descriptions.........................................................................................................................257
14.5.1 Low Voltage Detect Status And Control 1 register (PMC_LVDSC1)........................................................258
14.5.2 Low Voltage Detect Status And Control 2 register (PMC_LVDSC2)........................................................259
14.5.3 Regulator Status And Control register (PMC_REGSC)..............................................................................260
Chapter 15
Low-Leakage Wakeup Unit (LLWU)
15.1 Introduction...................................................................................................................................................................263
15.1.1 Features........................................................................................................................................................263
15.1.2 Modes of operation......................................................................................................................................264
15.1.3 Block diagram..............................................................................................................................................265
15.2 LLWU signal descriptions............................................................................................................................................266
15.3 Memory map/register definition...................................................................................................................................266
15.3.1 LLWU Pin Enable 1 register (LLWU_PE1)................................................................................................267
15.3.2 LLWU Pin Enable 2 register (LLWU_PE2)................................................................................................268
15.3.3 LLWU Pin Enable 3 register (LLWU_PE3)................................................................................................269
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Freescale Semiconductor, Inc. 11
Section number Title Page
15.3.4 LLWU Pin Enable 4 register (LLWU_PE4)................................................................................................270
15.3.5 LLWU Module Enable register (LLWU_ME)............................................................................................271
15.3.6 LLWU Flag 1 register (LLWU_F1).............................................................................................................273
15.3.7 LLWU Flag 2 register (LLWU_F2).............................................................................................................275
15.3.8 LLWU Flag 3 register (LLWU_F3).............................................................................................................276
15.3.9 LLWU Pin Filter 1 register (LLWU_FILT1)..............................................................................................278
15.3.10 LLWU Pin Filter 2 register (LLWU_FILT2)..............................................................................................279
15.4 Functional description...................................................................................................................................................280
15.4.1 LLS mode.....................................................................................................................................................281
15.4.2 VLLS modes................................................................................................................................................281
15.4.3 Initialization.................................................................................................................................................281
Chapter 16
Reset Control Module (RCM)
16.1 Introduction...................................................................................................................................................................283
16.2 Reset memory map and register descriptions...............................................................................................................283
16.2.1 System Reset Status Register 0 (RCM_SRS0)............................................................................................284
16.2.2 System Reset Status Register 1 (RCM_SRS1)............................................................................................285
16.2.3 Reset Pin Filter Control register (RCM_RPFC)..........................................................................................286
16.2.4 Reset Pin Filter Width register (RCM_RPFW)...........................................................................................287
Chapter 17
Bit Manipulation Engine (BME)
17.1 Introduction...................................................................................................................................................................289
17.1.1 Overview......................................................................................................................................................290
17.1.2 Features........................................................................................................................................................291
17.1.3 Modes of operation......................................................................................................................................291
17.2 Memory map and register definition.............................................................................................................................291
KL26 Sub-Family Reference Manual, Rev. 3.2, October 2013
12 Freescale Semiconductor, Inc.
Section number Title Page
17.3 Functional description...................................................................................................................................................292
17.3.1 BME decorated stores..................................................................................................................................292
17.3.2 BME decorated loads...................................................................................................................................299
17.3.3 Additional details on decorated addresses and GPIO accesses....................................................................305
17.4 Application information................................................................................................................................................306
Chapter 18
Miscellaneous Control Module (MCM)
18.1 Introduction...................................................................................................................................................................309
18.1.1 Features........................................................................................................................................................309
18.2 Memory map/register descriptions...............................................................................................................................309
18.2.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)................................................................310
18.2.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC)............................................................311
18.2.3 Platform Control Register (MCM_PLACR)................................................................................................311
18.2.4 Compute Operation Control Register (MCM_CPO)...................................................................................314
Chapter 19
Micro Trace Buffer (MTB)
19.1 Introduction...................................................................................................................................................................317
19.1.1 Overview......................................................................................................................................................317
19.1.2 Features........................................................................................................................................................320
19.1.3 Modes of operation......................................................................................................................................321
19.2 External signal description............................................................................................................................................321
19.3 Memory map and register definition.............................................................................................................................322
19.3.1 MTB_RAM Memory Map...........................................................................................................................322
19.3.2 MTB_DWT Memory Map...........................................................................................................................335
19.3.3 System ROM Memory Map.........................................................................................................................345
Chapter 20
Crossbar Switch Lite (AXBS-Lite)
20.1 Introduction...................................................................................................................................................................351
20.1.1 Features........................................................................................................................................................351
20.2 Memory Map / Register Definition...............................................................................................................................352
KL26 Sub-Family Reference Manual, Rev. 3.2, October 2013
Freescale Semiconductor, Inc. 13
Section number Title Page
20.3 Functional Description..................................................................................................................................................352
20.3.1 General operation.........................................................................................................................................352
20.3.2 Arbitration....................................................................................................................................................353
20.4 Initialization/application information...........................................................................................................................354
Chapter 21
Peripheral Bridge (AIPS-Lite)
21.1 Introduction...................................................................................................................................................................355
21.1.1 Features........................................................................................................................................................355
21.1.2 General operation.........................................................................................................................................355
21.2 Functional description...................................................................................................................................................356
21.2.1 Access support.............................................................................................................................................356
Chapter 22
Direct Memory Access Multiplexer (DMAMUX)
22.1 Introduction...................................................................................................................................................................357
22.1.1 Overview......................................................................................................................................................357
22.1.2 Features........................................................................................................................................................358
22.1.3 Modes of operation......................................................................................................................................358
22.2 External signal description............................................................................................................................................359
22.3 Memory map/register definition...................................................................................................................................359
22.3.1 Channel Configuration register (DMAMUXx_CHCFGn)..........................................................................360
22.4 Functional description...................................................................................................................................................360
22.4.1 DMA channels with periodic triggering capability......................................................................................361
22.4.2 DMA channels with no triggering capability...............................................................................................363
22.4.3 Always-enabled DMA sources....................................................................................................................363
22.5 Initialization/application information...........................................................................................................................365
22.5.1 Reset.............................................................................................................................................................365
22.5.2 Enabling and configuring sources................................................................................................................365
KL26 Sub-Family Reference Manual, Rev. 3.2, October 2013
14 Freescale Semiconductor, Inc.
Section number Title Page
Chapter 23
DMA Controller Module
23.1 Introduction...................................................................................................................................................................369
23.1.1 Overview......................................................................................................................................................369
23.1.2 Features........................................................................................................................................................371
23.2 DMA Transfer Overview..............................................................................................................................................371
23.3 Memory Map/Register Definition.................................................................................................................................372
23.3.1 Source Address Register (DMA_SARn).....................................................................................................374
23.3.2 Destination Address Register (DMA_DARn).............................................................................................375
23.3.3 DMA Status Register / Byte Count Register (DMA_DSR_BCRn).............................................................375
23.3.4 DMA Control Register (DMA_DCRn)........................................................................................................378
23.4 Functional Description..................................................................................................................................................381
23.4.1 Transfer requests (Cycle-Steal and Continuous modes)..............................................................................382
23.4.2 Channel initialization and startup................................................................................................................382
23.4.3 Dual-Address Data Transfer Mode..............................................................................................................384
23.4.4 Advanced Data Transfer Controls: Auto-Alignment...................................................................................385
23.4.5 Termination..................................................................................................................................................386
Chapter 24
Multipurpose Clock Generator (MCG)
24.1 Introduction...................................................................................................................................................................387
24.1.1 Features........................................................................................................................................................387
24.1.2 Modes of Operation.....................................................................................................................................389
24.2 External Signal Description..........................................................................................................................................389
24.3 Memory Map/Register Definition.................................................................................................................................390
24.3.1 MCG Control 1 Register (MCG_C1)...........................................................................................................390
24.3.2 MCG Control 2 Register (MCG_C2)...........................................................................................................392
24.3.3 MCG Control 3 Register (MCG_C3)...........................................................................................................393
24.3.4 MCG Control 4 Register (MCG_C4)...........................................................................................................394
24.3.5 MCG Control 5 Register (MCG_C5)...........................................................................................................395
KL26 Sub-Family Reference Manual, Rev. 3.2, October 2013
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Artemis Development Kit Reference guide

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Reference guide
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