Janz Tec emPC-CX+ System Reference Manual

Brand
Janz Tec
Model
emPC-CX+
Type
System Reference Manual
PROPRIETARY NOTICE
All rights reserved by Janz Tec AG.
No parts of this technical manual may be modified, copied or reproduced
in any form or by any means for commercial use without the prior written
permission of Janz Tec AG, Germany.
All instructions, information and specification contained in this manual
are for reference only and remain subject to change without
announcement.
emPC-CX+
embedded computer system
(System Reference Manual)
Version 1.2
refers to product revision no.
V -
Title:
emPC-CX platforms systems reference
File:
j:\as\entwicklung\projekte\hw\empc\empc_+\doc\manual\manual_empc-
cxplus_platforms_system_reference.doc
Pattern:
c:\users\as\appdata\roaming\microsoft\templates\normal.dotm
Created:
24.09.2012
Last Update:
Stefan Althöfer, 02.06.2015
© Janz Tec AG 2014
Im Dörener Feld 8
PO Box 1906
D-33 049 Paderborn, Germany
Tel.:
FAX:
email:
Internet:
emPC-CX+ (System Reference Manual) Contents i
Rev. 1.2 © Janz Tec AG
Contents
1 Introduction 7
1.1 Features ............................................................................................................................... 7
1.2 Functional Overview ............................................................................................................ 8
1.3 Front Connectors ................................................................................................................. 9
1.4 Personality Board ...............................................................................................................10
2 Safety Instructions 11
2.1 Installation and Maintenance .............................................................................................11
2.2 Installation and Maintenance .............................................................................................11
2.3 Ambient and Environmental Conditions .............................................................................11
1 Hardware details 12
1.1 PCI Express .......................................................................................................................12
1.1.1 PCI Express mini card ..................................................................................................12
1.2 Video Output ......................................................................................................................12
1.3 Ethernet ..............................................................................................................................13
1.3.1 Ethernet 1 .....................................................................................................................13
1.3.2 Ethernet 2 .....................................................................................................................13
1.4 USB ....................................................................................................................................13
1.4.1 Front Panel USB ...........................................................................................................13
1.4.2 Internal USB ..................................................................................................................13
1.5 SATA ..................................................................................................................................13
1.6 LVDS ..................................................................................................................................14
1.7 Display Touch- and Power-Connector ...............................................................................15
2 FPGA expansion subsystem 16
2.1 Control Registers ...............................................................................................................17
2.1.1 Feature detection ..........................................................................................................17
2.1.2 Interrupt programming ..................................................................................................17
2.1.3 Function Reset ..............................................................................................................18
2.1.4 Internal I2C bus .............................................................................................................18
2.2 CAN Interface .....................................................................................................................19
2.2.1 CAN address space ......................................................................................................19
2.2.2 CAN termination and LEDs ...........................................................................................19
2.3 Serial Port Interface ...........................................................................................................20
2.3.1 Serial Port address space .............................................................................................20
2.4 NVRAM ..............................................................................................................................21
2.5 Digital IO ............................................................................................................................22
2.6 FPGA Reprogramming ......................................................................................................23
3 System Control 24
3.1.1 I2C Address ..................................................................................................................26
3.1.2 I2C Registers ................................................................................................................26
3.1.3 Command Codes ..........................................................................................................31
3.2 FAN Controller ...................................................................................................................32
3.2.1 I2C Communication ......................................................................................................32
3.2.2 I2C Address ..................................................................................................................33
3.2.3 Registers .......................................................................................................................33
3.2.4 Command Codes ..........................................................................................................36
3.2.5 Configuration .................................................................................................................37
4 Appendices 38
4.1 References .........................................................................................................................38
ii emPC-CX+ (System Reference Manual)
© Janz Tec AG Rev. 1.2
4.2 Personality Board Connector .............................................................................................39
4.3 Product History...................................................................................................................41
4.4 Manual History ...................................................................................................................42
emPC-CX+ (System Reference Manual) Contents iii
Rev. 1.2 © Janz Tec AG
List of Figures
Figure 1: emPC-CX+ block diagram......................................................................................................... 8
Figure 2: emPC-CX+ carrier module front connectors ............................................................................. 9
Figure 3: emPC-CX+ system supervision ..............................................................................................24
figure 4: System control by power supply voltage (VIN) ........................................................................25
figure 5:System control by remote control input (VS) .............................................................................25
Figure 6: PMON I2C Protocols ...............................................................................................................26
figure 7: fan controller setpoints .............................................................................................................32
figure 8: fan controller I2C Protocols ......................................................................................................33
List of Tables
Table 1: Available Personality Board .....................................................................................................10
Table 2: COM Express PCIe lane usage ...............................................................................................12
Table 3: Internal USB connector. ...........................................................................................................13
Table 4: COM Express SATA usage ......................................................................................................13
Table 5: SATA power connector. ...........................................................................................................14
Table 6: LVDS panel connector (internal) ..............................................................................................14
Table 7: Display and touch- and power connector (internal)..................................................................15
Table 8: PCI identification.......................................................................................................................16
Table 9: Local address spaces ...............................................................................................................16
Table 10: Control registers .....................................................................................................................17
Table 11: NVRAM address (128KByte NVRAM)....................................................................................21
Table 12: Digital IO registers ..................................................................................................................22
Table 13: Personality board connector pin assignment .........................................................................39
Table 14: Personality board connector signal description ......................................................................40
iv emPC-CX+ (System Reference Manual)
© Janz Tec AG Rev. 1.2
About this Manual
This is the system reference manual for the CX+ series. It starts with an introduction to the emPC-CX+
and emVIEW. It describes the features and architecture of the CX series. After that it discusses some
topics about programming for these products.
For a description of the emPC-CX+ and emPC-CX+ refer to the respective hardware manuals; the
Janz Tec AG homepage gives information about it.
Conventions
DANGER
indicates that death or severe personal injury will result if proper precautions are not
taken.
WARNING
indicates that death or severe personal injury may result if proper precautions are not
taken.
CAUTION
indicates that minor personal injury can result if proper precautions are not taken.
NOTICE
indicates that damage to equipment can result if proper precautions are not taken.
indicates information that we think you should have read to save your time by avoiding
common problems. Important suggestions that should be followed will also be marked
with this sign.
If numbers are specified in this manual, they will be either decimal or hexadecimal. We use C-notation
to identify hexadecimal numbers (the 0x prefix).
If we refer to low active signal names, they will suffixed by a “#” character.
Register descriptions are done in the following style:
Word address
↓
Access width
↓
Access type
↓
Register Name
serial EEPROM
0x080
(byte,
rw)
Bit Numbers
7
6
5
4
3
2
1
0
Field Numbers
reserved
SCL
SDA
Reset:
State after Reset
-
0
0
The access type specifies the possible operations on this register. The code ro (read-only)
says that this register is only defined for read operations, while the code wo (write-only)
indicates that this register can only be written. Undefined operations must be performed on a
register.
The code rw (read/write) specifies that this register might be read and written. Depending on
the detailed description for a register, this does not necessarily mean that you can do read-
modify-write operations on this register.
The state-after-reset specifies the value that is read after reset, or the internal value after reset
emPC-CX+ (System Reference Manual) Contents v
Rev. 1.2 © Janz Tec AG
if the register is of type read-only. If several reset conditions are possible, the exact source is
specified.
Some parts of the text are really important. These are visually marked with the following signs:
Some parts of the manual contains notices you have to observe to ensure your personal safety, or to
prevent damage to property. These are visually marked with the following alert symbols:
Acronyms and Abbreviations
CAN
Controller Area Network
EMC
Electromagnetic capability
ESD
Electrostatic discharge
FLASH
Electrically erasable PROM. Capable of in-circuit re-programming with the capability
of erasing considerably large blocks (in contrast to EEPROM)
HDD
Hard Disk Drive
I/O
Input / Output
LED
Light Emitting Diode
MDIX
Media Dependent Interface Crossover
MII
Medium Independent Interface
NVRAM
Non volatile RAM. Storage is ensured by a battery or flash memory backup
PCB
Printed Circuit Board
PHY
PHYsical Layer in ISO/OSI-Standard
PWM
Pulse Width Modulation
USB
Universal Serial Bus
emPC-CX+ (System Reference Manual) Introduction 1 - 7
Rev. 1.2 © Janz Tec AG
1 Introduction
The CX series are flexible embedded computing systems based on high performance processor
technologies. Due to permanent minimization of all machines the CX series are a small but flexible
and high performance computing system which matches all needs of different customized solutions.
Additionally the emPC-CX+ systems are able to be mounted on the rear side of a LCD display to
become a flexible HMI system with or without touch screen called emVIEW. Look for these emVIEW
systems for more information at the Janz homepage. The emPC-CX+ series is available all common
operating system.
1.1 Features
small housing size
Typ 6 COM Express powered
Up to 4x USB 3.0 (2 additional internal USB 2.0)
1x DVI-I
2x 10/100/1000 Mbits Ethernet
CFAST slot
(9)14 .. 34 V DC power supply
fanless cooling concept with low power CPUs
PCIe based expansion options
Riser card connector with 2x X1 and 2x X4 link width
PCIe mini card connector
2x X1 link on personality module
PCIe attached FPGA subsystem with flexible IO personality module
Up to 2x isolated CAN ports with SJA1000 controller and LED status indicators
RS232/RS485 interfaces (non-legacy)
Digital IO
status LEDs for power-on and HDD activity
internal LVDS port for use in combination with emVIEW displays
internal serial port for the touch screen (emVIEW display only)
internal 2x SATA connector for SATA 2,5’’ HDD
1 - 8 emPC-CX+ (System Reference Manual) Introduction
© Janz Tec AG Rev. 1.2
1.2 Functional Overview
Basically an emPC-CX+ system consists of a base board with several interfaces and connectors. To
be scalable in computing power an COM Express Typ 6 embedded computer module is snapped onto
the base board. The heat spreader of the Com Express module is mounted on the backside case heat
sink.
A variety of customization options are available:
PCIe slots with various riser cards
PCIe Mini Card
I/O Interfaces with personality board
SATA0
SATA1
SATA2
GBE 2x
10/100/1000
BaseT
Reset Button
CFast
Socket
9..34V DC Power
input
DC/DC
Power
Management
PCIe Riser Card Connector
Display Interface
Intel
i210IT
Power LED
SATA Activity LED
4x USB 3.0
2x USB 2.0
PCIe Mini Card
PCIe
USB 2.0
PCIe
LVDS DVI-I
Status LEDs
FrontInternal
DVI+VGA
NvSRAM
2xPCIe
I/O’s
RS232
Transceiver
Personality Module connector
SJA1000
SJA1000
2x PCIe x1 2x PCIe x4
Type 6 ComExpress Modul
1xPCIe
Spartan6
LX25T
Spartan6
LX25T
PCIe - Local Bus
Bridge
COM1
COM0
HDA
Temp. Sensor
I²C
I²C
SUS_Sx / PWR_Btn / PWR_OK
Fan Controller
Power Supply
UART
UART
Power Button
Remote
Figure 1: emPC-CX+ block diagram
emPC-CX+ (System Reference Manual) Introduction 1 - 9
Rev. 1.2 © Janz Tec AG
1.3 Front Connectors
DVI-I
CFast
LAN-2 LAN-1 Serial 1
Headers defined by personality module
4 x USB
Power
HDD Reset
Power BTN
Figure 2: emPC-CX+ carrier module front connectors
1 - 10 emPC-CX+ (System Reference Manual) Introduction
© Janz Tec AG Rev. 1.2
1.4 Personality Board
Pers. Board
Features
BO-EPC-CPP00
2 x CAN (isolated), digital IO
BO-EPC-CPP01
2 x CAN (isolated)
BO-EPC-CPPS0
1 x CAN (isolated), 1 x RS232, digital IO
BO-EPC-CPPS1
1 x CAN (isolated), 1 x RS232
BO-EPC-CPPU0
4 x RS232, USB based (suitable for CX+ Lite)
Table 1: Available Personality Board
emPC-CX+ (System Reference Manual) Safety Instructions 2 - 11
Rev. 1.2 © Janz Tec AG
2 Safety Instructions
Refer to page iv for explanation of the warning notice system.
This manual describes only internal technical information. It is the system integrators responsibility to
identify and document risks in the documentation of the final product. Refer to the product manual for
specific safety instructions.
The following general risks apply to the board level products as described in this manual.
2.1 Installation and Maintenance
2.2 Installation and Maintenance
DANGER
The boards may only be operated with power supply systems with outputs which can be
considered as SELV circuits.
WARNING
The IO interfaces (connectors) of the boards are only suited to be connected to SELV
circuits if not otherwise noted.
CAUTION
Some of the boards are equipped with a Lithium battery.
Danger of explosion when replacing with wrong type of battery. Replace only with battery
of the same or equivalent type.
2.3 Ambient and Environmental Conditions
CAUTION
Do not operate the boards beyond the specified ambient conditions.
DANGER
Do not operate the boards in potentially explosive atmosphere.
1 - 12 emPC-CX+ (System Reference Manual) Hardware details
© Janz Tec AG Rev. 1.2
1 Hardware details
1.1 PCI Express
The emPC-CX+ uses PCI Express for a couple of expansion options. Some COM Express modules
only provide a limited number of PCI Express lanes. Refer to Table 2 for a detailed resource list.
COM Express
PCIe lanes
Function
PCIE0
Ethernet 2
PCIE1
FPGA
PCIE2
PCI Express mini card
PCIE3
Riser card connector
PCIE4
Riser card connector
PCIE5
Personality board
PCIE6
Personality board
PCIE7
unused (unsupported by most COMe modules)
PEG8-15
Riser card connector
Table 2: COM Express PCIe lane usage
Certain COM Express modules may only offer a limited number PCI Express lanes, starting with
PCIE0. Some or all PCI Express expansion options are not available in systems with such modules.
PEG8-15 lanes (if available for a certain COM Express module) can usually be configured for different
link configurations:
1x X8
2x X4
NOTICE
The riser card connector utilizes a 164 pin PCIe connector with nonstandard pin
assignment. DO NOT ATTEMPT to plug standard PCIe cards or riser cards INTO THIS
SOCKET.
1.1.1 PCI Express mini card
The PCI Express mini card slot provides the PCI Express interface. It is not compatible with mSATA
storage modules. Besides of the PCI Express interface, USB5 can be used on this socket.
A UIM module for SIM card usage can optionally be equipped on the carrier board.
1.2 Video Output
The emPC-CX+ provides DVI-I video output:
VGA analog signals provided by the analog video output signals of the COM Express
modules. This feature is not available if the used COM Express module does not provide
analog video singnals (some ATOM base low power modules do not)
DVI digital signals provided by the COM Express DDI1 interface. This feature is only available
if this interface can be configured for DVI/HDMI mode (sometime called TMDS).
emPC-CX+ (System Reference Manual) Hardware details 1 - 13
Rev. 1.2 © Janz Tec AG
1.3 Ethernet
The emPC-CX+ provides two 10/100/1000 ethernet interfaces
1.3.1 Ethernet 1
This Ethernet interface is provides by the COM Express module, refer to the module documentation
for details (e.g. controller type).
Wake on LAN implementation depends on the COM Express modules and is usually possible.
1.3.2 Ethernet 2
This Ethernet interface is implanted on the carrier board by an Intel i210 ethernet controller.
The standard configuration uses the i210’s iNVM memory for parameter storage. As an option,
external FLASH memory option is possible, but not normally equipped on the carrier board.
Wake on LAN is not supported by Ethernet 2.
1.4 USB
1.4.1 Front Panel USB
The emPC-CX+ provides 4 front panel USB Typ A connectors.
The front panel USB connectors always have the blue USB 3.0 colour code. However,
USB 3.0 function is only available when supported by the COM Express module.
If the COM Express module does not support USB 3.0, the front panel USB connectors
will function as USB 2.0 interfaces (with full mechanical compatibility).
1.4.2 Internal USB
The emPC-CX+ provides an internal USB connector with two USB Ports. This is a standard 10 pin
dual row connector with 2.54 mm grid.
1
VCC7
VCC6
2
3
USB7N
USB6N
4
5
USB7P
USB6P
6
7
GND7
GND6
8
9
SHIELD/GND
SHIELD/GND
10
Table 3: Internal USB connector.
VCC6 and VCC7 are each internally fuses by a 900 mA USB power switch.
1.5 SATA
The emPC-CX+ uses the COM Express defined SATA interfaces to connect mass storage.
COM Express
SATA channel
Usage
SATA0
CFast socket
SATA1
Internal 7pin SATA header
SATA2
Internal 7 pin SATA header
SATA3
unused
Table 4: COM Express SATA usage
1 - 14 emPC-CX+ (System Reference Manual) Hardware details
© Janz Tec AG Rev. 1.2
Refer to the COM Express module documentation about the number of supported SATA channel and
the supported features (e.g. speed, Raid functions).
NOTICE
The CFast socket does not support hot swap functionality. Turn power off before cards
are inserted or extracted.
An internal 4 pin MINIFIT header provides power for SATA devices (HDD/SSD):
1
GND
GND
2
3
+5V
+5V
4
Table 5: SATA power connector.
1.6 LVDS
The emPC-CX+ provides dual channel 24bit LVDS video signal for connection to a flat panel display.
The LVDS signals are found on an internal 1,27mm header. The pin out of this connector is shown in
Table 6.
1
BLON#
DIGON
2
3
LDDETECT
DCCLK
4
5
GND
DCDAT
6
7
BIASON
8
9
GND
10
11
TAx0-
TAx0+
12
13
GND
TAx1-
14
15
TAx1+
GND
16
17
TAx2-
TAx2+
18
19
GND
TAx3-
20
21
TAx3+
GND
22
23
TAxC-
TAxC+
24
25
GND
TBx0-
26
27
TBx0+
GND
28
29
TBx1-
TBx1+
30
31
GND
TBx2-
32
33
TBX2+
GND
34
35
TBx3-
TBx3+
36
37
GND
TBxC-
38
39
TBxC+
GND
40
Table 6: LVDS panel connector (internal)
All signals have/tolerate LVTTL Level, except LVDS signals. The signals have the following functions:
Signal Names
Sig-Dir
Description
BLON#
Output
Active low. Enables power to the backlight
inverter when active. This is the inverted COM
Express LVDS_BKLT_EN signal.
DIGON
Output
Active high. Enables power to the digital logic of
the flatpanel. Connected to COM Express
LVDS_VDD_EN signal.
BIASON
Output
Controls contrast voltage to the panel.
Connected to COM Express LVDS_BKLT_CTRL
signal.
LDDETECT
Output
LVDS mapping selection.
Driven to +3V3 to indicate that the LVDS signals
emPC-CX+ (System Reference Manual) Hardware details 1 - 15
Rev. 1.2 © Janz Tec AG
are mapped in industry standard mode. Driven
to GND to indicate open LDI mode.
Implemented by Jumper J2 on the emPC-CX+
(J2=set corresponds to low).
DCCLK/DCDAT
BiDir
I2C Interface to detect and configure the display
(display specific). Also used for backlight control.
These signals are connected to COM Express
LVDS_I2C_CLK and LVDS_I2C_DAT.
The following LVDS cable components are recommended:
Socket
Samtec EHF-120-01-xxxx
Cable
Samtec FFSD-20-D-xxxx
Backlight intensity control is performed by the LVDS I2C interface. Refer to the COM Express module
vendors description for applicable libraries or interfaces.
1.7 Display Touch- and Power-Connector
1
RxD
TxD
2
3
RTS
GND
4
5
PSON#
+5V
6
7
GND
+3V3
8
9
GND
VIN
10
11
GND
VIN
12
13
GND
VIN
14
15
USB+
USB-
16
17
GND
+5V
18
19
n.c.
n.c.
20
Table 7: Display and touch- and power connector (internal)
All signals have/tolerate LVTTL Level, except USB signals. The signals have the following functions:
Signal Names
Sig-Dir
Description
RxD
Input
Serial port receive signal for touch (COM2)
TxD
Output
Serial port transmit signal for touch (COM2)
RTS
TBD
RTS handshake for touch (COM2)
PSON#
Output
Power supply control signal for display power
supply unit. Signal is low to turn power supply
on.
GND
-
Reference Signal
+3V3/+5V
-
+3.3V/5V power supply for use on display
interface circuit. This power supply is on as long
as the COM Express module is running (S0
state). This power supply is not switched when
the display is turn off.
VIN
-
Input power supply fed through for display
interface logic. Display and Touch power use
this power supply to generate required power
supplies (e.g. +12V).
USB+/USB-
-
Internal USB interface for touch (COM Express
USB4)
2 - 16 emPC-CX+ (System Reference Manual) FPGA expansion subsystem
© Janz Tec AG Rev. 1.2
2 FPGA expansion subsystem
The PCIe interface for special Janz Tec Features is implemented by a FPGA and is identified by a set
of IDs in PCIe configuration space as listed below:
Purpose
Value
Found in
Vendor ID
0x13C3
CFG space register 0x00
Device ID
0x2600
CFG space register 0x02
Subsystem Vendor ID
0x13C3
CFG space register 0x2C
Subsystem ID emPC-CX+
0x2600
CFG space register 0x2E
Table 8: PCI identification
The FPGA PCIe interface provides access to several register spaces.
PCI base
address
register
Description
Size
0
Local configuration registers (memory mapped)
512 B
1
N/A
-
2
CAN/RS232 address space
8 kB
3
Reserved
8 kB
4
Control registers
4 kB
5
NVRAM / IO port address space
1 MB
Table 9: Local address spaces
The actual addresses for these memory spaces are configured by the BIOS of your system every time
the computer is booted. If you wish to access one of these spaces, then you need to read the actual
addresses from the PCIe configuration space.
emPC-CX+ (System Reference Manual) FPGA expansion subsystem 2 - 17
Rev. 1.2 © Janz Tec AG
2.1 Control Registers
Address Offset
access
Description
BAR4 + 0x00
RO
INT_STAT
BAR4 + 0x04
RO
INT_MASK
BAR4 + 0x08
WO
INT_DISABLE
BAR4 + 0x0C
WO
INT_ENABLE
BAR4 + 0x10
WO
RESET_ASSERT
BAR4 + 0x14
WO
RESET_DEASSERT
BAR4 + 0x18
RO
RESET_STATUS
BAR4 + 0x1c
RW
I2C_CONTROL
BAR4 + 0x20
RO
FEATURE1
BAR4 + 0x24
RO
FEATURE2
BAR4 + 0x30
RW
TESTREG
BAR4 + 0x3C
RO
REVISON
Table 10: Control registers
2.1.1 Feature detection
FEATURE1 BAR4 + 0x20 (32bit, ro)
31..9
9
8
7..2
1
0
reserved
COM1
COM0
Reserved
CAN1
CAN0
CAN[1..0]
High if corresponding CAN is available
COM[1..0]
High if corresponding COM is available
Reserved
Reserved positions are zero
REVISION BAR4 + 0x3c (32bit, ro)
31..9
9
8
7..2
1
0
TBD
2.1.2 Interrupt programming
The FPGA generate an interrupt that is logically or’ed amoung all internal interrupt sources.
To determine which source has generated an interrupt the Interrupt handler must read the interrupt
status register:
INT_STAT BAR4 + 0x0 (32bit, ro)
31..9
9
8
7..2
1
0
reserved
COM1
COM0
Reserved
CAN1
CAN0
CAN[1..0]
Interrupt status info. Each defined bit in this register reflects the status of
the INT# pin of the corresponding CAN. A zero will be read when an
interrupt is pending.
If a CAN interrupt request line is disabled, then the corresponding bit is
2 - 18 emPC-CX+ (System Reference Manual) FPGA expansion subsystem
© Janz Tec AG Rev. 1.2
forced to “1”.
COM[1..0]
Interrupt status info. Each defined bit in this register reflects the status of
the INT# pin of the corresponding COM. A one will be read when an
interrupt is pending.
If a COM interrupt request line is disabled, then the corresponding bit is
forced to “0”.
Reserved
Reserved positions are undefined, and must not be considered. Software
must mask them off.
Interrupt requests can be masked off by the CPU. This is done through the interrupt disable/enable
registers. Interrupts are disabled after RESET, and you need to enable a CAN interrupt line before
using it.
INT_ DISABLE BAR4 + 0x8 (32bit, wo)
31..9
9
8
7..2
1
0
reserved
COM1
COM0
Reserved
CAN1
CAN0
INT_ENABLE BAR4 + 0xC (32bit, wo)
31..9
9
8
7..2
1
0
reserved
COM1
COM0
Reserved
CAN1
CAN0
2.1.3 Function Reset
To ensure a defined state of a function at any time, it is possible to activate the RST# line of a function
via software. This can be done with the reset assert/deassert registers. The RST# line of all functions
are activated during a PCIe bus reset.
RESET_ASSERT BAR4 + 0x10 (32bit, wo)
31..9
9
8
7..2
1
0
reserved
COM1
COM0
Reserved
CAN1
CAN0
RESET_DEASSERT BAR4 + 0x14 (32bit, wo)
31..9
9
8
7..2
1
0
reserved
COM1
COM0
Reserved
CAN1
CAN0
2.1.4 Internal I2C bus
The control register for the onboard I2C interface provides bit-bang style I2C implementation.
CAN[1..0]
COM[1..0]
Writing one of the bits disables/enables interrupts from the corresponding
function. Both registers are accessed in hot-1 technique: Writing a one to
a bit disables/enables further interrupts from the corresponding function,
writing zero to a bit do not affect the interrupt mask status of that function.
If a functions interrupt request line is disabled, then this functions
interrupt bit will never appear in the INT_STAT register and it will not
cause interrupts.
Reserved
Reserved bit positions must be written as zero.
CAN[1..0]
COM[1..0]
Writing one of the bits disables/enables interrupts from the corresponding
function. Both registers are accessed in hot-1 technique: Writing a one to
a bit disables/enables further interrupts from the corresponding function,
writing zero to a bit do not affect the interrupt mask status of that function.
If a functions interrupt request line is disabled, then this functions
interrupt bit will never appear in the INT_STAT register and it will not
cause interrupts.
Reserved
Reserved bit positions must be written as zero.
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Janz Tec emPC-CX+ System Reference Manual

Brand
Janz Tec
Model
emPC-CX+
Type
System Reference Manual
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