eZ80
®
CPU
User Manual
UM007715-0415 Registers and Bit Flags
10
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Program Counter (PC) register—the multibyte Program Counter register stores the
address of the current instruction being fetched from memory. The Program Counter is
automatically incremented during program execution. When a program jump occurs,
the new value is placed in the Program Counter, overriding the incremented value. In
Z80 mode, the Program Counter is only 16 bits; however, a full 24-bit address
{MBASE,PC[15:0]}, is used. In ADL mode, the Program Counter is returned by
{PC[23:0]}.
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Refresh Counter (R) register—the Refresh Counter register contains a count of exe-
cuted instruction fetch cycles. The 7 least significant bits (lsb) of the R register are
automatically incremented after each instruction fetch. The most significant bit (msb)
can only be changed by writing to the R register. The R register can be read from and
written to using dedicated instructions
LD
A,R and
LD
R,A, respectively.
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Stack Pointer Long (SPL) register—in ADL mode, the 24-bit Stack Pointer Long
stores the address for the current top of the external stack. In ADL mode, the stack can
be located anywhere in memory. The external stack is organized as a last-in first-out
(LIFO) file. Data can be pushed onto the stack or popped off of the stack using the
PUSH and POP instructions. Interrupts, traps, calls, and returns also employ the
stack.
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Stack Pointer Short register (SPS)—in Z80 mode, the 16-bit Stack Pointer Short stores
the address for the current top of the stack. In Z80 mode, the stack can be located any-
where within the current Z80 memory page. The current Z80 memory page is selected
by the MBASE register. The 24-bit Stack Pointer address in Z80 mode is {MBASE,
SPS}. The stack is organized as a last-in first-out (LIFO) file. Data can be pushed onto
the stack or popped off of the stack using the PUSH and POP instructions. Interrupts,
traps, calls, and returns also employ the stack.
eZ80
®
CPU Control Bits
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Address and Data Long Mode Bit (ADL)—the ADL mode bit indicates the current
memory mode of the CPU. An ADL mode bit reset to 0 indicates that the CPU is oper-
ating in Z80 MEMORY mode with 16-bit Z80-style addresses offset by the 8-bit
MBASE register. An ADL mode bit set to 1 indicates that the CPU is operating in
ADL mode with 24-bit linear addressing. The default for the ADL mode bit is reset
(cleared to 0). The ADL mode bit can only be changed by those instructions that allow
persistent memory mode changes, interrupts, and traps. The ADL mode bit cannot be
directly written to.
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Mixed-ADL Bit (MADL)—the MADL control bit is used to configure the CPU to
execute programs containing code that uses both ADL and Z80 MEMORY modes.
The MADL control bit is explained in more detail in Interrupts in Mixed Memory
Mode Applications on page 36. An additional explanation is available in the Mixed-
Memory Mode Applications on page 34.