NXP TEA2016AAT User guide

Brand: NXP

Model: TEA2016AAT

Type: User guide

NXP TEA2016AAT is a controller IC for resonant power supplies which includes a PFC. It provides high efficiency at all power levels.

To reach a high efficiency at all power levels, the TEA2016AAT provides a low-power (LP) operation mode and extensive burst mode configuration options. Most LLC resonant converter controllers regulate the output power by adjusting the operating frequency. The TEA2016AAT regulates the output power by adjusting the voltage across the primary resonant capacitor for accurate state control and a linear power control.

It includes extra functions, like external OTP sensing and power good signal. To provide the correct handling, protections can be configured.

NXP TEA2016AAT is a controller IC for resonant power supplies which includes a PFC. It provides high efficiency at all power levels.

It includes extra functions, like external OTP sensing and power good signal. To provide the correct handling, protections can be configured.

UM11553

TEA2016AAT 160 W TV application design example

Rev. 1 — 4 February 2021 User manual

Document information

Information Content

Keywords TEA2016AAT, 160 W, multiple outputs, 12 V × 5 A and 100 V × 1 A, PFC,

LLC, resonant controller, burst mode, power supply, programmable setting,

Abstract The TEA2016AAT is controller IC for resonant power supplies which includes

a PFC. It provides high efficiency at all power levels.

To reach a high efficiency at all power levels, the TEA2016AAT provides

a low-power (LP) operation mode and extensive burst mode configuration

options.

Most LLC resonant converter controllers regulate the output power by

adjusting the operating frequency. The TEA2016AAT regulates the output

power by adjusting the voltage across the primary resonant capacitor for

accurate state control and a linear power control.

Parameter settings in an internal multiple times programmable memory (MTP)

define the operation modes and protections. For product development, an IC

version is available to make setting changes on the fly. To optimize controller

properties to application-specific requirements, this feature provides flexibility

and ease of design.

The TEA2016AAT provides extra functions, like external OTP sensing and

power good signal. To provide the correct handling, protections can be

configured.

The efficiency at high power levels is above 90 %. No-load power

consumption is below 150 mW. At 120 mW output power, the input power is

below the 260 mW. So it meets the TV application typical requirements.

This design example includes a dual output (12 V and 100 V) for a TV

application.

NXP Semiconductors

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TEA2016AAT 160 W TV application design example

Rev Date Description

v.1 20210204 Initial version

Revision history

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1 Introduction

WARNING

Lethal voltage and fire ignition hazard

The non-insulated high voltages that are present when operating this

product, constitute a risk of electric shock, personal injury, death and/

or ignition of fire. This product is intended for evaluation purposes only.

It shall be operated in a designated test area by personnel qualified

according to local requirements and labor laws to work with non-

insulated mains voltages and high-voltage circuits. This product shall

never be operated unattended.

This document describes the 160 W power supply design using the TEA2016AAT. It

contains a functional description and a set of preliminary measurements to show the

main characteristics.

1.1 TEA2016AAT

The TEA2016AAT provides high efficiency at all power levels. A high-performance cost-

effective resonant power supply can be designed. It meets the efficiency regulations of

Energy Star, the Department of Energy (DoE), the Eco-design Directive of the European

Union, the European Code of Conduct, and other guidelines.

In general, resonant converters show an excellent efficiency at high-power levels, while

at lower levels their efficiency reduces because of the relatively high magnetizing current

losses. To reach a high efficiency at all power levels, the TEA2016AAT provides a low-

power (LP) operation mode and extensive burst-mode configuration options.

Most LLC resonant converter controllers regulate the output power by adjusting the

operating frequency. The TEA2016AAT regulates the output power by adjusting the

voltage across the primary resonant capacitor. The result is accurate state control and a

linear power control.

The primary resonant capacitor voltage provides accurate information about the output

power to the controller via a voltage divider. The voltage divider sets the output power

levels. It determines when the system switches from the high-power mode to low-power

mode and when it switches from low-power mode to burst mode.

An extensive number of parameter settings define the operation modes and protections.

Protections can be stored/programmed in an internal memory. This feature provides

flexibility and ease of design. It optimizes controller properties to application-specific

requirements or even optimizes/corrects performance during power supply production.

At start-up, the IC loads the parameter settings. For easy design work during product

development, an IC version is available, which makes it possible to make setting

changes on the fly.

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aaa-030882

SNSMAINS SNSFB

SNSBOOST SNSCURLLC

SNSCURPFC SNSCAP

GND SUPIC

GATEPFC HVS

GATELS HB

HVS SUPHS

DRAINPFC GATEHS

Figure 1. TEA2016AAT pinning diagram

2 Safety warning

The 160 W power supply is connected to the mains voltage. Avoid touching the board

while it is connected to the mains voltage and when it is in operation. An isolated housing

is obligatory when used in uncontrolled, non-laboratory environments.

Galvanic isolation from the mains phase using a fixed or variable transformer is always

recommended.

019aab173

019aab174

a. Isolated b. Not isolated

Figure 2. Isolation symbols

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3 Specifications

Symbol Parameter Value Condition

Input

mains

AC mains voltage 90 V to 264 V AC

mains

mains frequency 47 Hz to 63 Hz -

i(noload)

no-load input power < 150 mW at 230 V/50 Hz

i(load=120mW)

standby power

consumption

< 260 mW at 230 V/50 Hz

i(load=240mW)

standby power

consumption

< 500 mW at 230 V/50 Hz

PF power factor

> 0.9

at 230 V/50 Hz;

maximum load

condition

Output

out

output voltage 12 V; 100 V

out

output current

5 A; 1 A

nominal current

out

maximum nominal

output power

160 W

out(ripple)

output voltage ripple

< 300 mV (p-p) at PCB end

out(p-p)

peak-to-peak out

voltage level during

dynamic load

< ±5 % 100 Hz; dynamic load

at the PCB end

holdup

hold-up time > 10 ms at 115 V/60 Hz; full

load

startup

start-up time < 500 ms at 115 V/60 Hz; full

load

rise

output voltage rising

time

< 20 ms at 115 V/60 Hz; full

load

AVG

average efficiency > 89 % average of 100 %,

75 %, 50 %, 25 %

10%

10 % load efficiency > 80 %

EMC and safety

CE conduction EMI > 3 dB full load

comp

component

temperature

see Section 5.12 at room temperature

OPP overpower protection 200 W 124 % of maximum

nominal power

short

input power during

output short

< 1 W average power

consumption without

any damage

Table 1. Design specification

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4 Board photographs

The 160 W TV design example uses the TEA2016AAT in an SO16 package. Figure 3

shows the top side and bottom side.

a. Top view

b. Bottom view

Figure 3. Design example

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5 Performance

5.1 Test facilities

• Oscilloscope: Agilent DSO9064A; Agilent DSOX3034T; Tektronix DPO7054

• AC power source: Chroma model 61502

• Electronic load: Chroma 63105; 63101

• Digital power meter: WT210

5.2 Start-up behavior

5.2.1 Start-up time

Total start-up time from mains switch-on until the output voltage reaches 12 V is

< 500 ms, regardless of mains voltages.

Conditions Specification Output condition Test result

115 V/60 Hz < 500 ms 12 V/5 A and

100 V/1 A

428 ms

Table 2. Start-up time

CH2: VOUT_12V (5 V/div)

CH3: AC mains voltage (500 V/div); Time: 100 ms/div

Figure 4. Start-up time at 115 V mains voltage, 12 V/5 A and 100 V/1 A

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5.2.2 Start-up voltage output risetime

Output voltage rising time during start-up measures the time between 0 % of nominal

output voltage and 95 % of nominal output voltage. The rising time is under 20 ms.

Conditions Specification Output condition Test result

115 V/60 Hz < 20 ms 12 V/5 A and

100 V/1 A

12 ms

Table 3. Start-up rising time

CH1: VOUT_100V (20 V/div)

CH2: VOUT_12V (5 V/div)

Time: 2 ms/div

Figure 5. Output voltage rising time at 115 V mains voltage, 12 V/5 A and 100 V/1 A

5.3 Efficiency

5.3.1 Average efficiency

Average efficiency is measured after 20 minutes aging time. The specification is based

on CoC-tier2 regulation. The output load currents for 12 V and 100 V are decreased with

the same ratio for different load conditions.

Condition Specificati

Average 25 % load 50 % load 75 % load 100 % load

115 V/60 Hz > 89 % 91.68 % 90.75 % 92.35 % 92.19 %

91.43 %

230 V/50 Hz

> 89 % 92.64 % 90.59 % 93.14 % 93.59 % 93.24 %

Table 4. Average efficiency result (measured at the PCB end)

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5.3.2 10 % load efficiency

Average efficiency is measured after 20 minutes aging time. Specification is based on

CoC-tier2 regulation. The 12 V/0.5 A and 100 V/0.1 A conditions are used for 10 % load

efficiency.

Condition Specification Measurement

condition

Efficiency

115 V/60 Hz > 80 % 85.44 %

230 V/50 Hz > 80 %

At the PCB end

85.88 %

Table 5. 10 % load efficiency (measured at the PCB end)

5.3.3 Standby power consumption

For standby power consumption measurement, 100 V output is the no-load condition.

12 V output loads specific output power.

Condition Specification Output power Input power

consumption

115 V/60 Hz < 260 mW 228 mW

230 V/50 Hz < 260 mW

120 mW

231 mW

Table 6. Standby power consumption (measured at the PCB end)

Condition Specification Output power Input power

consumption

115 V/60 Hz < 500 mW 380 mW

230 V/50 Hz < 500 mW

240 mW

382 mW

Table 7. Standby power consumption (measured at the PCB end)

5.3.4 No-load power consumption

Condition Specification Output power Input power

consumption

115 V/60 Hz < 150 mW 87 mW

230 V/50 Hz < 150 mW

no load

92 mW

Table 8. Standby power consumption (measured at the PCB end)

5.3.5 Power factor value

Condition Specification Output power Power factor value

115 V/60 Hz > 0.9 0.988

230 V/50 Hz > 0.9

12 V/5 A; 100 V/1 A

0.931

Table 9. Power factor value

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5.4 Cross regulation

Mains condition Output load at

12 V

Output load at

100 V

12 V output

voltage

100 V output

voltage

5 A 1 A 12.7 V 101 V

5 A 0.1 A 12.48 V 101.7 V

0.1 A 1 A 12.95 V 94.8 V

230 V/50 Hz

0 A 0 A 12.5 V 100 V

Table 10. Cross regulation (measured at the PCB end)

5.5 Half-bridge resonant converter operation

The TEA2016AAT incorporates a cycle-by-cycle VCAP control method. It operates

as high-power mode, low-power mode, and burst mode. The three operation modes

optimize the efficiency.

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a. High-power mode at 115 V mains voltage; 12 V/5 A

and 100 V/1 A

b. Low-power mode at 115 V mains voltage; 12 V/2 A

and 100 V/0.2 A

CH1: GATELS (10 V/div)

CH2: GATEPFC (10.2 V/div)

CH3: LLC resonant current (2.5 A/div)

Time: 20 μs/div and 10 μs/div

c. Burst mode operation at 115 V mains voltage; 12 V/0.5 A and 100 V/0.04 A

CH1: LLC resonant current (500 mA/div)

CH2: GATELS (5 V/div)

CH3: GATEPFC (5 V/div)

Time: 2 ms/div and 10 μs/div

Figure 6. Half-bridge resonant converter operation

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5.6 PFC operation

The TEA2016AAT PFC incorporates a fixed t

control method. It also contains the valley

detection function. The maximum frequency of the TEA2016AAT is 125 kHz.

a. PFC operation at 90 V mains voltage; 12 V/5 A and

100 V/1 A

b. PFC operation at 264 V mains voltage; 12 V/5 A and

100 V/1 A

CH1: PFC output voltage (50 V/div)

CH2: GATEPFC (5 V/div)

CH3: DRAINPFC (100 V/div)

Time: 5 ms/div and 5 μs/div

CH1: PFC output (50 V/div)

CH2: PFC gate (5 V/div)

CH3: DRAINPFC (100 V/div)

Time: 5 ms/div and 5 μs/div

Figure 7. PFC operation

5.7 Output voltage ripple and noise

The output voltage ripple is measured at the PCB end. To reduce spurious noise signal,

the end capacitor and ground lead of the voltage probe are removed. A 0.1 μF/50 V

ceramic capacitor and a 10 μF/50 V electrolytic capacitor are placed on the voltage

probe.

LLC operation mode Output power condition Maximum 12 V output

voltage ripple

HP mode 160 W 115 mV

LP mode 34 W 92 mV

BM mode 10 W 268 mV

Table 11. Maximum output voltage ripple and noise

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a. Maximum ripple at 115 V mains voltage; 12 V/5 A and

100 V/1 A

b. Maximum ripple at 115 V mains voltage; 12 V/2 A and

100 V/0.1 A

c. Maximum ripple at 115 V mains voltage; 12 V/0.5 A and 100 V/0.04 A

CH2: VOUT_12V (100 mV/div)

CH3: LLC resonant current (2.5 A/div and 1 A/div)

Time: 40 μs/div and 20 μs/div and 4 ms/div

Figure 8. Output voltage ripple and noise

5.8 Dynamic load response

The peak-to-peak of the output voltage during dynamic load condition is measured

at the PCB end. The output load is changed between maximum nominal load and

no load for dynamic load. The slew rate is set as 2.5 A/μs. To reduce spurious noise

signal, the end capacitor and the ground lead of the voltage probe are removed. The

0.1 μF/50 V ceramic capacitor and the 10 μF/50 V electrolytic capacitor are placed on the

voltage probe. At the same time, the condition of the output loads at 12 V and 100 V are

dynamic.

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Condition Output load

at 12 V

Output load

at 100 V

Load step

frequency

Vpk_pk

at 12 V

Vpk_pk

at 100 V

115 V/60 Hz 0 A to 5 A 0 A to 1 A 100 Hz 823 mV 5.78 V

Table 12. Output undershoot and overshoot at dynamic load

Dynamic at 115 V mains voltage with a frequency of 100 Hz

CH1: VOUT_100V (5 V/div)

CH2: VOUT_12V (500 mV/div)

CH3: IOUT_12V (5 A/div)

Time: 20 ms/div

Figure 9. Output undershoot and overshoot at dynamic load

5.9 Power-off behavior

The output voltage hold-up time is measured from the mains disconnection. The output

voltage drops to 95 % of the nominal voltage. The mains is disconnected at zero

degrees. The hold-up time is longer than 10 ms.

Condition Specification Output load Hold-up time

115 V/60 Hz > 10 ms 100 % 52 ms

Table 13. Hold-up time

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Hold-up time at 115 V mains voltage, 12 V/5 A and 100 V/1 A

CH2: VOUT_12V (5 V/div)

CH3: AC mains voltage (250 V/div)

Time: 20 ms/div

Figure 10. Power-off and hold-up time

5.10 MOSFET voltage stress

The voltage between the drain and the source requires 10 % margin from absolute

maximum ratings for each MOSFET.

Mains condition Output power

Components

Specification Result

264 V/50 Hz 160 W PFC MOSFET < 540 V 406 V

264 V/50 Hz 160 W LLC high side

MOSFET

< 540 V 408 V

264 V/50 Hz 160 W LLC low side

MOSFET

< 540 V 400 V

Table 14. MOSFET voltage stress

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a. PFC MOSFET stress at 264 V mains voltage; 12 V/5 A and 100 V/1 A

CH1: PFC MOSFET VDS (100 V/div)

Time: 20 μs/div

b. LLC MOSFET stress at 264 V mains voltage; 12 V/5 A

and 100 V/1 A

c. LLC MOSFET stress at 264 V mains voltage, 12 V/5 A

and 100 V/1 A

CH1: LLC high side MOSFET VDS (100 V/div)

Time: 20 μs/div

CH1: LLC low side MOSFET VDS (100 V/div)

Time: 20 μs/div

Figure 11. MOSFET voltage stress measurement

5.11 Protections

5.11.1 LLC overpower protection

Overpower protection is tested with increasing output current of 12 V in steps of 160 mA.

The output current of 100 V is fixed at 1 A. The restart time after an overpower protection

event is 1 s.

Condition OPP level OPP restart time

115 V/50 Hz 208.5 W 1 s

Table 15. Overpower protection level and restart time

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Overpower protection at 115 V mains

CH1: IOUT_12V (2 A/div)

CH3: VOUT_12V (5 V/div)

Time: 2 s/div

Figure 12. Overpower protection measurement

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5.11.2 Output short overcurrent protection (OCP)

The TEA2016AAT incorporates OCP protection via the SNSCURLLC pin. This OCP

protects the system from output short conditions within a short time. When SNSCURLLC

exceeds 4 V or drops to below 1 V, GATEHS or GATELS is disabled immediately to limit

the maximum resonant current. After a 5-cycle consecutive current limit, the OCP is

triggered.

Output short overcurrent protection at 115 V mains

CH1: SNSCURLLC (1 V/div)

CH2: GATELS (5 V/div)

Time: 500 μs/div and 20 μs/div

Figure 13. Output short overcurrent protection

5.11.3 Brownin/brownout protection

To avoid excessive power loss and temperature increase at very low mains voltage,

brownin/brownout protection is implemented on the TEA2016AAT. Brownin is measured

by increasing the mains voltage. Brownout is measured by decreasing the mains voltage.

Condition Output

power

Test result

Brownin level; the mains voltage is increased 160 W 72 V (AC)

Brownout level; the mains voltage is decreased 160 W 61 V (AC)

Table 16. Brownin/brownout protection level

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a. Brownin at 12 V/5 A and 100 V/1 A b. Brownout at 12 V/5 A and 100 V/1 A

CH1: AC mains voltage (100 V/div)

CH3: GATEPFC (5 V/div)

Time: 1 s/div

Figure 14. Brownin/brownout protection

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5.12 Component temperature performance

Temperature is measured at a room temperature condition.

a. Top view

b. Bottom view

Figure 15. Temperature performance at 90 V mains voltage; 12 V/5 A and 100 V/1 A

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NXP TEA2016AAT User guide

Brand: NXP

Model: TEA2016AAT

Type: User guide

NXP TEA2016AAT is a controller IC for resonant power supplies which includes a PFC. It provides high efficiency at all power levels.

It includes extra functions, like external OTP sensing and power good signal. To provide the correct handling, protections can be configured.

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NXP TEA2016AAT User guide

NXP TEA2016AAT User guide

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