NXP TEA2016AAT User guide

Brand: NXP

Model: TEA2016AAT

Type: User guide

UM11319

TEA2016DB1505 TEA2016 slim adapter design example

Rev. 1 — 17 December 2020 User manual

Document information

Information Content

Keywords TEA2016DB1505, 100 W, 19.5 V × 5.13 A, PFC, LLC, resonant controller,

burst mode, power supply, programmable settings, I2C

Abstract The TEA2016 is a controller IC for resonant power supplies. It includes power

factor correction (PFC). It provides high efficiency at all power levels.

Together with the TEA1995 dual LLC resonant SR controller, a high-

performance cost-effective resonant power supply can be designed.

To reach a high efficiency at all power levels, the TEA2016 provides a low-

power operation mode (LP) and extensive burst mode configuration options.

Most LLC resonant converter controllers regulate the output power by

adjusting the operating frequency. The TEA2016 regulates the output power

by adjusting the voltage across the primary resonant capacitor for accurate

state control and a linear power control.

Operation modes and protections can be defined by parameter settings in

an internal multitimes programmable memory. For product development, an

IC version is available to change settings on the fly. This feature provides

flexibility and ease of design to optimize controller properties to application-

specific application requirements.

The TEA2016 provides extra functions like active X-capacitor discharge,

external OTP sensing, and the power good signal. To ensure correct handling,

protections can be configured.

The efficiency at high power levels is well above 90 %. No-load power

consumption is below 100 mW. To meet the EUP lot6 standby requirement,

the input power is well below 450 mW at a 250 mW output power.

The TEA2016DB1505 design example shows a single output (19.5 V) laptop

adapter application.

NXP Semiconductors

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TEA2016DB1505 TEA2016 slim adapter design example

Rev Date Description

v.1 20201217 Initial version

Revision history

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1 Introduction

WARNING

Lethal voltage and fire ignition hazard

The non-insulated high voltages that are present when operating this

product, constitute a risk of electric shock, personal injury, death and/

or ignition of fire. This product is intended for evaluation purposes only.

It shall be operated in a designated test area by personnel qualified

according to local requirements and labor laws to work with non-

insulated mains voltages and high-voltage circuits. This product shall

never be operated unattended.

This user manual describes the TEA2016DB1505 100 W power supply design example

using the TEA2016 and the TEA1995. The user manual contains a functional description

and a set of preliminary measurements to show the main characteristics.

1.1 TEA2016

The TEA2016 provides high efficiency at all power levels. Together with the TEA1995,

a dual LLC resonant SR controller, a high-performance cost-effective resonant power

supply can be designed. The power supply designed can meet the efficiency regulations

of Energy Star, the Department of Energy (DoE), the Eco-design Directive of the

European Union, the European Code of Conduct, and other guidelines.

In general, resonant converters show an excellent efficiency at high power levels, while

at lower levels their efficiency reduces because of the relatively high magnetizing current

losses. To reach a high efficiency at all power levels, the TEA2016 provides a low-power

operation mode (LP) and extensive burst mode configuration options.

Most LLC resonant converter controllers regulate the output power by adjusting the

operating frequency. The TEA2016 regulates the output power by adjusting the voltage

across the primary resonant capacitor for accurate state control and a linear power

control.

The primary resonant capacitor voltage provides accurate information about the output

power to the controller using a voltage divider. The voltage divider sets the output power

levels. It determines when the system switches from the high-power mode to low-power

mode and when it switches from low-power mode to burst mode.

An extensive number of parameter settings for operation can define operation modes and

protections. Protections can be stored/programmed in an internal memory. This feature

provides flexibility and ease of design to optimize controller properties to application-

specific requirements or even optimize/correct performance during power supply

production. At start-up, the IC loads the parameter values for operation. For easy design

work during product development, an IC version is available to change settings on the fly.

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aaa-032979

SNSMAINS

DEVELOPMENT

VERSION

SNSFB

SNSBOOST SNSCURLLC

SNSCURPFC (SCL) SNSCAP (SDA)

GND SUPIC

GATEPFC SDA

GATELS HB

SCL SUPHS

DRAINPFC GATEHS

Figure 1. TEA2016AAT (development version) pinning

Note: The TEA2016DB1505 design example contains the development version.

1.2 TEA1995

The TEA1995 is a synchronous rectifier (SR) controller IC for LLC switched-mode power

supplies. It incorporates an adaptive gate drive method for maximum efficiency at any

load.

The TEA1995 is a dedicated controller IC for synchronous rectification on the secondary

side of resonant converters. It includes two driver stages for driving the SR MOSFETs,

which rectify the outputs of the central-tap secondary transformer windings.

The two-gate driver stages have their own sensing inputs and operate independently.

GDB GDA

GND V

DSB DSA

SSB SSA

aaa-016990

Figure 2. TEA1995 pinning

1.3 TEA2016 GUI and USB-I

C interface

In addition to the normal TEA2016 ICs, NXP Semiconductors provides special IC

versions for product development. The difference is that the development IC samples

provide a second I

C interface for easy modification of settings while the IC is operating,

changing operation “on the fly”. The prototype TEA2016DB1505 design example

contains the development version of the TEA2016.

1.3.1 Development IC samples: SDA and SCL on spacer pins

Connections to the second I

C interface of the IC are provided on the pins that are

normally not connected, high-voltage spacer pins 7 and 12. The basic I

C interface

functions in the IC on the combined function pins are available on development samples.

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aaa-035741

Mains-L

Mains-N

GATEPFC

SNSMAINS

GND

SUPIC

SNSFB

DRAINPFC

SNSBOOST

TEA2016

GATELS

ground

SCL

SDA

USB

Vboost

SNSCUR

SETTING

SUPIC

SUPHS

SENSE

USB-I

interface

SNSCURLLC

SNSCAP

GATELS

GATEHS

SUPHS

Vout (DC)

SNSCURPFC

Figure 3. Development IC: I

C connections with spacer pins

1.3.2 Production IC samples: SDA and SCL on combined pins

The basic I

C interface in the IC is available on the combined pins SNSCURPFC (SCL)

and SNSCAP (SDA). To program the IC, the IC must be put in the disabled condition,

pulling SNSBOOST to GND. During programming, SUPIC must supply the IC.

Figure 4. Two TEA2016 programming setups: on the fly and standalone

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2 Safety warning

The TEA2016DB1505 design example must be connected to mains voltage. Avoid

touching the TEA2016DB1505 design example while it is connected to the mains

voltage. An isolated housing is obligatory when used in uncontrolled, non-laboratory

environments. Galvanic isolation of the mains phase using a variable transformer is

always recommended. Figure 5 shows the symbols that identify the isolated and non-

isolated devices.

019aab173

019aab174

a. Isolated b. Not isolated

Figure 5. Isolation symbols

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3 Specifications

Symbol Description Value Conditions

Input

mains

AC mains voltage 90 V to 264 V AC

mains

mains frequency 47 Hz to 63 Hz

i(noload)

no-load input power < 100 mW at 230 V/50 Hz

i(load-250mW)

standby power

consumption

< 450 mW at 230 V/50 Hz;

out

= 250 mW

Output

output voltage 19.5 V

output current 0 A to 5.13 A nominal current

o(max)

maximum output power 6.36 A with OPP

out(pk-pk)

output voltage peak-to-

peak

< ±5 % 10 Hz; 100 Hz; 1000 Hz

dynamic load at the PCB

end

hold

hold time > 10 ms at 115 V/60 Hz; full load

start

start time < 500 ms at 115 V/60 Hz; full load

average efficiency > 89 % average according to

CoC-tier2

10%

10 % load efficiency > 80 % according to CoC-tier2

EMC and safety

CE conduction EMI < −3 dB at maximum nominal load

comp

components temperature See temperature section at room temperature

dch(xcap)

X-capacitor discharge

time

< 1 s (to 57 V) at 230 V/60 Hz; no load

Table 1. TEA2016DB1505 design example specification

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4 Design example photographs

a. Top view

b. Bottom view

c. Side view

Figure 6. TEA2016DB1505 design examples photographs

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5 Performance measurements

5.1 Test facilities

• Oscilloscope: Agilent Technologies DSO9064A

• AC power source: Chroma 61504

• Electronic load: Chroma 63600-2

• Digital power meter: Fluke 15B

5.2 Start-up behavior

5.2.1 Output voltage rising time

The output voltage rising time during start-up measures the duration between 0 % and

90 % of nominal output voltage. The rising time is < 20 ms.

Condition Specification Output power Test result

115 V/60 Hz < 20 ms 100 W 10.0 ms

230 V/50 Hz < 20 ms 100 W 10.3 ms

Table 2. Output voltage rising time

a. 115 V mains/nominal maximum load b. 230 V mains/nominal maximum load

CH1: PFC gate (5 V/div)

CH2: Half-bridge voltage (200 V/div)

CH3: V

out

(5 V/div)

CH4: I

out

(2 A/div)

Time: 5 ms

Figure 7. Output voltage rising time

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5.2.2 Start-up time

The total start-up time from mains switch-on until the output voltage reaches 19.5 V is

< 500 ms regardless of AC mains voltage conditions.

Condition Specification Output power Test result

115 V/60 Hz < 500 ms 100 W 200 ms

230 V/50 Hz < 500 ms 100 W 205 ms

Table 3. Start-up time

a. 115 V mains/nominal maximum load b. 230 V mains/nominal maximum load

CH2: V

out

(5 V/div)

CH3: V

SUPIC

(5 V/div)

CH4: I

out

(2 A/div)

Time: 50 ms/div

Figure 8. Start-up time

5.3 Efficiency

5.3.1 Average efficiency

Average efficiency is measured after 20 minutes aging time.

Condition Specification Average 25 % load 50 % load 75 % load 100 % load

115 V/60 Hz > 89 % 92.17 % 89.57 % 92.62 % 93.26 % 93.24 %

230 V/50 Hz > 89 % 93.54 % 90.64 % 93.91 % 94.72 % 94.91 %

Table 4. Average efficiency result (measured at the PCB end)

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Condition Specification Average 25 % load 50 % load 75 % load 100 % load

115 V/60 Hz > 89 % 91.00 % 89.11 % 91.68 % 91.84 % 91.35 %

230 V/50 Hz > 89 % 92.35 % 90.18 % 92.96 % 93.28 % 92.98 %

Table 5. Average efficiency result (measured at the 1.8 M/18 AWG cable end)

5.3.2 10 % load efficiency

Condition Specification Measurement

condition

Efficiency

115 V/60 Hz > 80 % 81.95 %

230 V/50 Hz > 80 %

At the PCB end

83.03 %

Table 6. Output voltage and 10 % load efficiency (measured at the PCB end)

Condition Specification Measurement

condition

Efficiency

115 V/60 Hz > 80 % 81.78 %

230 V/50 Hz > 80 %

At the 1.8 M/18 AWG

cable end

82.87 %

Table 7. Output voltage and 10 % load efficiency (measured at the 1.8 M/18 AWG cable

end)

5.3.3 Standby power consumption

Condition Specification Output power Input power

consumption

115 V/60 Hz < 450 mW 250 mW 434 mW

230 V/50 Hz < 450 mW 250 mW 421 mW

Table 8. Standby power consumption (measured at the PCB end)

5.3.4 No-load power consumption

Condition Specification Output power Input power

consumption

115 V/60 Hz < 100 mW no load 69 mW

230 V/50 Hz < 100 mW no load 78 mW

Table 9. No-load power consumption (measured at the PCB end)

5.3.5 Power factor

Condition Specification Output power Input power

consumption

115 V/60 Hz > 0.9 100 W 0.984

230 V/50 Hz > 0.9 100 W 0.923

Table 10. Power factor correction

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5.4 Half-bridge resonant converter operation

a. High-power mode operation b. Low-power mode operation

CH1: PFC gate (5 V/div)

CH2: Resonant capacitor voltage (50.3 V/div)

CH3: Half-bridge voltage (200 V/div)

CH4: V

OUT

(5 V/div)

Time: 20 ms and 10 μs

c. Burst mode operation

CH1: PFC gate (5 V/div)

CH2: Resonant capacitor voltage (10 V/div)

CH3: Half-bridge voltage (200 V/div)

CH4: V

OUT

(5 V/div)

Time: 5 ms and 500 μs

Figure 9. Half-bridge resonant converter operation

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5.5 LLC operation mode transitions

CH1: PFC gate (5 V/div)

CH2: Half-bridge voltage (200 V/div)

CH3: V

out

(100 mV/div)

CH4: I

out

(1 A/div)

Time: 2 s

Figure 10. Mode transition waveform: BM-LP-HP-LP-BM

Transition Output power

HP → LP 27.50 W

LP → BM 8.00 W

BM → LP 8.00 W

LP → HP 31.40 W

Table 11. LLC operation mode transition power Level

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5.6 PFC operation

a. PFC maximum nominal load operation at 230 V b. PFC burst mode at 230 V

CH1: PFC gate (5 V/div)

CH2: DRAINPFC (200 V/div)

CH3: PFC output voltage (50.3 V/div)

CH4: I

out

(2 A/div)

Time: 5 ms and 5 μs

CH1: PFC gate (5 V/div)

CH2: DRAINPFC (200 V/div)

CH3: PFC output voltage (50.3 V/div)

CH4: I

out

(2 A/div)

Time: 20 ms and 5 μs

Figure 11. PFC operation waveform

5.7 Output voltage ripple and noise

The output voltage ripple is measured at the 1.8 M/18 AWG cable end. To reduce

spurious noise signal, the end cap and ground lead of the voltage probe are removed.

The 0.1 μF/50 V ceramic capacitor and the 10 μF/50 V electrolytic capacitor are placed

on the voltage probe.

At the output power of each operation mode, there is a maximum output ripple.

Operation mode Output power Maximum output voltage

ripple

HP mode 100 W 164 mV

LP mode 23.60 W 150 mV

BM mode 4.49 W 223 mV

Table 12. Output voltage ripple and noise

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a. Maximum ripple and noise at high-power mode b. Maximum ripple and noise at low-power mode

c. Maximum ripple and noise at burst mode

CH1: V

out

(50 mV/div)

Time: 10 ms and 1 ms

Figure 12. Output voltage ripple and noise

5.8 Dynamic load response

The undershoot and the overshoot of the output voltage during dynamic load condition

is measured at the PCB end. For dynamic load, the output load is changed between

maximum nominal load and no load. The slew rate is set as 2.5 A/μsec. The four different

periods of each step are tested (see Table 13). To reduce spurious noise signal, the end

cap and the ground lead of the voltage probe are removed. The 0.1 μF/50 V ceramic

capacitor and 10 μF/50 V electrolytic capacitor are placed on the voltage probe.

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Condition Output load Load step frequency Undershoot/overshoot

115 V/60 Hz 19.01 V/19.78 V

230 V/50 Hz

10 Hz

19.03 V/19.79 V

115 V/60 Hz 18.88 V/19.76 V

230 V/50 Hz

100 Hz

18.86 V/19.77 V

115 V/60 Hz 18.83 V/19.82 V

230 V/50 Hz

0 % to 100 %

1000 Hz

18.83 V/19.81 V

Table 13. Output undershoot and output overshoot at load steps

a. 115 V b. 230 V

CH3: V

out

(1 V/div)

CH4: I

out

(2 A/div)

Time: 50 ms and 1.98 ms

Figure 13. Dynamic load response - at 10 Hz step load

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a. 115 V b. 230 V

CH3: V

out

(1 V/div)

CH4: I

out

(2 A/div)

Time: 50 ms and 0.45 ms

Figure 14. Dynamic load response - at 100 Hz step load

a. 115 V b. 230 V

CH3: V

out

(1 V/div)

CH4: I

out

(2 A/div)

Time: 50 ms and 0.5 ms

Figure 15. Dynamic load response - at 1000 Hz step load

5.9 Power-off behavior

The output voltage hold-up time is measured from mains disconnection until the output

voltage has dropped to 95 % of the nominal voltage. Mains is disconnected at zero

degrees. The hold-up time is > 10 ms.

Condition Specification Output load Hold-up time

115 V/60 Hz > 10 ms 100 % 28 ms

Table 14. Hold-up time

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CH1: V

bulk

(50 V/div)

CH2: AC mains (100 V/div)

CH3: V

out

(5 V/div)

CH4: I

out

(2 A/div)

Time: 5 ms

Figure 16. Power-off and hold-up time

5.10 X-capacitor discharge behavior

For safety, the X-capacitor placed on the mains line must be discharged within 1 s.

The regulation requires to discharge to 37 % within 1 s or 60 V within 2 s. TEA2016

implements the discharge function via the DRAINPFC pin. It can satisfy regulations. The

X-capacitor is discharged to zero voltage within 1 s.

Since the impedance of a differential probe discharges capacitor, it cannot measure

the exact discharge time using the by X-capacitor discharge function of the TEA2016.

A 20 MΩ resistor is connected in series with the differential probe. To measure the

discharge time, the differential probe is connected in parallel with the X-capacitor

(CX101).

Condition Output load X-capacitor discharge time

264 V/50 Hz no load 249 ms

Table 15. X-capacitor discharge time

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CH4: Voltage on X-capacitor (200 V/div)

Time: 100 ms

Figure 17. X-capacitor discharge time measurement

5.11 MOSFET voltage stress

The voltage between drain and source requires a 10 % margin from the absolute

maximum ratings for each MOSFET. To check the worst case stress, this voltage is

measured at the dynamic load condition.

Mains condition Output load MOSFET Specification Result

264 V/50 Hz dynamic PFC MOSFET < 540 V 427 V

264 V/50 Hz dynamic LLC high-side

MOSFET

< 540 V 432 V

264 V/50 Hz dynamic LLC low-side

MOSFET

< 540 V 431 V

Table 16. MOSFET voltage stress

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a. PFC MOSFET stress during dynamic load

b. LLC high-side MOSFET stress during dynamic load c. LLC low-side MOSFET stress during dynamic load

CH2: I

out

(2 A/div)

CH4: V

(100 V/div)

Time: 5 ms

Figure 18. MOSFET voltage stress measurement

5.12 SUPIC operating voltage

The auxiliary winding of LLC transformer supplies the SUPIC voltage. The SUPIC voltage

depends on the output load condition. The minimum level must be > V

low(SUPIC)

. The

maximum level must be < V

O(ovp)SUPIC

Mains condition Output load Result

90 V/60 Hz 100 W 19.2 V

90 V/60 Hz no load 15.8 V

264 V/50 Hz 100 W 19.4 V

264 V/50 Hz no load 16.8 V

Table 17. SUPIC operating voltage range

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NXP TEA2016AAT User guide

NXP TEA2016AAT User guide

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