NXP K50_100 Reference guide

K50 Sub-Family Reference Manual

Supports: MK50DX256ZCLL10, MK50DN512ZCLL10

Document Number: K50P100M100SF2RM

Rev. 6, Nov 2011

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Contents

Section Number Title Page

Chapter 1

About This Document

1.1 Overview.......................................................................................................................................................................53

1.1.1 Purpose.........................................................................................................................................................53

1.1.2 Audience......................................................................................................................................................53

1.2 Conventions..................................................................................................................................................................53

1.2.1 Numbering systems......................................................................................................................................53

1.2.2 Typographic notation...................................................................................................................................54

1.2.3 Special terms................................................................................................................................................54

Chapter 2

Introduction

2.1 Overview.......................................................................................................................................................................55

2.2 K50 Family Introduction...............................................................................................................................................55

2.3 Module Functional Categories......................................................................................................................................55

2.3.1 ARM Cortex-M4 Core Modules..................................................................................................................57

2.3.2 System Modules...........................................................................................................................................57

2.3.3 Memories and Memory Interfaces...............................................................................................................58

2.3.4 Clocks...........................................................................................................................................................59

2.3.5 Security and Integrity modules....................................................................................................................59

2.3.6 Analog modules...........................................................................................................................................60

2.3.7 Timer modules.............................................................................................................................................60

2.3.8 Communication interfaces...........................................................................................................................62

2.3.9 Human-machine interfaces..........................................................................................................................62

2.4 Orderable part numbers.................................................................................................................................................63

Chapter 3

Chip Configuration

3.1 Introduction...................................................................................................................................................................65

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3.2 Core modules................................................................................................................................................................65

3.2.1 ARM Cortex-M4 Core Configuration..........................................................................................................65

3.2.2 Nested Vectored Interrupt Controller (NVIC) Configuration......................................................................68

3.2.3 Asynchronous Wake-up Interrupt Controller (AWIC) Configuration.........................................................74

3.2.4 JTAG Controller Configuration...................................................................................................................75

3.3 System modules............................................................................................................................................................76

3.3.1 SIM Configuration.......................................................................................................................................76

3.3.2 Mode Controller Configuration...................................................................................................................77

3.3.3 PMC Configuration......................................................................................................................................77

3.3.4 Low-Leakage Wake-up Unit (LLWU) Configuration.................................................................................78

3.3.5 MCM Configuration....................................................................................................................................80

3.3.6 Crossbar Switch Configuration....................................................................................................................80

3.3.7 Memory Protection Unit (MPU) Configuration...........................................................................................83

3.3.8 Peripheral Bridge Configuration..................................................................................................................85

3.3.9 DMA request multiplexer configuration......................................................................................................87

3.3.10 DMA Controller Configuration...................................................................................................................90

3.3.11 External Watchdog Monitor (EWM) Configuration....................................................................................91

3.3.12 Watchdog Configuration..............................................................................................................................92

3.4 Clock Modules..............................................................................................................................................................93

3.4.1 MCG Configuration.....................................................................................................................................93

3.4.2 OSC Configuration......................................................................................................................................94

3.4.3 RTC OSC configuration...............................................................................................................................95

3.5 Memories and Memory Interfaces................................................................................................................................95

3.5.1 Flash Memory Configuration.......................................................................................................................95

3.5.2 Flash Memory Controller Configuration.....................................................................................................99

3.5.3 SRAM Configuration...................................................................................................................................100

3.5.4 SRAM Controller Configuration.................................................................................................................103

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3.5.5 System Register File Configuration.............................................................................................................104

3.5.6 VBAT Register File Configuration..............................................................................................................105

3.5.7 EzPort Configuration...................................................................................................................................106

3.5.8 FlexBus Configuration.................................................................................................................................107

3.6 Security.........................................................................................................................................................................110

3.6.1 CRC Configuration......................................................................................................................................110

3.6.2 DryIce (tamper detect and secure storage) configuration............................................................................111

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3.7 Analog...........................................................................................................................................................................112

3.7.1 16-bit SAR ADC with PGA Configuration.................................................................................................112

3.7.2 CMP Configuration......................................................................................................................................119

3.7.3 12-bit DAC Configuration...........................................................................................................................121

3.7.4 Op-amp Configuration.................................................................................................................................122

3.7.5 TRIAMP Configuration...............................................................................................................................124

3.7.6 VREF Configuration....................................................................................................................................125

3.8 Timers...........................................................................................................................................................................126

3.8.1 PDB Configuration......................................................................................................................................126

3.8.2 FlexTimer Configuration.............................................................................................................................130

3.8.3 PIT Configuration........................................................................................................................................133

3.8.4 Low-power timer configuration...................................................................................................................134

3.8.5 CMT Configuration......................................................................................................................................136

3.8.6 RTC configuration.......................................................................................................................................137

3.9 Communication interfaces............................................................................................................................................138

3.9.1 Universal Serial Bus (USB) Subsystem.......................................................................................................138

3.9.2 SPI configuration.........................................................................................................................................143

3.9.3 I2C Configuration........................................................................................................................................146

3.9.4 UART Configuration...................................................................................................................................147

3.9.5 SDHC Configuration....................................................................................................................................149

3.9.6 I2S configuration..........................................................................................................................................150

3.10 Human-machine interfaces (HMI)................................................................................................................................152

3.10.1 GPIO configuration......................................................................................................................................152

3.10.2 TSI Configuration........................................................................................................................................153

Chapter 4

Memory Map

4.1 Introduction...................................................................................................................................................................157

4.2 System memory map.....................................................................................................................................................157

4.2.1 Aliased bit-band regions..............................................................................................................................158

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4.3 Flash Memory Map.......................................................................................................................................................159

4.3.1 Alternate Non-Volatile IRC User Trim Description....................................................................................160

4.4 SRAM memory map.....................................................................................................................................................161

4.5 Peripheral bridge (AIPS-Lite0 and AIPS-Lite1) memory maps...................................................................................161

4.5.1 Peripheral Bridge 0 (AIPS-Lite 0) Memory Map........................................................................................161

4.5.2 Peripheral Bridge 1 (AIPS-Lite 1) Memory Map........................................................................................165

4.6 Private Peripheral Bus (PPB) memory map..................................................................................................................170

Chapter 5

Clock Distribution

5.1 Introduction...................................................................................................................................................................171

5.2 Programming model......................................................................................................................................................171

5.3 High-Level device clocking diagram............................................................................................................................171

5.4 Clock definitions...........................................................................................................................................................172

5.4.1 Device clock summary.................................................................................................................................173

5.5 Internal clocking requirements.....................................................................................................................................175

5.5.1 Clock divider values after reset....................................................................................................................176

5.5.2 VLPR mode clocking...................................................................................................................................176

5.6 Clock Gating.................................................................................................................................................................176

5.7 Module clocks...............................................................................................................................................................177

5.7.1 PMC 1-kHz LPO clock................................................................................................................................178

5.7.2 WDOG clocking..........................................................................................................................................179

5.7.3 Debug trace clock.........................................................................................................................................179

5.7.4 PORT digital filter clocking.........................................................................................................................179

5.7.5 LPTMR clocking..........................................................................................................................................180

5.7.6 USB FS OTG Controller clocking...............................................................................................................180

5.7.7 UART clocking............................................................................................................................................181

5.7.8 SDHC clocking............................................................................................................................................181

5.7.9 I2S clocking.................................................................................................................................................182

5.7.10 TSI clocking.................................................................................................................................................182

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Chapter 6

Reset and Boot

6.1 Introduction...................................................................................................................................................................185

6.2 Reset..............................................................................................................................................................................185

6.2.1 Power-on reset (POR)..................................................................................................................................186

6.2.2 System resets................................................................................................................................................186

6.2.3 Debug resets.................................................................................................................................................189

6.3 Boot...............................................................................................................................................................................191

6.3.1 Boot sources.................................................................................................................................................191

6.3.2 Boot options.................................................................................................................................................191

6.3.3 FOPT boot options.......................................................................................................................................191

6.3.4 Boot sequence..............................................................................................................................................192

Chapter 7

Power Management

7.1 Introduction...................................................................................................................................................................195

7.2 Power modes.................................................................................................................................................................195

7.3 Entering and exiting power modes...............................................................................................................................197

7.4 Power mode transitions.................................................................................................................................................198

7.5 Power modes shutdown sequencing.............................................................................................................................199

7.6 Module Operation in Low Power Modes......................................................................................................................199

7.7 Clock Gating.................................................................................................................................................................202

Chapter 8

Security

8.1 Introduction...................................................................................................................................................................203

8.2 Flash Security...............................................................................................................................................................203

8.3 Security Interactions with other Modules.....................................................................................................................204

8.3.1 Security interactions with FlexBus..............................................................................................................204

8.3.2 Security Interactions with EzPort................................................................................................................204

8.3.3 Security Interactions with Debug.................................................................................................................204

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Chapter 9

Debug

9.1 Introduction...................................................................................................................................................................207

9.1.1 References....................................................................................................................................................209

9.2 The Debug Port.............................................................................................................................................................209

9.2.1 JTAG-to-SWD change sequence.................................................................................................................210

9.2.2 JTAG-to-cJTAG change sequence...............................................................................................................210

9.3 Debug Port Pin Descriptions.........................................................................................................................................211

9.4 System TAP connection................................................................................................................................................211

9.4.1 IR Codes.......................................................................................................................................................211

9.5 JTAG status and control registers.................................................................................................................................212

9.5.1 MDM-AP Control Register..........................................................................................................................213

9.5.2 MDM-AP Status Register............................................................................................................................215

9.6 Debug Resets................................................................................................................................................................216

9.7 AHB-AP........................................................................................................................................................................217

9.8 ITM...............................................................................................................................................................................218

9.9 Core Trace Connectivity...............................................................................................................................................218

9.10 Embedded Trace Macrocell v3.5 (ETM)......................................................................................................................218

9.11 Coresight Embedded Trace Buffer (ETB)....................................................................................................................219

9.11.1 Performance Profiling with the ETB...........................................................................................................219

9.11.2 ETB Counter Control...................................................................................................................................220

9.12 TPIU..............................................................................................................................................................................220

9.13 DWT.............................................................................................................................................................................220

9.14 Debug in Low Power Modes........................................................................................................................................221

9.14.1 Debug Module State in Low Power Modes.................................................................................................222

9.15 Debug & Security.........................................................................................................................................................222

Chapter 10

Signal Multiplexing and Signal Descriptions

10.1 Introduction...................................................................................................................................................................223

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10.2 Signal Multiplexing Integration....................................................................................................................................223

10.2.1 Port control and interrupt module features..................................................................................................224

10.2.2 Clock gating.................................................................................................................................................224

10.2.3 Signal multiplexing constraints....................................................................................................................224

10.3 Pinout............................................................................................................................................................................224

10.3.1 K50 Signal Multiplexing and Pin Assignments...........................................................................................225

10.3.2 K50 Pinouts..................................................................................................................................................229

10.4 Module Signal Description Tables................................................................................................................................230

10.4.1 Core Modules...............................................................................................................................................231

10.4.2 System Modules...........................................................................................................................................231

10.4.3 Clock Modules.............................................................................................................................................232

10.4.4 Memories and Memory Interfaces...............................................................................................................232

10.4.5 Security Modules.........................................................................................................................................233

10.4.6 Analog..........................................................................................................................................................234

10.4.7 Communication Interfaces...........................................................................................................................236

10.4.8 Human-Machine Interfaces (HMI)..............................................................................................................240

Chapter 11

Port control and interrupts (PORT)

11.1 Introduction...................................................................................................................................................................241

11.1.1 Overview......................................................................................................................................................241

11.1.2 Features........................................................................................................................................................241

11.1.3 Modes of operation......................................................................................................................................242

11.2 External signal description............................................................................................................................................243

11.3 Detailed signal descriptions..........................................................................................................................................243

11.4 Memory map and register definition.............................................................................................................................243

11.4.1 Pin Control Register n (PORTx_PCRn).......................................................................................................250

11.4.2 Global Pin Control Low Register (PORTx_GPCLR)..................................................................................252

11.4.3 Global Pin Control High Register (PORTx_GPCHR).................................................................................253

11.4.4 Interrupt Status Flag Register (PORTx_ISFR)............................................................................................253

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11.4.5 Digital Filter Enable Register (PORTx_DFER)...........................................................................................254

11.4.6 Digital Filter Clock Register (PORTx_DFCR)............................................................................................255

11.4.7 Digital Filter Width Register (PORTx_DFWR)..........................................................................................255

11.5 Functional description...................................................................................................................................................256

11.5.1 Pin control....................................................................................................................................................256

11.5.2 Global pin control........................................................................................................................................256

11.5.3 External interrupts........................................................................................................................................257

11.5.4 Digital filter..................................................................................................................................................258

Chapter 12

System integration module (SIM)

12.1 Introduction...................................................................................................................................................................259

12.1.1 Features........................................................................................................................................................259

12.1.2 Modes of operation......................................................................................................................................259

12.1.3 SIM Signal Descriptions..............................................................................................................................260

12.2 Memory map and register definition.............................................................................................................................260

12.2.1 System Options Register 1 (SIM_SOPT1)..................................................................................................262

12.2.2 System Options Register 2 (SIM_SOPT2)..................................................................................................264

12.2.3 System Options Register 4 (SIM_SOPT4)..................................................................................................266

12.2.4 System Options Register 5 (SIM_SOPT5)..................................................................................................269

12.2.5 System Options Register 6 (SIM_SOPT6)..................................................................................................270

12.2.6 System Options Register 7 (SIM_SOPT7)..................................................................................................271

12.2.7 System Device Identification Register (SIM_SDID)...................................................................................273

12.2.8 System Clock Gating Control Register 1 (SIM_SCGC1)............................................................................274

12.2.9 System Clock Gating Control Register 2 (SIM_SCGC2)............................................................................275

12.2.10 System Clock Gating Control Register 3 (SIM_SCGC3)............................................................................276

12.2.11 System Clock Gating Control Register 4 (SIM_SCGC4)............................................................................277

12.2.12 System Clock Gating Control Register 5 (SIM_SCGC5)............................................................................280

12.2.13 System Clock Gating Control Register 6 (SIM_SCGC6)............................................................................282

12.2.14 System Clock Gating Control Register 7 (SIM_SCGC7)............................................................................284

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12.2.15 System Clock Divider Register 1 (SIM_CLKDIV1)...................................................................................285

12.2.16 System Clock Divider Register 2 (SIM_CLKDIV2)...................................................................................288

12.2.17 Flash Configuration Register 1 (SIM_FCFG1)...........................................................................................289

12.2.18 Flash Configuration Register 2 (SIM_FCFG2)...........................................................................................291

12.2.19 Unique Identification Register High (SIM_UIDH).....................................................................................292

12.2.20 Unique Identification Register Mid-High (SIM_UIDMH)..........................................................................293

12.2.21 Unique Identification Register Mid Low (SIM_UIDML)...........................................................................293

12.2.22 Unique Identification Register Low (SIM_UIDL)......................................................................................294

12.3 Functional description...................................................................................................................................................294

Chapter 13

Mode Controller

13.1 Introduction...................................................................................................................................................................295

13.1.1 Features........................................................................................................................................................295

13.1.2 Modes of Operation.....................................................................................................................................295

13.1.3 MCU Reset...................................................................................................................................................306

13.2 Mode Control Memory Map/Register Definition.........................................................................................................309

13.2.1 System Reset Status Register High (MC_SRSH)........................................................................................310

13.2.2 System Reset Status Register Low (MC_SRSL).........................................................................................311

13.2.3 Power Mode Protection Register (MC_PMPROT).....................................................................................312

13.2.4 Power Mode Control Register (MC_PMCTRL)..........................................................................................314

Chapter 14

Power Management Controller

14.1 Introduction...................................................................................................................................................................317

14.2 Features.........................................................................................................................................................................317

14.3 Low-Voltage Detect (LVD) System.............................................................................................................................317

14.3.1 LVD Reset Operation...................................................................................................................................318

14.3.2 LVD Interrupt Operation.............................................................................................................................318

14.3.3 Low-Voltage Warning (LVW) Interrupt Operation.....................................................................................318

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14.4 PMC Memory Map/Register Definition.......................................................................................................................319

14.4.1 Low Voltage Detect Status and Control 1 Register (PMC_LVDSC1)........................................................319

14.4.2 Low Voltage Detect Status and Control 2 Register (PMC_LVDSC2)........................................................320

14.4.3 Regulator Status and Control Register (PMC_REGSC)..............................................................................322

Chapter 15

Low-leakage wake-up unit (LLWU)

15.1 Introduction...................................................................................................................................................................325

15.1.1 Features........................................................................................................................................................326

15.1.2 Modes of operation......................................................................................................................................326

15.1.3 Block diagram..............................................................................................................................................327

15.2 LLWU Signal Descriptions...........................................................................................................................................328

15.3 Memory map/register definition...................................................................................................................................329

15.3.1 LLWU Pin Enable 1 Register (LLWU_PE1)..............................................................................................329

15.3.2 LLWU Pin Enable 2 Register (LLWU_PE2)..............................................................................................330

15.3.3 LLWU Pin Enable 3 Register (LLWU_PE3)..............................................................................................332

15.3.4 LLWU Pin Enable 4 Register (LLWU_PE4)..............................................................................................333

15.3.5 LLWU Module Enable Register (LLWU_ME)...........................................................................................334

15.3.6 LLWU Flag 1 Register (LLWU_F1)...........................................................................................................335

15.3.7 LLWU Flag 2 Register (LLWU_F2)...........................................................................................................337

15.3.8 LLWU Flag 3 Register (LLWU_F3)...........................................................................................................339

15.3.9 LLWU Control and Status Register (LLWU_CS).......................................................................................340

15.4 Functional description...................................................................................................................................................341

15.4.1 LLS mode.....................................................................................................................................................342

15.4.2 VLLS modes................................................................................................................................................342

15.4.3 Initialization.................................................................................................................................................343

15.4.4 Low power mode recovery..........................................................................................................................343

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Chapter 16

Miscellaneous Control Module (MCM)

16.1 Introduction...................................................................................................................................................................345

16.1.1 Features........................................................................................................................................................345

16.2 Memory Map/Register Descriptions.............................................................................................................................345

16.2.1 Crossbar switch (AXBS) slave configuration (MCM_PLASC)..................................................................346

16.2.2 Crossbar switch (AXBS) master configuration (MCM_PLAMC)..............................................................346

16.2.3 SRAM arbitration and protection (MCM_SRAMAP).................................................................................347

16.2.4 Interrupt status register (MCM_ISR)...........................................................................................................348

16.2.5 ETB counter control register (MCM_ETBCC)...........................................................................................349

16.2.6 ETB reload register (MCM_ETBRL)..........................................................................................................350

16.2.7 ETB counter value register (MCM_ETBCNT)...........................................................................................351

16.3 Functional Description..................................................................................................................................................351

16.3.1 Interrupts......................................................................................................................................................351

Chapter 17

Crossbar Switch (AXBS)

17.1 Introduction...................................................................................................................................................................353

17.1.1 Features........................................................................................................................................................353

17.2 Memory Map / Register Definition...............................................................................................................................354

17.2.1 Priority Registers Slave (AXBS_PRSn)......................................................................................................355

17.2.2 Control Register (AXBS_CRSn).................................................................................................................358

17.2.3 Master General Purpose Control Register (AXBS_MGPCRn)...................................................................360

17.3 Functional Description..................................................................................................................................................361

17.3.1 General operation.........................................................................................................................................361

17.3.2 Register coherency.......................................................................................................................................362

17.3.3 Arbitration....................................................................................................................................................362

17.4 Initialization/application information...........................................................................................................................365

Chapter 18

Memory Protection Unit (MPU)

18.1 Introduction...................................................................................................................................................................367

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18.2 Overview.......................................................................................................................................................................367

18.2.1 Block Diagram.............................................................................................................................................367

18.2.2 Features........................................................................................................................................................368

18.3 Memory Map/Register Definition.................................................................................................................................369

18.3.1 Control/Error Status Register (MPU_CESR)..............................................................................................372

18.3.2 Error Address Register, Slave Port n (MPU_EARn)...................................................................................374

18.3.3 Error Detail Register, Slave Port n (MPU_EDRn)......................................................................................375

18.3.4 Region Descriptor n, Word 0 (MPU_RGDn_WORD0)..............................................................................376

18.3.5 Region Descriptor n, Word 1 (MPU_RGDn_WORD1)..............................................................................377

18.3.6 Region Descriptor n, Word 2 (MPU_RGDn_WORD2)..............................................................................377

18.3.7 Region Descriptor n, Word 3 (MPU_RGDn_WORD3)..............................................................................380

18.3.8 Region Descriptor Alternate Access Control n (MPU_RGDAACn)...........................................................381

18.4 Functional Description..................................................................................................................................................383

18.4.1 Access Evaluation Macro.............................................................................................................................383

18.4.2 Putting It All Together and Error Terminations...........................................................................................384

18.4.3 Power Management......................................................................................................................................385

18.5 Initialization Information..............................................................................................................................................385

18.6 Application Information................................................................................................................................................385

Chapter 19

Peripheral Bridge (AIPS-Lite)

19.1 Introduction...................................................................................................................................................................389

19.1.1 Features........................................................................................................................................................389

19.1.2 General operation.........................................................................................................................................389

19.2 Memory map/register definition...................................................................................................................................390

19.2.1 Master Privilege Register A (AIPSx_MPRA).............................................................................................391

19.2.2 Peripheral Access Control Register (AIPSx_PACRn).................................................................................395

19.2.3 Peripheral Access Control Register (AIPSx_PACRn).................................................................................400

19.3 Functional Description..................................................................................................................................................405

19.3.1 Access support.............................................................................................................................................405

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Chapter 20

Direct memory access multiplexer (DMAMUX)

20.1 Introduction...................................................................................................................................................................407

20.1.1 Overview......................................................................................................................................................407

20.1.2 Features........................................................................................................................................................408

20.1.3 Modes of operation......................................................................................................................................408

20.2 External signal description............................................................................................................................................409

20.3 Memory map/register definition...................................................................................................................................409

20.3.1 Channel Configuration Register (DMAMUX_CHCFGn)...........................................................................410

20.4 Functional description...................................................................................................................................................411

20.4.1 DMA channels with periodic triggering capability......................................................................................411

20.4.2 DMA channels with no triggering capability...............................................................................................414

20.4.3 "Always enabled" DMA sources.................................................................................................................414

20.5 Initialization/application information...........................................................................................................................415

20.5.1 Reset.............................................................................................................................................................415

20.5.2 Enabling and configuring sources................................................................................................................415

Chapter 21

Direct Memory Access Controller (eDMA)

21.1 Introduction...................................................................................................................................................................419

21.1.1 Block diagram..............................................................................................................................................419

21.1.2 Block parts...................................................................................................................................................420

21.1.3 Features........................................................................................................................................................422

21.2 Modes of operation.......................................................................................................................................................423

21.3 Memory map/register definition...................................................................................................................................423

21.3.1 Control Register (DMA_CR).......................................................................................................................438

21.3.2 Error Status Register (DMA_ES)................................................................................................................440

21.3.3 Enable Request Register (DMA_ERQ).......................................................................................................442

21.3.4 Enable Error Interrupt Register (DMA_EEI)...............................................................................................444

21.3.5 Clear Enable Error Interrupt Register (DMA_CEEI)..................................................................................446

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21.3.6 Set Enable Error Interrupt Register (DMA_SEEI)......................................................................................447

21.3.7 Clear Enable Request Register (DMA_CERQ)...........................................................................................448

21.3.8 Set Enable Request Register (DMA_SERQ)...............................................................................................449

21.3.9 Clear DONE Status Bit Register (DMA_CDNE)........................................................................................450

21.3.10 Set START Bit Register (DMA_SSRT)......................................................................................................451

21.3.11 Clear Error Register (DMA_CERR)............................................................................................................452

21.3.12 Clear Interrupt Request Register (DMA_CINT).........................................................................................453

21.3.13 Interrupt Request Register (DMA_INT)......................................................................................................453

21.3.14 Error Register (DMA_ERR)........................................................................................................................456

21.3.15 Hardware Request Status Register (DMA_HRS)........................................................................................458

21.3.16 Channel n Priority Register (DMA_DCHPRIn)..........................................................................................460

21.3.17 TCD Source Address (DMA_TCDn_SADDR)...........................................................................................461

21.3.18 TCD Signed Source Address Offset (DMA_TCDn_SOFF)........................................................................462

21.3.19 TCD Transfer Attributes (DMA_TCDn_ATTR).........................................................................................462

21.3.20 TCD Minor Byte Count (Minor Loop Disabled) (DMA_TCDn_NBYTES_MLNO).................................463

21.3.21 TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)

(DMA_TCDn_NBYTES_MLOFFNO).......................................................................................................464

21.3.22 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)

(DMA_TCDn_NBYTES_MLOFFYES).....................................................................................................465

21.3.23 TCD Last Source Address Adjustment (DMA_TCDn_SLAST).................................................................466

21.3.24 TCD Destination Address (DMA_TCDn_DADDR)...................................................................................466

21.3.25 TCD Signed Destination Address Offset (DMA_TCDn_DOFF)................................................................467

21.3.26 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)

(DMA_TCDn_CITER_ELINKYES)...........................................................................................................467

21.3.27 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)

(DMA_TCDn_CITER_ELINKNO)............................................................................................................468

21.3.28 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCDn_DLASTSGA)..........469

21.3.29 TCD Control and Status (DMA_TCDn_CSR)............................................................................................470

21.3.30 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)

(DMA_TCDn_BITER_ELINKYES)...........................................................................................................472

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21.3.31 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)

(DMA_TCDn_BITER_ELINKNO)............................................................................................................473

21.4 Functional description...................................................................................................................................................474

21.4.1 eDMA basic data flow.................................................................................................................................474

21.4.2 Error reporting and handling........................................................................................................................477

21.4.3 Channel preemption.....................................................................................................................................479

21.4.4 Performance.................................................................................................................................................479

21.5 Initialization/application information...........................................................................................................................483

21.5.1 eDMA initialization.....................................................................................................................................483

21.5.2 Programming errors.....................................................................................................................................485

21.5.3 Arbitration mode considerations..................................................................................................................486

21.5.4 Performing DMA transfers..........................................................................................................................486

21.5.5 Monitoring transfer descriptor status...........................................................................................................490

21.5.6 Dynamic programming................................................................................................................................492

Chapter 22

External Watchdog Monitor (EWM)

22.1 Introduction...................................................................................................................................................................495

22.1.1 Features........................................................................................................................................................495

22.1.2 Modes of Operation.....................................................................................................................................496

22.1.3 Block Diagram.............................................................................................................................................497

22.2 EWM Signal Descriptions............................................................................................................................................498

22.3 Memory Map/Register Definition.................................................................................................................................498

22.3.1 Control Register (EWM_CTRL).................................................................................................................498

22.3.2 Service Register (EWM_SERV)..................................................................................................................499

22.3.3 Compare Low Register (EWM_CMPL)......................................................................................................500

22.3.4 Compare High Register (EWM_CMPH).....................................................................................................500

22.4 Functional Description..................................................................................................................................................501

22.4.1 The EWM_out Signal..................................................................................................................................501

22.4.2 The EWM_in Signal....................................................................................................................................502

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Section Number Title Page

22.4.3 EWM Counter..............................................................................................................................................502

22.4.4 EWM Compare Registers............................................................................................................................502

22.4.5 EWM Refresh Mechanism...........................................................................................................................503

Chapter 23

Watchdog Timer (WDOG)

23.1 Introduction...................................................................................................................................................................505

23.2 Features.........................................................................................................................................................................505

23.3 Functional Overview.....................................................................................................................................................507

23.3.1 Unlocking and Updating the Watchdog.......................................................................................................508

23.3.2 The Watchdog Configuration Time (WCT).................................................................................................509

23.3.3 Refreshing the Watchdog.............................................................................................................................510

23.3.4 Windowed Mode of Operation....................................................................................................................510

23.3.5 Watchdog Disabled Mode of Operation......................................................................................................510

23.3.6 Low Power Modes of Operation..................................................................................................................511

23.3.7 Debug Modes of Operation..........................................................................................................................511

23.4 Testing the Watchdog...................................................................................................................................................512

23.4.1 Quick Test....................................................................................................................................................512

23.4.2 Byte Test......................................................................................................................................................512

23.5 Backup Reset Generator...............................................................................................................................................514

23.6 Generated Resets and Interrupts...................................................................................................................................514

23.7 Memory Map and Register Definition..........................................................................................................................515

23.7.1 Watchdog Status and Control Register High (WDOG_STCTRLH)...........................................................516

23.7.2 Watchdog Status and Control Register Low (WDOG_STCTRLL)............................................................518

23.7.3 Watchdog Time-out Value Register High (WDOG_TOVALH).................................................................518

23.7.4 Watchdog Time-out Value Register Low (WDOG_TOVALL)..................................................................519

23.7.5 Watchdog Window Register High (WDOG_WINH)..................................................................................519

23.7.6 Watchdog Window Register Low (WDOG_WINL)...................................................................................520

23.7.7 Watchdog Refresh Register (WDOG_REFRESH)......................................................................................520

23.7.8 Watchdog Unlock Register (WDOG_UNLOCK).......................................................................................520

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23.7.9 Watchdog Timer Output Register High (WDOG_TMROUTH).................................................................521

23.7.10 Watchdog Timer Output Register Low (WDOG_TMROUTL)..................................................................521

23.7.11 Watchdog Reset Count Register (WDOG_RSTCNT).................................................................................522

23.7.12 Watchdog Prescaler Register (WDOG_PRESC).........................................................................................522

23.8 Watchdog Operation with 8-bit access.........................................................................................................................522

23.8.1 General Guideline........................................................................................................................................522

23.8.2 Refresh and Unlock operations with 8-bit access........................................................................................523

23.9 Restrictions on Watchdog Operation............................................................................................................................524

Chapter 24

Multipurpose Clock Generator (MCG)

24.1 Introduction...................................................................................................................................................................527

24.1.1 Features........................................................................................................................................................527

24.1.2 Modes of Operation.....................................................................................................................................530

24.2 External Signal Description..........................................................................................................................................531

24.3 Memory Map/Register Definition.................................................................................................................................531

24.3.1 MCG Control 1 Register (MCG_C1)...........................................................................................................532

24.3.2 MCG Control 2 Register (MCG_C2)...........................................................................................................533

24.3.3 MCG Control 3 Register (MCG_C3)...........................................................................................................534

24.3.4 MCG Control 4 Register (MCG_C4)...........................................................................................................535

24.3.5 MCG Control 5 Register (MCG_C5)...........................................................................................................536

24.3.6 MCG Control 6 Register (MCG_C6)...........................................................................................................538

24.3.7 MCG Status Register (MCG_S)..................................................................................................................539

24.3.8 MCG Auto Trim Control Register (MCG_ATC)........................................................................................541

24.3.9 MCG Auto Trim Compare Value High Register (MCG_ATCVH)............................................................541

24.3.10 MCG Auto Trim Compare Value Low Register (MCG_ATCVL)..............................................................542

24.4 Functional Description..................................................................................................................................................542

24.4.1 MCG Mode State Diagram..........................................................................................................................542

24.4.2 Low Power Bit Usage..................................................................................................................................547

K50 Sub-Family Reference Manual, Rev. 6, Nov 2011

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