Section Number Title Page
18.2 Overview.......................................................................................................................................................................381
18.2.1 Block Diagram.............................................................................................................................................381
18.2.2 Features........................................................................................................................................................382
18.3 Memory Map/Register Definition.................................................................................................................................383
18.3.1 Control/Error Status Register (MPU_CESR)..............................................................................................386
18.3.2 Error Address Register, Slave Port n (MPU_EARn)...................................................................................388
18.3.3 Error Detail Register, Slave Port n (MPU_EDRn)......................................................................................389
18.3.4 Region Descriptor n, Word 0 (MPU_RGDn_WORD0)..............................................................................390
18.3.5 Region Descriptor n, Word 1 (MPU_RGDn_WORD1)..............................................................................391
18.3.6 Region Descriptor n, Word 2 (MPU_RGDn_WORD2)..............................................................................391
18.3.7 Region Descriptor n, Word 3 (MPU_RGDn_WORD3)..............................................................................394
18.3.8 Region Descriptor Alternate Access Control n (MPU_RGDAACn)...........................................................395
18.4 Functional Description..................................................................................................................................................397
18.4.1 Access Evaluation Macro.............................................................................................................................397
18.4.2 Putting It All Together and Error Terminations...........................................................................................398
18.4.3 Power Management......................................................................................................................................399
18.5 Initialization Information..............................................................................................................................................399
18.6 Application Information................................................................................................................................................399
Chapter 19
Peripheral Bridge (AIPS-Lite)
19.1 Introduction...................................................................................................................................................................403
19.1.1 Features........................................................................................................................................................403
19.1.2 General operation.........................................................................................................................................403
19.2 Memory map/register definition...................................................................................................................................404
19.2.1 Master Privilege Register A (AIPSx_MPRA).............................................................................................405
19.2.2 Peripheral Access Control Register (AIPSx_PACRn).................................................................................409
19.2.3 Peripheral Access Control Register (AIPSx_PACRn).................................................................................414
19.3 Functional Description..................................................................................................................................................419
19.3.1 Access support.............................................................................................................................................419
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 15