NXP K30_100 Reference guide

Type
Reference guide
K30 Sub-Family Reference Manual
Supports: MK30DN512VLK10, MK30DN512VMB10
Document Number: K30P81M100SF2V2RM
Rev. 2 Jun 2012
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Contents
Section number Title Page
Chapter 1
About This Document
1.1 Overview.......................................................................................................................................................................53
1.1.1 Purpose.........................................................................................................................................................53
1.1.2 Audience......................................................................................................................................................53
1.2 Conventions..................................................................................................................................................................53
1.2.1 Numbering systems......................................................................................................................................53
1.2.2 Typographic notation...................................................................................................................................54
1.2.3 Special terms................................................................................................................................................54
Chapter 2
Introduction
2.1 Overview.......................................................................................................................................................................55
2.2 Module Functional Categories......................................................................................................................................55
2.2.1 ARM Cortex-M4 Core Modules..................................................................................................................56
2.2.2 System Modules...........................................................................................................................................57
2.2.3 Memories and Memory Interfaces...............................................................................................................58
2.2.4 Clocks...........................................................................................................................................................58
2.2.5 Security and Integrity modules....................................................................................................................59
2.2.6 Analog modules...........................................................................................................................................59
2.2.7 Timer modules.............................................................................................................................................60
2.2.8 Communication interfaces...........................................................................................................................61
2.2.9 Human-machine interfaces..........................................................................................................................61
2.3 Orderable part numbers.................................................................................................................................................62
Chapter 3
Chip Configuration
3.1 Introduction...................................................................................................................................................................63
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3.2 Core modules................................................................................................................................................................63
3.2.1 ARM Cortex-M4 Core Configuration..........................................................................................................63
3.2.2 Nested Vectored Interrupt Controller (NVIC) Configuration......................................................................65
3.2.3 Asynchronous Wake-up Interrupt Controller (AWIC) Configuration.........................................................71
3.2.4 JTAG Controller Configuration...................................................................................................................73
3.3 System modules............................................................................................................................................................73
3.3.1 SIM Configuration.......................................................................................................................................73
3.3.2 System Mode Controller (SMC) Configuration...........................................................................................74
3.3.3 PMC Configuration......................................................................................................................................75
3.3.4 Low-Leakage Wake-up Unit (LLWU) Configuration.................................................................................75
3.3.5 MCM Configuration....................................................................................................................................77
3.3.6 Crossbar Switch Configuration....................................................................................................................78
3.3.7 Memory Protection Unit (MPU) Configuration...........................................................................................80
3.3.8 Peripheral Bridge Configuration..................................................................................................................82
3.3.9 DMA request multiplexer configuration......................................................................................................84
3.3.10 DMA Controller Configuration...................................................................................................................87
3.3.11 External Watchdog Monitor (EWM) Configuration....................................................................................87
3.3.12 Watchdog Configuration..............................................................................................................................89
3.4 Clock modules..............................................................................................................................................................90
3.4.1 MCG Configuration.....................................................................................................................................90
3.4.2 OSC Configuration......................................................................................................................................91
3.4.3 RTC OSC configuration...............................................................................................................................92
3.5 Memories and memory interfaces.................................................................................................................................92
3.5.1 Flash Memory Configuration.......................................................................................................................92
3.5.2 Flash Memory Controller Configuration.....................................................................................................95
3.5.3 SRAM Configuration...................................................................................................................................96
3.5.4 SRAM Controller Configuration.................................................................................................................99
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3.5.5 System Register File Configuration.............................................................................................................100
3.5.6 VBAT Register File Configuration..............................................................................................................100
3.5.7 EzPort Configuration...................................................................................................................................101
3.6 Security.........................................................................................................................................................................102
3.6.1 CRC Configuration......................................................................................................................................102
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3.7 Analog...........................................................................................................................................................................103
3.7.1 16-bit SAR ADC with PGA Configuration.................................................................................................103
3.7.2 CMP Configuration......................................................................................................................................111
3.7.3 12-bit DAC Configuration...........................................................................................................................113
3.7.4 VREF Configuration....................................................................................................................................114
3.8 Timers...........................................................................................................................................................................115
3.8.1 PDB Configuration......................................................................................................................................115
3.8.2 FlexTimer Configuration.............................................................................................................................118
3.8.3 PIT Configuration........................................................................................................................................122
3.8.4 Low-power timer configuration...................................................................................................................123
3.8.5 CMT Configuration......................................................................................................................................125
3.8.6 RTC configuration.......................................................................................................................................126
3.9 Communication interfaces............................................................................................................................................127
3.9.1 CAN Configuration......................................................................................................................................127
3.9.2 SPI configuration.........................................................................................................................................129
3.9.3 I2C Configuration........................................................................................................................................133
3.9.4 UART Configuration...................................................................................................................................133
3.9.5 SDHC Configuration....................................................................................................................................136
3.9.6 I2S configuration..........................................................................................................................................138
3.10 Human-machine interfaces...........................................................................................................................................140
3.10.1 GPIO configuration......................................................................................................................................140
3.10.2 TSI Configuration........................................................................................................................................141
3.10.3 Segment LCD Configuration.......................................................................................................................143
Chapter 4
Memory Map
4.1 Introduction...................................................................................................................................................................147
4.2 System memory map.....................................................................................................................................................147
4.2.1 Aliased bit-band regions..............................................................................................................................148
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4.3 Flash Memory Map.......................................................................................................................................................149
4.3.1 Alternate Non-Volatile IRC User Trim Description....................................................................................150
4.4 SRAM memory map.....................................................................................................................................................150
4.5 Peripheral bridge (AIPS-Lite0 and AIPS-Lite1) memory maps...................................................................................150
4.5.1 Peripheral Bridge 0 (AIPS-Lite 0) Memory Map........................................................................................151
4.5.2 Peripheral Bridge 1 (AIPS-Lite 1) Memory Map........................................................................................154
4.6 Private Peripheral Bus (PPB) memory map..................................................................................................................158
Chapter 5
Clock Distribution
5.1 Introduction...................................................................................................................................................................159
5.2 Programming model......................................................................................................................................................159
5.3 High-Level device clocking diagram............................................................................................................................159
5.4 Clock definitions...........................................................................................................................................................160
5.4.1 Device clock summary.................................................................................................................................161
5.5 Internal clocking requirements.....................................................................................................................................162
5.5.1 Clock divider values after reset....................................................................................................................163
5.5.2 VLPR mode clocking...................................................................................................................................164
5.6 Clock Gating.................................................................................................................................................................164
5.7 Module clocks...............................................................................................................................................................165
5.7.1 PMC 1-kHz LPO clock................................................................................................................................166
5.7.2 WDOG clocking..........................................................................................................................................166
5.7.3 Debug trace clock.........................................................................................................................................167
5.7.4 PORT digital filter clocking.........................................................................................................................167
5.7.5 LPTMR clocking..........................................................................................................................................168
5.7.6 FlexCAN clocking.......................................................................................................................................168
5.7.7 UART clocking............................................................................................................................................169
5.7.8 SDHC clocking............................................................................................................................................169
5.7.9 I2S/SAI clocking..........................................................................................................................................169
5.7.10 TSI clocking.................................................................................................................................................170
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Chapter 6
Reset and Boot
6.1 Introduction...................................................................................................................................................................173
6.2 Reset..............................................................................................................................................................................174
6.2.1 Power-on reset (POR)..................................................................................................................................174
6.2.2 System reset sources....................................................................................................................................174
6.2.3 MCU Resets.................................................................................................................................................178
6.2.4 Reset Pin .....................................................................................................................................................180
6.2.5 Debug resets.................................................................................................................................................180
6.3 Boot...............................................................................................................................................................................181
6.3.1 Boot sources.................................................................................................................................................181
6.3.2 Boot options.................................................................................................................................................182
6.3.3 FOPT boot options.......................................................................................................................................182
6.3.4 Boot sequence..............................................................................................................................................183
Chapter 7
Power Management
7.1 Introduction...................................................................................................................................................................185
7.2 Power modes.................................................................................................................................................................185
7.3 Entering and exiting power modes...............................................................................................................................187
7.4 Power mode transitions.................................................................................................................................................188
7.5 Power modes shutdown sequencing.............................................................................................................................189
7.6 Module Operation in Low Power Modes......................................................................................................................189
7.7 Clock Gating.................................................................................................................................................................192
Chapter 8
Security
8.1 Introduction...................................................................................................................................................................193
8.2 Flash Security...............................................................................................................................................................193
8.3 Security Interactions with other Modules.....................................................................................................................194
8.3.1 Security Interactions with EzPort................................................................................................................194
8.3.2 Security Interactions with Debug.................................................................................................................194
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Chapter 9
Debug
9.1 Introduction...................................................................................................................................................................195
9.1.1 References....................................................................................................................................................197
9.2 The Debug Port.............................................................................................................................................................197
9.2.1 JTAG-to-SWD change sequence.................................................................................................................198
9.2.2 JTAG-to-cJTAG change sequence...............................................................................................................198
9.3 Debug Port Pin Descriptions.........................................................................................................................................199
9.4 System TAP connection................................................................................................................................................199
9.4.1 IR Codes.......................................................................................................................................................199
9.5 JTAG status and control registers.................................................................................................................................200
9.5.1 MDM-AP Control Register..........................................................................................................................201
9.5.2 MDM-AP Status Register............................................................................................................................203
9.6 Debug Resets................................................................................................................................................................204
9.7 AHB-AP........................................................................................................................................................................205
9.8 ITM...............................................................................................................................................................................206
9.9 Core Trace Connectivity...............................................................................................................................................206
9.10 Embedded Trace Macrocell v3.5 (ETM)......................................................................................................................207
9.11 Coresight Embedded Trace Buffer (ETB)....................................................................................................................208
9.11.1 Performance Profiling with the ETB...........................................................................................................208
9.11.2 ETB Counter Control...................................................................................................................................209
9.12 TPIU..............................................................................................................................................................................209
9.13 DWT.............................................................................................................................................................................209
9.14 Debug in Low Power Modes........................................................................................................................................210
9.14.1 Debug Module State in Low Power Modes.................................................................................................211
9.15 Debug & Security.........................................................................................................................................................211
Chapter 10
Signal Multiplexing and Signal Descriptions
10.1 Introduction...................................................................................................................................................................213
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10.2 Signal Multiplexing Integration....................................................................................................................................213
10.2.1 Port control and interrupt module features..................................................................................................214
10.2.2 PCRn reset values for port A.......................................................................................................................214
10.2.3 Clock gating.................................................................................................................................................214
10.2.4 Signal multiplexing constraints....................................................................................................................214
10.3 Pinout............................................................................................................................................................................215
10.3.1 K30 Signal Multiplexing and Pin Assignments...........................................................................................215
10.3.2 K30 Pinouts..................................................................................................................................................220
10.4 Module Signal Description Tables................................................................................................................................221
10.4.1 Core Modules...............................................................................................................................................222
10.4.2 System Modules...........................................................................................................................................222
10.4.3 Clock Modules.............................................................................................................................................223
10.4.4 Memories and Memory Interfaces...............................................................................................................223
10.4.5 Analog..........................................................................................................................................................224
10.4.6 Timer Modules.............................................................................................................................................225
10.4.7 Communication Interfaces...........................................................................................................................227
10.4.8 Human-Machine Interfaces (HMI)..............................................................................................................230
Chapter 11
Port control and interrupts (PORT)
11.1 Introduction...................................................................................................................................................................233
11.2 Overview.......................................................................................................................................................................233
11.2.1 Features........................................................................................................................................................233
11.2.2 Modes of operation......................................................................................................................................234
11.3 External signal description............................................................................................................................................235
11.4 Detailed signal description............................................................................................................................................235
11.5 Memory map and register definition.............................................................................................................................235
11.5.1 Pin Control Register n (PORTx_PCRn).......................................................................................................241
11.5.2 Global Pin Control Low Register (PORTx_GPCLR)..................................................................................244
11.5.3 Global Pin Control High Register (PORTx_GPCHR).................................................................................244
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11.5.4 Interrupt Status Flag Register (PORTx_ISFR)............................................................................................245
11.6 Functional description...................................................................................................................................................245
11.6.1 Pin control....................................................................................................................................................245
11.6.2 Global pin control........................................................................................................................................246
11.6.3 External interrupts........................................................................................................................................246
Chapter 12
System Integration Module (SIM)
12.1 Introduction...................................................................................................................................................................249
12.1.1 Features........................................................................................................................................................249
12.2 Memory map and register definition.............................................................................................................................250
12.2.1 System Options Register 1 (SIM_SOPT1)..................................................................................................251
12.2.2 System Options Register 2 (SIM_SOPT2)..................................................................................................253
12.2.3 System Options Register 4 (SIM_SOPT4)..................................................................................................255
12.2.4 System Options Register 5 (SIM_SOPT5)..................................................................................................257
12.2.5 System Options Register 7 (SIM_SOPT7)..................................................................................................259
12.2.6 System Device Identification Register (SIM_SDID)...................................................................................261
12.2.7 System Clock Gating Control Register 1 (SIM_SCGC1)............................................................................262
12.2.8 System Clock Gating Control Register 2 (SIM_SCGC2)............................................................................263
12.2.9 System Clock Gating Control Register 3 (SIM_SCGC3)............................................................................264
12.2.10 System Clock Gating Control Register 4 (SIM_SCGC4)............................................................................265
12.2.11 System Clock Gating Control Register 5 (SIM_SCGC5)............................................................................268
12.2.12 System Clock Gating Control Register 6 (SIM_SCGC6)............................................................................270
12.2.13 System Clock Gating Control Register 7 (SIM_SCGC7)............................................................................272
12.2.14 System Clock Divider Register 1 (SIM_CLKDIV1)...................................................................................273
12.2.15 System Clock Divider Register 2 (SIM_CLKDIV2)...................................................................................275
12.2.16 Flash Configuration Register 1 (SIM_FCFG1)...........................................................................................276
12.2.17 Flash Configuration Register 2 (SIM_FCFG2)...........................................................................................278
12.2.18 Unique Identification Register High (SIM_UIDH).....................................................................................279
12.2.19 Unique Identification Register Mid-High (SIM_UIDMH)..........................................................................280
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12.2.20 Unique Identification Register Mid Low (SIM_UIDML)...........................................................................280
12.2.21 Unique Identification Register Low (SIM_UIDL)......................................................................................281
12.3 Functional description...................................................................................................................................................281
Chapter 13
Reset Control Module (RCM)
13.1 Introduction...................................................................................................................................................................283
13.2 Reset memory map and register descriptions...............................................................................................................283
13.2.1 System Reset Status Register 0 (RCM_SRS0)............................................................................................283
13.2.2 System Reset Status Register 1 (RCM_SRS1)............................................................................................285
13.2.3 Reset Pin Filter Control register (RCM_RPFC)..........................................................................................286
13.2.4 Reset Pin Filter Width register (RCM_RPFW)...........................................................................................287
13.2.5 Mode Register (RCM_MR).........................................................................................................................289
Chapter 14
System Mode Controller
14.1 Introduction...................................................................................................................................................................291
14.2 Modes of operation.......................................................................................................................................................291
14.3 Memory map and register descriptions.........................................................................................................................293
14.3.1 Power Mode Protection register (SMC_PMPROT).....................................................................................294
14.3.2 Power Mode Control register (SMC_PMCTRL).........................................................................................295
14.3.3 VLLS Control register (SMC_VLLSCTRL)...............................................................................................296
14.3.4 Power Mode Status register (SMC_PMSTAT)...........................................................................................297
14.4 Functional description...................................................................................................................................................298
14.4.1 Power mode transitions................................................................................................................................298
14.4.2 Power mode entry/exit sequencing..............................................................................................................301
14.4.3 Run modes....................................................................................................................................................303
14.4.4 Wait modes..................................................................................................................................................305
14.4.5 Stop modes...................................................................................................................................................306
14.4.6 Debug in low power modes.........................................................................................................................309
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Chapter 15
Power Management Controller
15.1 Introduction...................................................................................................................................................................311
15.2 Features.........................................................................................................................................................................311
15.3 Low-voltage detect (LVD) system................................................................................................................................311
15.3.1 LVD reset operation.....................................................................................................................................312
15.3.2 LVD interrupt operation...............................................................................................................................312
15.3.3 Low-voltage warning (LVW) interrupt operation.......................................................................................312
15.4 I/O retention..................................................................................................................................................................313
15.5 Memory map and register descriptions.........................................................................................................................313
15.5.1 Low Voltage Detect Status And Control 1 register (PMC_LVDSC1)........................................................314
15.5.2 Low Voltage Detect Status And Control 2 register (PMC_LVDSC2)........................................................315
15.5.3 Regulator Status And Control register (PMC_REGSC)..............................................................................316
Chapter 16
Low-Leakage Wakeup Unit (LLWU)
16.1 Introduction...................................................................................................................................................................319
16.1.1 Features........................................................................................................................................................319
16.1.2 Modes of operation......................................................................................................................................320
16.1.3 Block diagram..............................................................................................................................................321
16.2 LLWU signal descriptions............................................................................................................................................322
16.3 Memory map/register definition...................................................................................................................................323
16.3.1 LLWU Pin Enable 1 register (LLWU_PE1)................................................................................................324
16.3.2 LLWU Pin Enable 2 register (LLWU_PE2)................................................................................................325
16.3.3 LLWU Pin Enable 3 register (LLWU_PE3)................................................................................................326
16.3.4 LLWU Pin Enable 4 register (LLWU_PE4)................................................................................................327
16.3.5 LLWU Module Enable register (LLWU_ME)............................................................................................328
16.3.6 LLWU Flag 1 register (LLWU_F1).............................................................................................................330
16.3.7 LLWU Flag 2 register (LLWU_F2).............................................................................................................331
16.3.8 LLWU Flag 3 register (LLWU_F3).............................................................................................................333
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16.3.9 LLWU Pin Filter 1 register (LLWU_FILT1)..............................................................................................335
16.3.10 LLWU Pin Filter 2 register (LLWU_FILT2)..............................................................................................336
16.3.11 LLWU Reset Enable register (LLWU_RST)...............................................................................................337
16.4 Functional description...................................................................................................................................................338
16.4.1 LLS mode.....................................................................................................................................................338
16.4.2 VLLS modes................................................................................................................................................338
16.4.3 Initialization.................................................................................................................................................339
Chapter 17
Miscellaneous Control Module (MCM)
17.1 Introduction...................................................................................................................................................................341
17.1.1 Features........................................................................................................................................................341
17.2 Memory map/register descriptions...............................................................................................................................341
17.2.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)................................................................342
17.2.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC)............................................................343
17.2.3 Control Register (MCM_CR)......................................................................................................................343
17.2.4 Interrupt Status Register (MCM_ISR).........................................................................................................345
17.2.5 ETB Counter Control register (MCM_ETBCC)..........................................................................................346
17.2.6 ETB Reload register (MCM_ETBRL).........................................................................................................347
17.2.7 ETB Counter Value register (MCM_ETBCNT)..........................................................................................347
17.2.8 Process ID register (MCM_PID).................................................................................................................348
17.3 Functional description...................................................................................................................................................348
17.3.1 Interrupts......................................................................................................................................................348
Chapter 18
Crossbar Switch (AXBS)
18.1 Introduction...................................................................................................................................................................351
18.1.1 Features........................................................................................................................................................351
18.2 Memory Map / Register Definition...............................................................................................................................352
18.2.1 Priority Registers Slave (AXBS_PRSn)......................................................................................................353
18.2.2 Control Register (AXBS_CRSn).................................................................................................................356
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18.2.3 Master General Purpose Control Register (AXBS_MGPCRn)...................................................................358
18.3 Functional Description..................................................................................................................................................358
18.3.1 General operation.........................................................................................................................................358
18.3.2 Register coherency.......................................................................................................................................360
18.3.3 Arbitration....................................................................................................................................................360
18.4 Initialization/application information...........................................................................................................................363
Chapter 19
Memory Protection Unit (MPU)
19.1 Introduction...................................................................................................................................................................365
19.2 Overview.......................................................................................................................................................................365
19.2.1 Block diagram..............................................................................................................................................365
19.2.2 Features........................................................................................................................................................366
19.3 Memory map/register definition...................................................................................................................................367
19.3.1 Control/Error Status Register (MPU_CESR)..............................................................................................371
19.3.2 Error Address Register, slave port n (MPU_EARn)....................................................................................372
19.3.3 Error Detail Register, slave port n (MPU_EDRn).......................................................................................373
19.3.4 Region Descriptor n, Word 0 (MPU_RGDn_WORD0)..............................................................................374
19.3.5 Region Descriptor n, Word 1 (MPU_RGDn_WORD1)..............................................................................374
19.3.6 Region Descriptor n, Word 2 (MPU_RGDn_WORD2)..............................................................................375
19.3.7 Region Descriptor n, Word 3 (MPU_RGDn_WORD3)..............................................................................378
19.3.8 Region Descriptor Alternate Access Control n (MPU_RGDAACn)...........................................................379
19.4 Functional description...................................................................................................................................................381
19.4.1 Access evaluation macro..............................................................................................................................381
19.4.2 Putting it all together and error terminations...............................................................................................382
19.4.3 Power management......................................................................................................................................383
19.5 Initialization information..............................................................................................................................................383
19.6 Application information................................................................................................................................................383
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Chapter 20
Peripheral Bridge (AIPS-Lite)
20.1 Introduction...................................................................................................................................................................387
20.1.1 Features........................................................................................................................................................387
20.1.2 General operation.........................................................................................................................................388
20.2 Memory map/register definition...................................................................................................................................388
20.2.1 Master Privilege Register A (AIPSx_MPRA).............................................................................................390
20.2.2 Peripheral Access Control Register (AIPSx_PACRn).................................................................................393
20.2.3 Peripheral Access Control Register (AIPSx_PACRn).................................................................................398
20.3 Functional description...................................................................................................................................................403
20.3.1 Access support.............................................................................................................................................403
Chapter 21
Direct Memory Access Multiplexer (DMAMUX)
21.1 Introduction...................................................................................................................................................................405
21.1.1 Overview......................................................................................................................................................405
21.1.2 Features........................................................................................................................................................406
21.1.3 Modes of operation......................................................................................................................................406
21.2 External signal description............................................................................................................................................407
21.3 Memory map/register definition...................................................................................................................................407
21.3.1 Channel Configuration register (DMAMUX_CHCFGn)............................................................................408
21.4 Functional description...................................................................................................................................................409
21.4.1 DMA channels with periodic triggering capability......................................................................................409
21.4.2 DMA channels with no triggering capability...............................................................................................411
21.4.3 "Always enabled" DMA sources.................................................................................................................411
21.5 Initialization/application information...........................................................................................................................412
21.5.1 Reset.............................................................................................................................................................413
21.5.2 Enabling and configuring sources................................................................................................................413
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Chapter 22
Direct Memory Access Controller (eDMA)
22.1 Introduction...................................................................................................................................................................417
22.1.1 Block diagram..............................................................................................................................................417
22.1.2 Block parts...................................................................................................................................................418
22.1.3 Features........................................................................................................................................................419
22.2 Modes of operation.......................................................................................................................................................421
22.3 Memory map/register definition...................................................................................................................................421
22.3.1 Control Register (DMA_CR).......................................................................................................................432
22.3.2 Error Status Register (DMA_ES)................................................................................................................434
22.3.3 Enable Request Register (DMA_ ERQ ).....................................................................................................436
22.3.4 Enable Error Interrupt Register (DMA_ EEI ).............................................................................................438
22.3.5 Clear Enable Error Interrupt Register (DMA_CEEI)..................................................................................441
22.3.6 Set Enable Error Interrupt Register (DMA_SEEI)......................................................................................442
22.3.7 Clear Enable Request Register (DMA_CERQ)...........................................................................................443
22.3.8 Set Enable Request Register (DMA_SERQ)...............................................................................................444
22.3.9 Clear DONE Status Bit Register (DMA_CDNE)........................................................................................445
22.3.10 Set START Bit Register (DMA_SSRT)......................................................................................................446
22.3.11 Clear Error Register (DMA_CERR)............................................................................................................447
22.3.12 Clear Interrupt Request Register (DMA_CINT).........................................................................................448
22.3.13 Interrupt Request Register (DMA_ INT )....................................................................................................449
22.3.14 Error Register (DMA_ ERR )......................................................................................................................451
22.3.15 Hardware Request Status Register (DMA_ HRS )......................................................................................454
22.3.16 Channel n Priority Register (DMA_DCHPRIn)..........................................................................................456
22.3.17 TCD Source Address (DMA_TCDn_SADDR)...........................................................................................457
22.3.18 TCD Signed Source Address Offset (DMA_TCDn_SOFF)........................................................................457
22.3.19 TCD Transfer Attributes (DMA_TCDn_ATTR).........................................................................................458
22.3.20 TCD Minor Byte Count (Minor Loop Disabled) (DMA_TCDn_NBYTES_MLNO).................................459
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22.3.21 TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)
(DMA_TCDn_NBYTES_MLOFFNO).......................................................................................................459
22.3.22 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
(DMA_TCDn_NBYTES_MLOFFYES).....................................................................................................460
22.3.23 TCD Last Source Address Adjustment (DMA_TCDn_SLAST).................................................................462
22.3.24 TCD Destination Address (DMA_TCDn_DADDR)...................................................................................462
22.3.25 TCD Signed Destination Address Offset (DMA_TCDn_DOFF)................................................................463
22.3.26 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
(DMA_TCDn_CITER_ELINKYES)...........................................................................................................463
22.3.27 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
(DMA_TCDn_CITER_ELINKNO)............................................................................................................464
22.3.28 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCDn_DLASTSGA)..........465
22.3.29 TCD Control and Status (DMA_TCDn_CSR)............................................................................................466
22.3.30 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
(DMA_TCDn_BITER_ELINKYES)...........................................................................................................468
22.3.31 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
(DMA_TCDn_BITER_ELINKNO)............................................................................................................469
22.4 Functional description...................................................................................................................................................470
22.4.1 eDMA basic data flow.................................................................................................................................470
22.4.2 Error reporting and handling........................................................................................................................473
22.4.3 Channel preemption.....................................................................................................................................475
22.4.4 Performance.................................................................................................................................................475
22.5 Initialization/application information...........................................................................................................................480
22.5.1 eDMA initialization.....................................................................................................................................480
22.5.2 Programming errors.....................................................................................................................................482
22.5.3 Arbitration mode considerations..................................................................................................................482
22.5.4 Performing DMA transfers (examples)........................................................................................................483
22.5.5 Monitoring transfer descriptor status...........................................................................................................487
22.5.6 Channel Linking...........................................................................................................................................488
K30 Sub-Family Reference Manual, Rev. 2 Jun 2012
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Preliminary
Freescale Semiconductor, Inc.
General Business Information
Section number Title Page
22.5.7 Dynamic programming................................................................................................................................490
Chapter 23
External Watchdog Monitor (EWM)
23.1 Introduction...................................................................................................................................................................495
23.1.1 Features........................................................................................................................................................495
23.1.2 Modes of Operation.....................................................................................................................................496
23.1.3 Block Diagram.............................................................................................................................................497
23.2 EWM Signal Descriptions............................................................................................................................................498
23.3 Memory Map/Register Definition.................................................................................................................................498
23.3.1 Control Register (EWM_CTRL).................................................................................................................498
23.3.2 Service Register (EWM_SERV)..................................................................................................................499
23.3.3 Compare Low Register (EWM_CMPL)......................................................................................................499
23.3.4 Compare High Register (EWM_CMPH).....................................................................................................500
23.3.5 Clock Prescaler Register (EWM_CLKPRESCALER)................................................................................501
23.4 Functional Description..................................................................................................................................................501
23.4.1 The EWM_out Signal..................................................................................................................................501
23.4.2 The EWM_in Signal....................................................................................................................................502
23.4.3 EWM Counter..............................................................................................................................................503
23.4.4 EWM Compare Registers............................................................................................................................503
23.4.5 EWM Refresh Mechanism...........................................................................................................................503
23.4.6 EWM Interrupt.............................................................................................................................................504
23.4.7 Counter clock prescaler................................................................................................................................504
Chapter 24
Watchdog Timer (WDOG)
24.1 Introduction...................................................................................................................................................................505
24.2 Features.........................................................................................................................................................................505
24.3 Functional overview......................................................................................................................................................507
24.3.1 Unlocking and updating the watchdog.........................................................................................................508
24.3.2 Watchdog configuration time (WCT)..........................................................................................................509
K30 Sub-Family Reference Manual, Rev. 2 Jun 2012
Freescale Semiconductor, Inc.
Preliminary
19
General Business Information
Section number Title Page
24.3.3 Refreshing the watchdog..............................................................................................................................510
24.3.4 Windowed mode of operation......................................................................................................................510
24.3.5 Watchdog disabled mode of operation.........................................................................................................510
24.3.6 Low-power modes of operation...................................................................................................................511
24.3.7 Debug modes of operation...........................................................................................................................511
24.4 Testing the watchdog....................................................................................................................................................512
24.4.1 Quick test.....................................................................................................................................................512
24.4.2 Byte test........................................................................................................................................................513
24.5 Backup reset generator..................................................................................................................................................514
24.6 Generated resets and interrupts.....................................................................................................................................514
24.7 Memory map and register definition.............................................................................................................................515
24.7.1 Watchdog Status and Control Register High (WDOG_STCTRLH)...........................................................516
24.7.2 Watchdog Status and Control Register Low (WDOG_STCTRLL)............................................................517
24.7.3 Watchdog Time-out Value Register High (WDOG_TOVALH).................................................................518
24.7.4 Watchdog Time-out Value Register Low (WDOG_TOVALL)..................................................................518
24.7.5 Watchdog Window Register High (WDOG_WINH)..................................................................................519
24.7.6 Watchdog Window Register Low (WDOG_WINL)...................................................................................519
24.7.7 Watchdog Refresh register (WDOG_REFRESH).......................................................................................520
24.7.8 Watchdog Unlock register (WDOG_UNLOCK).........................................................................................520
24.7.9 Watchdog Timer Output Register High (WDOG_TMROUTH).................................................................520
24.7.10 Watchdog Timer Output Register Low (WDOG_TMROUTL)..................................................................521
24.7.11 Watchdog Reset Count register (WDOG_RSTCNT)..................................................................................521
24.7.12 Watchdog Prescaler register (WDOG_PRESC)..........................................................................................522
24.8 Watchdog operation with 8-bit access..........................................................................................................................522
24.8.1 General guideline.........................................................................................................................................522
24.8.2 Refresh and unlock operations with 8-bit access.........................................................................................522
24.9 Restrictions on watchdog operation..............................................................................................................................523
K30 Sub-Family Reference Manual, Rev. 2 Jun 2012
20
Preliminary
Freescale Semiconductor, Inc.
General Business Information
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NXP K30_100 Reference guide

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Reference guide

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