IMD SF104x User manual

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SF104x

Fingerprint Image Sensor Module

User Manual

February 7, 2014

Image Match Design Inc.

http://www.imagematch.com.tw/

B3-2, No. 1, Lising 1st Road, Hisnchu Science

Park, Hsinchu 300, Taiwan (R.O.C.)

Tel：+886-3-666-9388

Fax：+886-3-666-9387

Service：[email protected]

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Revision History

Version Date Content Approved Checked Drawn

P01 2014/02/07 Initial draft Albert Ke

P02 2014/3012 I/O spec AL

P03 2014/03/17

Interface and drawing

update Eros

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Content

1OVERVIEW .................................................................................................................... 5

1.1DESCRIPTION ............................................................................................................ 5

1.2FEATURES ................................................................................................................. 5

1.3SENSOR BLOCK DIAGRAM .......................................................................................... 6

1.4APPLICATIONS ........................................................................................................... 6

2PHYSICAL DIMENSION ................................................................................................ 7

3DEVICE OPERATION .................................................................................................... 7

3.1SETTING UP CLOCK DIVIDER ........................................................................................ 7

3.2CONFIGURING GAIN AND RANGE OF PRE-AMP AND ADC ................................................. 8

3.3COMMAND AND REGISTERS ......................................................................................... 9

3.4SPI COMMAND PROTOCOL ........................................................................................ 11

3.5COMMAND CODE DETAIL ........................................................................................... 13

3.6REGISTER DETAIL..................................................................................................... 15

4OPERATION WORKFLOW ......................................................................................... 22

4.1GENERAL DESCRIPTION ............................................................................................ 22

4.2RESET .................................................................................................................... 23

4.3FINGER DETECTION MODE AND INTERRUPT ................................................................. 23

4.4TIMING CONSIDERATIONS .......................................................................................... 24

4.5A SAMPLE SESSION .................................................................................................. 25

5TIMING CHARACTERISTICS ...................................................................................... 28

5.1SPI INTERFACE TIMING ............................................................................................. 28

6MAXIMUM RATINGS AND OPERATING CONDITION ............................................... 31

7ELECTRICAL CHARACTERISTICS ............................................................................ 32

8RELIABILITY TEST ..................................................................................................... 32

8.1ESD IMMUNITY ........................................................................................................ 32

8.2ENVIRONMENTAL LIMITS ........................................................................................... 33

8.3MECHANICAL DURABILITY .......................................................................................... 33

9PACKAGING INFORMATION ..................................................................................... 34

9.1THE SF104X PACKAGING ......................................................................................... 34

9.2SIGNAL DEFINITION................................................................................................... 34

9.3PART DRAWING ........................................................................................................ 35

9.4PIN CONFIGURATION ................................................................................................ 35

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9.5REFERENCE SCHEMATIC ........................................................................................... 36

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1 Overview

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1.1 Description

The SF104x fingerprint image sensor module is based on capacitive-contact

technology with hardened surface and enhanced ESD resistivity. The build-in analog and

digital circuitry minimizes the number of external component, and provides easy-to-use,

standard SPI interface to microprocessors.

The operation of SF104x is controlled through fingerprint image sensing by pixel array,

A/D converting, digital process, following is simple interface protocol. The captured image

quality of SF104x can be adjusted by setting gain, offset and reference voltage parameters.

In addition, the internal operation parameter and interface speed can also be configured to

the need.

1.2 Features

 Spatial resolution 508 DPI

 2D sensor array of 160x160 pixels

 Active sensing area 8 mm x 8 mm

 Build-in 8-bit ADC for digitizing image

 Build-in programmable voltage reference

 High speed SPI interface

 0.03 sec read out time

 128-byte on-chip data FIFO

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1.3 Sensor Block Diagram

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1.4 Applications

The compact, thin packaging of SF104x sensor module allows a wide range of

applications

 Security devices

 Fingerprint identification systems

 Fingerprint recognition systems

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2 Physical Dimension

The sensor’s active pixel array is 160x160 pixels, and the SF104xM module is a

13.4mm*13.9mm highly integrated SPI fingerprint module.

3 Device operation

3.1 Setting up clock divider

The fingerprint sensor module has an on-board oscillator of 18Mhz, the sensor’s

internal clock logic is summarized as the following figure:

Sensor

& ADC

128-BYTE

FIFO

SPI

interface

Timing

Generator

Registers

Digital control

Register access

Analog control

D0~D7

D0~D7 ADCCLK

MCU

OTP

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In the above diagram, OPCLK is used for internal timing, and PCLK is for image pixels.

The “detect start” signal starts the short “finger detect” cycle in detect mode.

The PCLK is 1/6 of OPCLK. OPCLK is the system clock pre-scaled by 1~16, controlled

by REG0/REG_CLK bit[3:0]. The detect start clock is controlled by REG9/REG_DDIV

bit[7:0].

For example, given the system clock input of 18Mhz, and REG0/REG_CLK bit[3:0]

value is 2 (divide by 3), then OPCLK is 6Mhz and PCLK is 1Mhz.

3.2 Configuring gain and range of pre-amp and ADC

Divide by

div_opclk

Clock from

external

oscillator

Divide

by 6

Divide by

4096

PCLK

OPCLK

Divide by

(DDIV+1)

detect

start

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Two cascaded programmable gain amplifier are used for conditioning the sensor signal

before converted by ADC. Register REG1/REG_PGA bit [1:0] is for the control of PGA1 gain,

and register REG1/REG_PGA bit [7:4] for the control of PGA2 gain.

The ADC bias current and input voltage range is controlled by BIAS, (VRT-VRB) and

VRB parameters in REG3/REG_ADC. See section 5.0 for the detail of the registers.

3.3 Command and registers

The SF104 operation is controlled by sending commands and setting control registers

through the SPI interface. The SF104 SPI interface follows the SPI protocol with CPHA=0

and CPOL=0 as SPI mode 0.

There are 6 command codes to program the chip:

160x160

Pixel

array

Sample

&hold ADC MCU

Gain

VRT

VCM

VRB

PGA1 PGA2

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command code name function read/write

0x01 rdata read pixel data R

0x02 start start scan W

0x03 status read status R

0xC0 srst software reset W

0x20+N rread read register R

0x40+N rwrite write register W

For the rread and rwrite command, the number N is the register address. The effective

N is in the range of 0x00 to 0x11.

The register content is summarized in the following table:

N Address Name Function RW Default

Value 76543210

0 0x00 reg_clk clock control RW 0

1 0x01 reg_pag pag control RW 0 en_test1 en_test0

2 0x02 reg_dcoc dc offset RW 0

3 0x03 reg_adc adc setting RW 0

4 0x04 reg_otp_addr OTP address RW 0

5 0x05 reg_otp_wdat OTP wirte data RW 0 otp_wd

6 0x06 reg_otp_mode OTP control RW 0 otp_prg otp_rst otp_ceb

7 0x07 reg_otp_rdat OTP read data RW

8 0x08 reg_deth finger detection threshold RW 0xFF

9 0x09 reg_ddiv clock divider for detection RW 0

10 0x0A reg_enab function enable bits RW 0 en_window en_inscan en_det en_sqwv lowcap en_osc en_analog

11 0x0B reg_mode mode control bits RW 0 en_intr

12 0x0C reg_llx windowing function setting RW 0

13 0x0D reg_lly windowing function setting RW 0

14 0x0E reg_urx windowing function setting RW 0x9F

15 0x0F reg_ury windowing function setting RW 0x9F

16 0x10 reg_chmd change mode W (N/A) ch_mode

17 0x11 reg_inscanline in scan detection line number RW 0x40

Reserve

Internal test

otp_rdat

test1 test0 div_opclk

pga2_gain pga1_gain

dc_offset

adc_bias adc_vrt adc_vrb

otp_yp

otp_ain

ury

in_scan_line

deth

ddiv

en_bits

llx

lly

urx

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3.4 SPI command protocol

Command and data are exchanged throught the SPI MISO and MOSI wires. Each byte

of data sent through the MOSI port brings back a received byte through the MISO port.

Commands can be cascaded one by another. The term “SPI command sequence” in

the following context is defined as a sequence of command code and data bytes exchange

within one active SPISEL strobe.

An SF104 command code may or may not have associated data. The “start” and “srst”

commands don’t have associated data, and take effect immediately after the command code

is sent.

For read/write data commands, the second byte will be the beginning of data byte or

bytes, as illustrated below:

 read command

 write command

Writing and reading a series of register content may look different. For writing to

consecutive registers, an internal address counter is incremented automatically after each

byte written. This design eliminates the need to repeat sending the 0x40+N command for

each byte. So the sequence of read/write commands may look like the following.

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 read sequence (the last command byte is a dummy command)

 write sequence

 read image sequence

In fact, except for the write register command (which writes a sequence of register

content), commands can be mixed in a single sequence like following:

 mixed mode of read image and status sequence

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3.5 Command code detail

Code 01 / RDATA command (read only)

 This command pumps image data from FIFO and sends it to host

Code 02 / START command (write only)

 This command starts fingerprint image scan

Code 03 / status read command (read only)

 This command sends the 8-bit internal status flags to host.

 The status flags are defined as below

Bit Function

0 Data FIFO is “half full”

1 Data FIFO is empty

2 Data FIFO is “almost full”

3 Data FIFO is full

4 Image scan active

5 Detect interrupt flag

6 Detect result is OK

7 (not used)

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Code 0xC0 / SRST command (write only)

 This command generates a software reset to the system. Its effect is the same as

hardware reset except that the register content is left unchanged.

Code 0x2N / register read command

 This command starts reading register at address N

 At least to bytes needs to be written, the first byte is the command code, and the second

(dummy) byte is for the register content.

 Subsequent register read command can be cascaded in one command sequence.

Code 0x4N / register write command

 This command starts writing registers starting at address N

 The first byte is the command code, followed by subsequent bytes that are written to

registers starting at the specified starting address N.



Code 0x3E, 0x3F / Chip ID read command

 These two command read back the chip id of high and low byte

0x3E : Chip ID High Byte – Value 0x01 for SF104.

0x3F : Chip ID Low Byte – Value 0x04 for SF104.

All command code as the first byte in a command sequence returns the state byte

(which can be explicitly read by the 03 command).

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3.6 Register detail

REGISTER

NAME

ADD

R R/W Bit(s) DEFAULT DESCRIPTION

REG_CLK 0 R/W

0000_0000 Clock control

[7:6]

Test mode 1

00 : AREGC[2]

01 : TESTPIN = VREF

10 : TESTPIN = VINPTST

11 : AREGC[0]

[5:4]

Test mode 0

00 : AREGC[3]

01 : TESTPIN = VAMP

10 : TESTPIN = CDS

11 : invert ADC data, TESTPIN = VGND

[3:0]

DIV_OPCLK

The 4-bit DIV_OPCLK value (0~15) is the divider defining the ratio between

system clock (OSC) and opclk:

opclk_freq = sysclk_freq / (DIV_OPCLK + 1)

REG_PGA 1 R/W

0100_0000 PGA Gain Control

[7:4] PGA2_GAIN

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For the gain control of PGA2

PGA2 gain =PGA_gain*[(Vinp_pga-Vinn_pga)+Voff]/[2*(VRT-VRB)]*255

[3]

EN_TEST1

0 : Disable Test mode 1

1 : Enable Test mode 1

[2]

EN_TEST0

0 : Disable Test mode 0

1 : Enable Test mode 0

[1:0]

PGA1_GAIN

00 : 4.6

01 : 7.6

10 : 12.8

11 : 22.7

REG_DCOC 2 R/W

0000_0000 DC_OFFSET - DC offset control of PGA2

[7]

Sign bit

0 : negative

1 : positive

[6:0]

Offset compensated voltage

The DC offset voltage is set as the following formula:

Voff=0.4545*(2*B7-1)*[<B6:B0>/128*(VRT-VRB)+Vos1]

Vos1 ~ N(μ1,σ1) normal distribution, μ1=0 & σ1~=3.5mV~5mV

REG_ADC 3 R/W

0010_0101 Adc setting

[7] Not used

[6:4] ADC_BIAS

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ADC bias current settings

000 : 8uA

001 : 12uA

010 : 16uA (default)

011 : 20uA

1xx : 24uA

[3:2]

ADC_VRT

(VRT-VRB) settings:

00 : 0.90V

01 : 1.05V (default)

10 : 1.20V

11 : 1.35V

[1:0]

ADC_VRB

VRB settings:

00 : 0.800V

01 : 0.844V (default)

10 : 0.933V

11 : 0.978V

REG_OTP_A

DDR

4 RW

0000_0000 OTP address

[7:5] Not used

[4:0]

OTP_YP

Byte address

REG_OTP_

WDAT

5 RW

0000_0000 OTP write data

[7:4] Not used

[3:1] OTP_AIN

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Bit address for writing

[0]

OTP_WD

Write data

REG_OTP_

MODE

6 RW

0000_0000 OTP control

[7:3] Not used

[2]

OTP_PRG

OTP “PRG” control bit (Program enable)

[1]

OTP_RST

OTP “RST” control bit (Reset)

[0]

OTP_CEB

OTP “CEB” control bit (Enable, active low)

REG_OTP_R

DAT

7 R

OTP read data

[7:0]

OTP_RDAT

OTP read data

REG_DETH 8 RW

1111_1111 Detection threshold

[7:0]

DETH

Finger detection threshold value

See the “finger detection” section below

REG_DDIV 9 RW

0000_0000 Clock divider for detection interval

[7:0]

DDIV

A clock divider for finger detection interval

See the “finger detection” section below

REG_ENAB A RW 0000_0000 Enable bits

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[7]

EN_WINDOW

Enable windowing mode

The windowing size is assigned by reg_llx, reg_lly, reg_urx and reg_ury

(0x0C~0x0F)

0 : Disable

1 : Enabl

[6]

EN_INSCAN_DET

Enable the in scan line detection mode

The finger detection scan line can be changed according to value of

reg_inscanline (0x11) if enable

0 : Disable

1 : Enable

[5]

EN_DET

Enable the detect mode

0 : Disable

1 : Enable

[4] Reserve

[3]

LOWCAP

Enable the low capacitance mode for the sensor array

0 : High capacitor (96ff), compensation capacitor (1.05 pF)

1 : Low capacitor (48ff), compensation capacitor (2.57 pF)

[2]

EN_OSC

Enable internal clock oscillator

0 : Disable

1 : Enable

[1] Not used

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[0]

EN_ANALOG

Enable analog circuit

0 : Disable

1 : Enable

REG_MODE B RW

0000_0000 Mode control bits

[7] Not used

[6]

EN_INTR

Enable detect interrupt

0 : Disable

1 : Enable

[5] Not used

[4:0]

ENBITS

Must be set to value 21 (0x15H) to enable the chip

REG_LLX C RW

0000_0000 Windowing function position setting

[7:0] LLX

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