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Silicon Labs EFM32 Giant Gecko 11 Family , EFM32GG11 Reference guide

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EFM32 Giant Gecko 11 Family
Reference Manual
The EFM32 Giant Gecko Series 1 MCUs are the world’s most
energy-friendly microcontrollers, featuring new connectivity interfa-
ces and user interface features.
EFM32GG11 includes a powerful 32-bit ARM
®
Cortex
®
-M4 and provides robust security
via a unique cryptographic hardware engine supporting AES, ECC, SHA, and True Ran-
dom Number Generator (TRNG). New features include an SD/MMC/SDIO controller, Oc-
tal/Quad-SPI memory controller, 10/100 Ethernet MAC, CAN bus controller, highly robust
capacitive sensing, enhanced alpha blending graphics engine, and LESENSE/PCNT en-
hancements for smart energy meters. These features, combined with ultra-low current
active mode and short wake-up time from energy-saving modes, make EFM32GG11 mi-
crocontrollers well suited for any battery-powered application, as well as other systems
requiring high performance and low-energy consumption.
Example applications:
ENERGY FRIENDLY FEATURES
• ARM Cortex-M4 at 72 MHz
• Ultra low energy operation in active and
sleep modes
• Octal/Quad-SPI memory interface w/ XIP
• SD/MMC/SDIO Host Controller
• 10/100 Ethernet MAC with 802.3az EEE,
IEEE1588
• Dual CAN 2.0 Bus Controller
• Crystal-free low-energy USB
• Hardware cryptographic engine supports
AES, ECC, SHA, and TRNG
• Robust capacitive touch sense
• Footprint compatible with select EFM32
packages
• 5 V tolerant I/O
• Smart energy meters
• Industrial and factory automation
• Home automation and security
• Mid- and high-tier wearables
• IoT devices
32-bit bus
Lowest power mode with peripheral operational:
EM2 – Deep Sleep
EM1 - Sleep
EM4H - Hibernate
EM4S - Shutoff
EM0 - Active
EM3 - Stop
Core / Memory
Flash Program
Memory
RAM Memory
ARM Cortex
TM
M4 processor
with FPU and
MPU
Debug Interface
LDMA
Controller
ETM
Other
CRYPTO
CRC
Energy Management
Brown-Out
Detector
DC-DC
Converter
Voltage
Regulator
Voltage/Temp
Monitor
Power-On Reset
Clock Management
High Frequency
RC Oscillator
Ultra Low Freq.
RC Oscillator
Universal HF RC
Oscillator
Low Frequency
Crystal Oscillator
Low Frequency
RC Oscillator
Auxiliary High
Freq. RC Osc.
High Frequency
Crystal Oscillator
PLL
Analog Interfaces
Low Energy LCD
Controller
IDAC
Operational
Amplifier
ADC
VDAC
Analog
Comparator
Capacitive
Sensing
Backup Domain
Peripheral Reflex System
Serial Interfaces
UART
I
2
C
LEUSB
(crystal free)
SD / MMC / SDIO
I/O Ports Timers and Triggers
Low Energy
Sensor IF
Timer/Counter
Low Energy Timer
Watchdog Timer
CRYOTIMER
External
Interrupts
Pin Reset
EBI + pixel-alpha
General
Purpose I/O
Pin Wakeup
TFT Driver
Real Time Counter
and Calendar
Pulse Counter
Real Time Counter
Quad-SPI
USART
Low Energy
UART
TM
CAN
10/100 Ethernet
True Random
Number Generator
SMU
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Table of Contents
1. About This Document ........................... 41
1.1 Introduction...............................41
1.2 Conventions ..............................41
1.3 Related Documentation ..........................42
2. System Overview ............................. 43
2.1 Introduction...............................43
2.2 Features................................43
2.3 Block Diagram..............................46
2.4 Energy Modes..............................47
2.5 Timers ................................48
3. System Processor ............................ 49
3.1 Introduction...............................49
3.2 Features................................50
3.3 Functional Description ...........................50
3.3.1 Interrupt Operation ..........................51
3.3.2 Interrupt Request Lines (IRQ) ......................52
4. Memory and Bus System .......................... 54
4.1 Introduction...............................55
4.2 Functional Description ...........................56
4.2.1 Peripheral Non-Word Access Behavior ...................57
4.2.2 Bit-banding .............................58
4.2.3 Peripheral Bit Set and Clear .......................59
4.2.4 Peripherals .............................60
4.2.5 Bus Matrix .............................62
4.3 Access to Low Energy Peripherals (Asynchronous Registers) ..............64
4.3.1 Writing ..............................65
4.3.2 Reading ..............................67
4.3.3 FREEZE Register ..........................67
4.4 Flash .................................67
4.5 SRAM ................................68
4.5.1 ECC (Error Correcting Code).......................68
4.6 DI Page Entry Map ............................69
4.7 DI Page Entry Description ..........................72
4.7.1 CAL - CRC of DI-page and calibration temperature ...............72
4.7.2 MODULEINFO - Module trace information ..................73
4.7.3 MODXOCAL - Module Crystal Oscillator Calibration ..............74
4.7.4 EXTINFO - External Component description .................75
4.7.5 EUI48L - EUI48 OUI and Unique identifier ..................76
4.7.6 EUI48H - OUI ...........................76
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4.7.7 CUSTOMINFO - Custom information ...................76
4.7.8 MEMINFO - Flash page size and misc. chip information .............77
4.7.9 UNIQUEL - Low 32 bits of device unique number ...............78
4.7.10 UNIQUEH - High 32 bits of device unique number ...............78
4.7.11 MSIZE - Flash and SRAM Memory size in kB ................78
4.7.12 PART - Part description ........................79
4.7.13 DEVINFOREV - Device information page revision ...............81
4.7.14 EMUTEMP - EMU Temperature Calibration Information .............81
4.7.15 ADC0CAL0 - ADC0 calibration register 0 ..................82
4.7.16 ADC0CAL1 - ADC0 calibration register 1 ..................83
4.7.17 ADC0CAL2 - ADC0 calibration register 2 ..................84
4.7.18 ADC0CAL3 - ADC0 calibration register 3 ..................84
4.7.19 ADC1CAL0 - ADC1 calibration register 0 ..................85
4.7.20 ADC1CAL1 - ADC1 calibration register 1 ..................86
4.7.21 ADC1CAL2 - ADC1 calibration register 2 ..................87
4.7.22 ADC1CAL3 - ADC1 calibration register 3 ..................87
4.7.23 HFRCOCAL0 - HFRCO Calibration Register (4 MHz) ..............88
4.7.24 HFRCOCAL3 - HFRCO Calibration Register (7 MHz) ..............89
4.7.25 HFRCOCAL6 - HFRCO Calibration Register (13 MHz) .............90
4.7.26 HFRCOCAL7 - HFRCO Calibration Register (16 MHz) .............91
4.7.27 HFRCOCAL8 - HFRCO Calibration Register (19 MHz) .............92
4.7.28 HFRCOCAL10 - HFRCO Calibration Register (26 MHz) .............93
4.7.29 HFRCOCAL11 - HFRCO Calibration Register (32 MHz) .............94
4.7.30 HFRCOCAL12 - HFRCO Calibration Register (38 MHz) .............95
4.7.31 HFRCOCAL13 - HFRCO Calibration Register (48 MHz) .............96
4.7.32 HFRCOCAL14 - HFRCO Calibration Register (56 MHz) .............97
4.7.33 HFRCOCAL15 - HFRCO Calibration Register (64 MHz) .............98
4.7.34 HFRCOCAL16 - HFRCO Calibration Register (72 MHz) .............99
4.7.35 AUXHFRCOCAL0 - AUXHFRCO Calibration Register (4 MHz) .........100
4.7.36 AUXHFRCOCAL3 - AUXHFRCO Calibration Register (7 MHz) .........101
4.7.37 AUXHFRCOCAL6 - AUXHFRCO Calibration Register (13 MHz) .........102
4.7.38 AUXHFRCOCAL7 - AUXHFRCO Calibration Register (16 MHz) .........103
4.7.39 AUXHFRCOCAL8 - AUXHFRCO Calibration Register (19 MHz) .........104
4.7.40 AUXHFRCOCAL10 - AUXHFRCO Calibration Register (26 MHz) ........105
4.7.41 AUXHFRCOCAL11 - AUXHFRCO Calibration Register (32 MHz) .........106
4.7.42 AUXHFRCOCAL12 - AUXHFRCO Calibration Register (38 MHz) ........107
4.7.43 AUXHFRCOCAL13 - AUXHFRCO Calibration Register (48 MHz) ........108
4.7.44 AUXHFRCOCAL14 - AUXHFRCO Calibration Register (50 MHz) ........109
4.7.45 VMONCAL0 - VMON Calibration Register 0 ................110
4.7.46 VMONCAL1 - VMON Calibration Register 1 ................111
4.7.47 VMONCAL2 - VMON Calibration Register 2 ................112
4.7.48 IDAC0CAL0 - IDAC0 Calibration Register 0 ................113
4.7.49 IDAC0CAL1 - IDAC0 Calibration Register 1 ................114
4.7.50 DCDCLNVCTRL0 - DCDC Low-noise VREF Trim Register 0 ..........114
4.7.51 DCDCLPVCTRL0 - DCDC Low-power VREF Trim Register 0 ..........115
4.7.52 DCDCLPVCTRL1 - DCDC Low-power VREF Trim Register 1 ..........116
4.7.53 DCDCLPVCTRL2 - DCDC Low-power VREF Trim Register 2 ..........117
4.7.54 DCDCLPVCTRL3 - DCDC Low-power VREF Trim Register 3 ..........118
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4.7.55 DCDCLPCMPHYSSEL0 - DCDC LPCMPHYSSEL Trim Register 0 ........118
4.7.56 DCDCLPCMPHYSSEL1 - DCDC LPCMPHYSSEL Trim Register 1 ........119
4.7.57 VDAC0MAINCAL - VDAC0 Cals for Main Path ...............120
4.7.58 VDAC0ALTCAL - VDAC0 Cals for Alternate Path ..............121
4.7.59 VDAC0CH1CAL - VDAC0 CH1 Error Cal .................122
4.7.60 OPA0CAL0 - OPA0 Calibration Register for DRIVESTRENGTH 0, INCBW=1 ....123
4.7.61 OPA0CAL1 - OPA0 Calibration Register for DRIVESTRENGTH 1, INCBW=1 ....124
4.7.62 OPA0CAL2 - OPA0 Calibration Register for DRIVESTRENGTH 2, INCBW=1 ....125
4.7.63 OPA0CAL3 - OPA0 Calibration Register for DRIVESTRENGTH 3, INCBW=1 ....126
4.7.64 OPA0CAL4 - OPA0 Calibration Register for DRIVESTRENGTH 0, INCBW=0 ....127
4.7.65 OPA0CAL5 - OPA0 Calibration Register for DRIVESTRENGTH 1, INCBW=0 ....128
4.7.66 OPA0CAL6 - OPA0 Calibration Register for DRIVESTRENGTH 2, INCBW=0 ....129
4.7.67 OPA0CAL7 - OPA0 Calibration Register for DRIVESTRENGTH 3, INCBW=0 ....130
4.7.68 OPA1CAL0 - OPA1 Calibration Register for DRIVESTRENGTH 0, INCBW=1 ....131
4.7.69 OPA1CAL1 - OPA1 Calibration Register for DRIVESTRENGTH 1, INCBW=1 ....132
4.7.70 OPA1CAL2 - OPA1 Calibration Register for DRIVESTRENGTH 2, INCBW=1 ....133
4.7.71 OPA1CAL3 - OPA1 Calibration Register for DRIVESTRENGTH 3, INCBW=1 ....134
4.7.72 OPA1CAL4 - OPA1 Calibration Register for DRIVESTRENGTH 0, INCBW=0 ....135
4.7.73 OPA1CAL5 - OPA1 Calibration Register for DRIVESTRENGTH 1, INCBW=0 ....136
4.7.74 OPA1CAL6 - OPA1 Calibration Register for DRIVESTRENGTH 2, INCBW=0 ....137
4.7.75 OPA1CAL7 - OPA1 Calibration Register for DRIVESTRENGTH 3, INCBW=0 ....138
4.7.76 OPA2CAL0 - OPA2 Calibration Register for DRIVESTRENGTH 0, INCBW=1 ....139
4.7.77 OPA2CAL1 - OPA2 Calibration Register for DRIVESTRENGTH 1, INCBW=1 ....140
4.7.78 OPA2CAL2 - OPA2 Calibration Register for DRIVESTRENGTH 2, INCBW=1 ....141
4.7.79 OPA2CAL3 - OPA2 Calibration Register for DRIVESTRENGTH 3, INCBW=1 ....142
4.7.80 OPA2CAL4 - OPA2 Calibration Register for DRIVESTRENGTH 0, INCBW=0 ....143
4.7.81 OPA2CAL5 - OPA2 Calibration Register for DRIVESTRENGTH 1, INCBW=0 ....144
4.7.82 OPA2CAL6 - OPA2 Calibration Register for DRIVESTRENGTH 2, INCBW=0 ....145
4.7.83 OPA2CAL7 - OPA2 Calibration Register for DRIVESTRENGTH 3, INCBW=0 ....146
4.7.84 OPA3CAL0 - OPA3 Calibration Register for DRIVESTRENGTH 0, INCBW=1 ....147
4.7.85 OPA3CAL1 - OPA3 Calibration Register for DRIVESTRENGTH 1, INCBW=1 ....148
4.7.86 OPA3CAL2 - OPA3 Calibration Register for DRIVESTRENGTH 2, INCBW=1 ....149
4.7.87 OPA3CAL3 - OPA3 Calibration Register for DRIVESTRENGTH 3, INCBW=1 ....150
4.7.88 OPA3CAL4 - OPA3 Calibration Register for DRIVESTRENGTH 0, INCBW=0 ....151
4.7.89 OPA3CAL5 - OPA3 Calibration Register for DRIVESTRENGTH 1, INCBW=0 ....152
4.7.90 OPA3CAL6 - OPA3 Calibration Register for DRIVESTRENGTH 2, INCBW=0 ....153
4.7.91 OPA3CAL7 - OPA3 Calibration Register for DRIVESTRENGTH 3, INCBW=0 ....154
4.7.92 CSENGAINCAL - Cap Sense Gain Adjustment ...............155
4.7.93 USHFRCOCAL7 - USHFRCO Calibration Register (16 MHz) ..........156
4.7.94 USHFRCOCAL11 - USHFRCO Calibration Register (32 MHz) ..........157
4.7.95 USHFRCOCAL13 - USHFRCO Calibration Register (48 MHz) ..........158
4.7.96 USHFRCOCAL14 - USHFRCO Calibration Register (50 MHz) ..........159
4.7.97 CURRMON5V - 5V Current monitor Transconductance ............159
5. DBG - Debug Interface ...........................160
5.1 Introduction..............................160
5.2 Features...............................160
5.3 Functional Description ..........................160
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5.3.1 Debug Pins............................161
5.3.2 Embedded Trace Macrocell V3.5 (ETM) ..................161
5.3.3 Debug and EM2 DeepSleep/EM3 Stop ..................161
5.3.4 Authentication Access Point ......................161
5.3.5 Debug Lock ...........................162
5.3.6 AAP Lock ............................163
5.3.7 Debugger Reads of Actionable Registers .................163
5.3.8 Debug Recovery ..........................163
5.4 Register Map .............................163
5.5 Register Description ...........................164
5.5.1 AAP_CMD - Command Register ....................164
5.5.2 AAP_CMDKEY - Command Key Register .................164
5.5.3 AAP_STATUS - Status Register ....................165
5.5.4 AAP_CTRL - Control Register .....................165
5.5.5 AAP_CRCCMD - CRC Command Register ................166
5.5.6 AAP_CRCSTATUS - CRC Status Register .................166
5.5.7 AAP_CRCADDR - CRC Address Register .................167
5.5.8 AAP_CRCRESULT - CRC Result Register .................167
5.5.9 AAP_IDR - AAP Identification Register ..................168
6. MSC - Memory System Controller ......................169
6.1 Introduction..............................169
6.2 Features...............................170
6.3 Functional Description ..........................171
6.3.1 User Data (UD) Page Description ....................171
6.3.2 Lock Bits (LB) Page Description.....................172
6.3.3 Device Information (DI) Page .....................173
6.3.4 Bootloader ............................173
6.3.5 Device Revision ..........................173
6.3.6 Post-reset Behavior .........................173
6.3.7 Flash Startup ...........................174
6.3.8 Wait-states ............................174
6.3.9 Suppressed Conditional Branch Target Prefetch (SCBTP) ............175
6.3.10 Cortex-M4 If-Then Block Folding ....................175
6.3.11 Instruction Cache .........................176
6.3.12 Low Voltage Flash Read .......................177
6.3.13 Bank Switching Operation ......................177
6.3.14 Erase and Write Operations......................178
6.4 Register Map .............................179
6.5 Register Description ...........................180
6.5.1 MSC_CTRL - Memory System Control Register ...............180
6.5.2 MSC_READCTRL - Read Control Register ................182
6.5.3 MSC_WRITECTRL - Write Control Register ................183
6.5.4 MSC_WRITECMD - Write Command Register ...............184
6.5.5 MSC_ADDRB - Page Erase/Write Address Buffer ..............185
6.5.6 MSC_WDATA - Write Data Register ...................185
6.5.7 MSC_STATUS - Status Register ....................186
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6.5.8 MSC_IF - Interrupt Flag Register ....................187
6.5.9 MSC_IFS - Interrupt Flag Set Register ..................189
6.5.10 MSC_IFC - Interrupt Flag Clear Register .................191
6.5.11 MSC_IEN - Interrupt Enable Register ..................193
6.5.12 MSC_LOCK - Configuration Lock Register ................194
6.5.13 MSC_CACHECMD - Flash Cache Command Register ............195
6.5.14 MSC_CACHEHITS - Cache Hits Performance Counter ............195
6.5.15 MSC_CACHEMISSES - Cache Misses Performance Counter ..........196
6.5.16 MSC_MASSLOCK - Mass Erase Lock Register ..............197
6.5.17 MSC_STARTUP - Startup Control ...................198
6.5.18 MSC_BANKSWITCHLOCK - Bank Switching Lock Register ..........199
6.5.19 MSC_CMD - Command Register ...................200
6.5.20 MSC_BOOTLOADERCTRL - Bootloader Read and Write Enable, Write Once Register . 200
6.5.21 MSC_AAPUNLOCKCMD - Software Unlock AAP Command Register .......201
6.5.22 MSC_CACHECONFIG0 - Cache Configuration Register 0 ...........202
6.5.23 MSC_RAMCTRL - RAM Control Enable Register ..............203
6.5.24 MSC_ECCCTRL - RAM ECC Control Register ...............204
6.5.25 MSC_RAMECCADDR - RAM ECC Error Address Register ...........204
6.5.26 MSC_RAM1ECCADDR - RAM1 ECC Error Address Register ..........205
7. LDMA - Linked DMA Controller........................206
7.1 Introduction..............................206
7.1.1 Features ............................207
7.2 Block Diagram.............................208
7.3 Functional Description ..........................209
7.3.1 Channel Descriptor .........................209
7.3.2 Channel Configuration ........................214
7.3.3 Channel Select Configuration .....................214
7.3.4 Starting a Transfer .........................214
7.3.5 Managing Transfer Errors .......................215
7.3.6 Arbitration ............................215
7.3.7 Channel Descriptor Data Structure ....................217
7.3.8 Interaction With the EMU .......................221
7.3.9 Interrupts ............................221
7.3.10 Debugging ...........................221
7.4 Examples ..............................221
7.4.1 Single Direct Register DMA Transfer ...................222
7.4.2 Descriptor Linked List ........................223
7.4.3 Single Descriptor Looped Transfer ....................225
7.4.4 Descriptor List With Looping ......................226
7.4.5 Simple Inter-Channel Synchronization...................227
7.4.6 2D Copy.............................229
7.4.7 Ping-Pong ............................231
7.4.8 Scatter-Gather ..........................232
7.5 Register Map .............................233
7.6 Register Description ...........................234
7.6.1 LDMA_CTRL - DMA Control Register ..................234
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7.6.2 LDMA_STATUS - DMA Status Register ..................235
7.6.3 LDMA_SYNC - DMA Synchronization Trigger Register (Single-Cycle RMW) .....236
7.6.4 LDMA_CHEN - DMA Channel Enable Register (Single-Cycle RMW) ........236
7.6.5 LDMA_CHBUSY - DMA Channel Busy Register ...............237
7.6.6 LDMA_CHDONE - DMA Channel Linking Done Register (Single-Cycle RMW) .....237
7.6.7 LDMA_DBGHALT - DMA Channel Debug Halt Register ............238
7.6.8 LDMA_SWREQ - DMA Channel Software Transfer Request Register ........238
7.6.9 LDMA_REQDIS - DMA Channel Request Disable Register ...........239
7.6.10 LDMA_REQPEND - DMA Channel Requests Pending Register .........239
7.6.11 LDMA_LINKLOAD - DMA Channel Link Load Register ............240
7.6.12 LDMA_REQCLEAR - DMA Channel Request Clear Register ..........240
7.6.13 LDMA_IF - Interrupt Flag Register ...................241
7.6.14 LDMA_IFS - Interrupt Flag Set Register .................241
7.6.15 LDMA_IFC - Interrupt Flag Clear Register ................242
7.6.16 LDMA_IEN - Interrupt Enable Register .................242
7.6.17 LDMA_CHx_REQSEL - Channel Peripheral Request Select Register .......243
7.6.18 LDMA_CHx_CFG - Channel Configuration Register .............249
7.6.19 LDMA_CHx_LOOP - Channel Loop Counter Register ............250
7.6.20 LDMA_CHx_CTRL - Channel Descriptor Control Word Register .........251
7.6.21 LDMA_CHx_SRC - Channel Descriptor Source Data Address Register ......254
7.6.22 LDMA_CHx_DST - Channel Descriptor Destination Data Address Register .....254
7.6.23 LDMA_CHx_LINK - Channel Descriptor Link Structure Address Register ......255
8. RMU - Reset Management Unit ........................256
8.1 Introduction..............................256
8.2 Features...............................256
8.3 Functional Description ..........................257
8.3.1 Reset Levels ...........................258
8.3.2 RMU_RSTCAUSE Register ......................259
8.3.3 Power-On Reset (POR) .......................260
8.3.4 Brown-Out Detector (BOD) ......................260
8.3.5 RESETn Pin Reset .........................261
8.3.6 Watchdog Reset ..........................261
8.3.7 Lockup Reset ...........................261
8.3.8 System Reset Request ........................261
8.3.9 Reset State ...........................261
8.3.10 Register Reset Signals .......................261
8.4 Register Map .............................263
8.5 Register Description ...........................264
8.5.1 RMU_CTRL - Control Register .....................264
8.5.2 RMU_RSTCAUSE - Reset Cause Register ................266
8.5.3 RMU_CMD - Command Register ....................267
8.5.4 RMU_RST - Reset Control Register ...................267
8.5.5 RMU_LOCK - Configuration Lock Register .................268
9. EMU - Energy Management Unit .......................269
9.1 Introduction..............................269
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9.2 Features...............................270
9.3 Functional Description ..........................271
9.3.1 Energy Modes...........................272
9.3.2 Entering Low Energy Modes ......................276
9.3.3 Exiting a Low Energy Mode ......................278
9.3.4 Power Configurations ........................279
9.3.5 DC-to-DC Interface .........................283
9.3.6 Analog Peripheral Power Selection....................284
9.3.7 Digital LDO Power Selection ......................285
9.3.8 IOVDD Connection .........................285
9.3.9 Voltage Scaling ..........................285
9.3.10 EM2/EM3 Peripheral Retention Disable ..................287
9.3.11 Brown Out Detector (BOD) ......................287
9.3.12 Voltage Monitor (VMON) .......................289
9.3.13 Powering Off SRAM Blocks ......................290
9.3.14 5 V Sub-System..........................290
9.3.15 Temperature Sensor ........................302
9.3.16 Registers latched in EM4 ......................302
9.3.17 Register Resets..........................302
9.3.18 Backup Power Domain .......................303
9.4 Register Map .............................306
9.5 Register Description ...........................308
9.5.1 EMU_CTRL - Control Register .....................308
9.5.2 EMU_STATUS - Status Register ....................310
9.5.3 EMU_LOCK - Configuration Lock Register .................312
9.5.4 EMU_RAM0CTRL - Memory Control Register ...............313
9.5.5 EMU_CMD - Command Register ....................314
9.5.6 EMU_EM4CTRL - EM4 Control Register .................315
9.5.7 EMU_TEMPLIMITS - Temperature Limits for Interrupt Generation .........316
9.5.8 EMU_TEMP - Value of Last Temperature Measurement ............316
9.5.9 EMU_IF - Interrupt Flag Register ....................317
9.5.10 EMU_IFS - Interrupt Flag Set Register ..................319
9.5.11 EMU_IFC - Interrupt Flag Clear Register .................321
9.5.12 EMU_IEN - Interrupt Enable Register ..................324
9.5.13 EMU_PWRLOCK - Regulator and Supply Lock Register ...........326
9.5.14 EMU_PWRCTRL - Power Control Register ................327
9.5.15 EMU_DCDCCTRL - DCDC Control ...................328
9.5.16 EMU_DCDCMISCCTRL - DCDC Miscellaneous Control Register ........329
9.5.17 EMU_DCDCZDETCTRL - DCDC Power Train NFET Zero Current Detector Control Register
................................331
9.5.18 EMU_DCDCCLIMCTRL - DCDC Power Train PFET Current Limiter Control Register ..332
9.5.19 EMU_DCDCLNCOMPCTRL - DCDC Low Noise Compensator Control Register ...333
9.5.20 EMU_DCDCLNVCTRL - DCDC Low Noise Voltage Register ..........334
9.5.21 EMU_DCDCLPVCTRL - DCDC Low Power Voltage Register ..........335
9.5.22 EMU_DCDCLPCTRL - DCDC Low Power Control Register ..........336
9.5.23 EMU_DCDCLNFREQCTRL - DCDC Low Noise Controller Frequency Control ....337
9.5.24 EMU_DCDCSYNC - DCDC Read Status Register ..............337
9.5.25 EMU_VMONAVDDCTRL - VMON AVDD Channel Control ...........338
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9.5.26 EMU_VMONALTAVDDCTRL - Alternate VMON AVDD Channel Control ......339
9.5.27 EMU_VMONDVDDCTRL - VMON DVDD Channel Control ...........340
9.5.28 EMU_VMONIO0CTRL - VMON IOVDD0 Channel Control ...........341
9.5.29 EMU_VMONIO1CTRL - VMON IOVDD1 Channel Control ...........342
9.5.30 EMU_VMONBUVDDCTRL - VMON BUVDD Channel Control ..........343
9.5.31 EMU_RAM1CTRL - Memory Control Register ...............344
9.5.32 EMU_RAM2CTRL - Memory Control Register ...............345
9.5.33 EMU_BUCTRL - Backup Power Configuration Register ............346
9.5.34 EMU_R5VCTRL - 5V Regulator Control .................348
9.5.35 EMU_R5VADCCTRL - 5V Regulator Control ...............349
9.5.36 EMU_R5VOUTLEVEL - 5V Regulator Voltage Select .............349
9.5.37 EMU_R5VDETCTRL - 5V Detector Enables ................350
9.5.38 EMU_DCDCLPEM01CFG - Configuration Bits for Low Power Mode to Be Applied During
EM01, This Field is Only Relevant If LP Mode is Used in EM01 ...........351
9.5.39 EMU_R5VSTATUS - 5V Detector Status Register ..............352
9.5.40 EMU_R5VSYNC - 5V Read Status Register ................353
9.5.41 EMU_EM23PERNORETAINCMD - Clears Corresponding Bits in EM23PERNORETAINSTA-
TUS Unlocking Access to Peripheral ....................354
9.5.42 EMU_EM23PERNORETAINSTATUS - Status Indicating If Peripherals Were Powered Down in
EM23, Subsequently Locking Access to It ..................356
9.5.43 EMU_EM23PERNORETAINCTRL - When Set Corresponding Peripherals May Get Powered
Down in EM23 ...........................359
10. CMU - Clock Management Unit .......................361
10.1 Introduction .............................361
10.2 Features ..............................362
10.3 Functional Description .........................363
10.3.1 System Clocks ..........................365
10.3.2 Oscillators ...........................371
10.3.3 Configuration for Operating Frequencies .................388
10.3.4 Energy Modes ..........................390
10.3.5 Clock Output on a Pin........................391
10.3.6 Clock Input From a Pin .......................391
10.3.7 Clock Output on PRS ........................391
10.3.8 Error Handling ..........................392
10.3.9 Interrupts ............................392
10.3.10 Wake-up ............................392
10.3.11 Protection ...........................392
10.3.12 Digital Phase-Locked Loop .....................392
10.3.13 USB Clock Recovery .......................394
10.4 Register Map.............................395
10.5 Register Description ..........................397
10.5.1 CMU_CTRL - CMU Control Register ..................397
10.5.2 CMU_USHFRCOCTRL - USHFRCO Control Register ............400
10.5.3 CMU_HFRCOCTRL - HFRCO Control Register ..............402
10.5.4 CMU_AUXHFRCOCTRL - AUXHFRCO Control Register ...........404
10.5.5 CMU_LFRCOCTRL - LFRCO Control Register ...............405
10.5.6 CMU_HFXOCTRL - HFXO Control Register ................407
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10.5.7 CMU_HFXOCTRL1 - HFXO Control 1 ..................409
10.5.8 CMU_HFXOSTARTUPCTRL - HFXO Startup Control ............410
10.5.9 CMU_HFXOSTEADYSTATECTRL - HFXO Steady State Control .........411
10.5.10 CMU_HFXOTIMEOUTCTRL - HFXO Timeout Control ............412
10.5.11 CMU_LFXOCTRL - LFXO Control Register ................414
10.5.12 CMU_DPLLCTRL - DPLL Control Register ................416
10.5.13 CMU_DPLLCTRL1 - DPLL Control Register ...............417
10.5.14 CMU_CALCTRL - Calibration Control Register ..............418
10.5.15 CMU_CALCNT - Calibration Counter Register ..............420
10.5.16 CMU_OSCENCMD - Oscillator Enable/Disable Command Register .......421
10.5.17 CMU_CMD - Command Register ...................422
10.5.18 CMU_DBGCLKSEL - Debug Trace Clock Select ..............423
10.5.19 CMU_HFCLKSEL - High Frequency Clock Select Command Register ......424
10.5.20 CMU_LFACLKSEL - Low Frequency A Clock Select Register .........425
10.5.21 CMU_LFBCLKSEL - Low Frequency B Clock Select Register .........425
10.5.22 CMU_LFECLKSEL - Low Frequency E Clock Select Register .........426
10.5.23 CMU_LFCCLKSEL - Low Frequency C Clock Select Register .........426
10.5.24 CMU_STATUS - Status Register ...................427
10.5.25 CMU_HFCLKSTATUS - HFCLK Status Register ..............429
10.5.26 CMU_HFXOTRIMSTATUS - HFXO Trim Status ..............430
10.5.27 CMU_IF - Interrupt Flag Register ...................431
10.5.28 CMU_IFS - Interrupt Flag Set Register .................433
10.5.29 CMU_IFC - Interrupt Flag Clear Register ................435
10.5.30 CMU_IEN - Interrupt Enable Register .................437
10.5.31 CMU_HFBUSCLKEN0 - High Frequency Bus Clock Enable Register 0 ......439
10.5.32 CMU_HFPERCLKEN0 - High Frequency Peripheral Clock Enable Register 0 ....440
10.5.33 CMU_HFPERCLKEN1 - High Frequency Peripheral Clock Enable Register 1 ....442
10.5.34 CMU_LFACLKEN0 - Low Frequency a Clock Enable Register 0 (Async Reg) ....443
10.5.35 CMU_LFBCLKEN0 - Low Frequency B Clock Enable Register 0 (Async Reg) ....444
10.5.36 CMU_LFCCLKEN0 - Low Frequency C Clock Enable Register 0 (Async Reg) ....444
10.5.37 CMU_LFECLKEN0 - Low Frequency E Clock Enable Register 0 (Async Reg) ....445
10.5.38 CMU_HFPRESC - High Frequency Clock Prescaler Register .........446
10.5.39 CMU_HFBUSPRESC - High Frequency Bus Clock Prescaler Register ......447
10.5.40 CMU_HFCOREPRESC - High Frequency Core Clock Prescaler Register .....447
10.5.41 CMU_HFPERPRESC - High Frequency Peripheral Clock Prescaler Register ....448
10.5.42 CMU_HFEXPPRESC - High Frequency Export Clock Prescaler Register .....448
10.5.43 CMU_HFPERPRESCB - High Frequency Peripheral Clock Prescaler B Register ...449
10.5.44 CMU_HFPERPRESCC - High Frequency Peripheral Clock Prescaler C Register ...449
10.5.45 CMU_LFAPRESC0 - Low Frequency a Prescaler Register 0 (Async Reg) .....450
10.5.46 CMU_LFBPRESC0 - Low Frequency B Prescaler Register 0 (Async Reg) .....453
10.5.47 CMU_LFEPRESC0 - Low Frequency E Prescaler Register 0 (Async Reg) .....454
10.5.48 CMU_SYNCBUSY - Synchronization Busy Register .............455
10.5.49 CMU_FREEZE - Freeze Register ...................458
10.5.50 CMU_PCNTCTRL - PCNT Control Register ...............459
10.5.51 CMU_ADCCTRL - ADC Control Register ................461
10.5.52 CMU_SDIOCTRL - SDIO Control Register ................463
10.5.53 CMU_QSPICTRL - QSPI Control Register ................464
10.5.54 CMU_ROUTEPEN - I/O Routing Pin Enable Register ............465
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10.5.55 CMU_ROUTELOC0 - I/O Routing Location Register ............466
10.5.56 CMU_ROUTELOC1 - I/O Routing Location Register ............467
10.5.57 CMU_LOCK - Configuration Lock Register ................468
10.5.58 CMU_HFRCOSS - HFRCO Spread Spectrum Register ...........469
10.5.59 CMU_USBCTRL - USB Control Register ................470
10.5.60 CMU_USBCRCTRL - USB Clock Recovery Control .............471
11. SMU - Security Management Unit ......................472
11.1 Introduction .............................472
11.2 Features ..............................472
11.3 Functional Description..........................473
11.3.1 PPU - Peripheral Protection Unit ....................473
11.3.2 Programming Model ........................474
11.4 Register Map .............................475
11.5 Register Description ..........................476
11.5.1 SMU_IF - Interrupt Flag Register ...................476
11.5.2 SMU_IFS - Interrupt Flag Set Register ..................476
11.5.3 SMU_IFC - Interrupt Flag Clear Register .................477
11.5.4 SMU_IEN - Interrupt Enable Register ..................477
11.5.5 SMU_PPUCTRL - PPU Control Register .................478
11.5.6 SMU_PPUPATD0 - PPU Privilege Access Type Descriptor 0 ..........479
11.5.7 SMU_PPUPATD1 - PPU Privilege Access Type Descriptor 1 ..........482
11.5.8 SMU_PPUPATD2 - PPU Privilege Access Type Descriptor 2 ..........484
11.5.9 SMU_PPUFS - PPU Fault Status ...................485
12. RTCC - Real Time Counter and Calendar ...................488
12.1 Introduction .............................488
12.2 Features ..............................488
12.3 Functional Description .........................489
12.3.1 Counter ............................490
12.3.2 Capture/Compare Channels .....................494
12.3.3 Interrupts and PRS Output ......................496
12.3.4 Energy Mode Availability .......................497
12.3.5 Register Lock ..........................497
12.3.6 Oscillator Failure Detection ......................497
12.3.7 Retention Registers ........................497
12.3.8 Timestamp ...........................497
12.3.9 Debug Session ..........................497
12.4 Register Map.............................498
12.5 Register Description ..........................499
12.5.1 RTCC_CTRL - Control Register (Async Reg) ...............499
12.5.2 RTCC_PRECNT - Pre-Counter Value Register (Async Reg) ..........501
12.5.3 RTCC_CNT - Counter Value Register (Async Reg) .............501
12.5.4 RTCC_COMBCNT - Combined Pre-Counter and Counter Value Register ......502
12.5.5 RTCC_TIME - Time of Day Register (Async Reg) ..............503
12.5.6 RTCC_DATE - Date Register (Async Reg) ................504
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12.5.7 RTCC_IF - RTCC Interrupt Flags ...................505
12.5.8 RTCC_IFS - Interrupt Flag Set Register .................506
12.5.9 RTCC_IFC - Interrupt Flag Clear Register ................507
12.5.10 RTCC_IEN - Interrupt Enable Register .................508
12.5.11 RTCC_STATUS - Status Register ...................509
12.5.12 RTCC_CMD - Command Register ...................509
12.5.13 RTCC_SYNCBUSY - Synchronization Busy Register ............510
12.5.14 RTCC_POWERDOWN - Retention RAM Power-down Register (Async Reg) ....510
12.5.15 RTCC_LOCK - Configuration Lock Register (Async Reg) ...........511
12.5.16 RTCC_EM4WUEN - Wake Up Enable .................511
12.5.17 RTCC_CCx_CTRL - CC Channel Control Register (Async Reg) ........512
12.5.18 RTCC_CCx_CCV - Capture/Compare Value Register (Async Reg) ........514
12.5.19 RTCC_CCx_TIME - Capture/Compare Time Register (Async Reg) ........515
12.5.20 RTCC_CCx_DATE - Capture/Compare Date Register (Async Reg) .......516
12.5.21 RTCC_RETx_REG - Retention Register .................516
13. RTC - Real Time Counter .........................517
13.1 Introduction .............................517
13.2 Features ..............................517
13.3 Functional Description .........................518
13.3.1 Counter ............................518
13.3.2 Compare Channels ........................519
13.3.3 Interrupts ............................520
13.3.4 Debugrun ............................520
13.3.5 Using the RTC in EM3 .......................520
13.3.6 Register Access..........................520
13.4 Register Map.............................520
13.5 Register Description ..........................521
13.5.1 RTC_CTRL - Control Register (Async Reg) ................521
13.5.2 RTC_CNT - Counter Value Register ..................522
13.5.3 RTC_IF - Interrupt Flag Register ....................522
13.5.4 RTC_IFS - Interrupt Flag Set Register ..................523
13.5.5 RTC_IFC - Interrupt Flag Clear Register .................523
13.5.6 RTC_IEN - Interrupt Enable Register ..................524
13.5.7 RTC_COMPx_COMP - Compare Value Register X (Async Reg) .........524
14. WDOG - Watchdog Timer .........................525
14.1 Introduction .............................525
14.2 Features ..............................525
14.3 Functional Description .........................525
14.3.1 Clock Source ..........................526
14.3.2 Debug Functionality ........................526
14.3.3 Energy Mode Handling .......................526
14.3.4 Register Access..........................526
14.3.5 Warning Interrupt .........................526
14.3.6 Window Interrupt .........................527
14.3.7 PRS as Watchdog Clear .......................528
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14.3.8 PRS Rising Edge Monitoring .....................528
14.4 Register Map.............................529
14.5 Register Description ..........................530
14.5.1 WDOG_CTRL - Control Register (Async Reg) ...............530
14.5.2 WDOG_CMD - Command Register (Async Reg) ..............533
14.5.3 WDOG_SYNCBUSY - Synchronization Busy Register ............534
14.5.4 WDOGn_PCHx_PRSCTRL - PRS Control Register (Async Reg) .........535
14.5.5 WDOG_IF - Watchdog Interrupt Flags ..................536
14.5.6 WDOG_IFS - Interrupt Flag Set Register .................537
14.5.7 WDOG_IFC - Interrupt Flag Clear Register ................538
14.5.8 WDOG_IEN - Interrupt Enable Register .................539
15. PRS - Peripheral Reflex System .......................540
15.1 Introduction .............................540
15.2 Features ..............................540
15.3 Functional Description .........................541
15.3.1 Channel Functions .........................541
15.3.2 Producers............................542
15.3.3 Consumers ...........................543
15.3.4 Event on PRS ..........................544
15.3.5 DMA Request on PRS .......................544
15.3.6 Example ............................545
15.4 Register Map.............................545
15.5 Register Description ..........................546
15.5.1 PRS_SWPULSE - Software Pulse Register ................546
15.5.2 PRS_SWLEVEL - Software Level Register ................548
15.5.3 PRS_ROUTEPEN - I/O Routing Pin Enable Register .............550
15.5.4 PRS_ROUTELOC0 - I/O Routing Location Register .............552
15.5.5 PRS_ROUTELOC1 - I/O Routing Location Register .............554
15.5.6 PRS_ROUTELOC2 - I/O Routing Location Register .............556
15.5.7 PRS_ROUTELOC3 - I/O Routing Location Register .............558
15.5.8 PRS_ROUTELOC4 - I/O Routing Location Register .............560
15.5.9 PRS_ROUTELOC5 - I/O Routing Location Register .............562
15.5.10 PRS_CTRL - Control Register ....................564
15.5.11 PRS_DMAREQ0 - DMA Request 0 Register ...............566
15.5.12 PRS_DMAREQ1 - DMA Request 1 Register ...............568
15.5.13 PRS_PEEK - PRS Channel Values ..................570
15.5.14 PRS_CHx_CTRL - Channel Control Register ...............572
16. LCD - Liquid Crystal Display Driver .....................582
16.1 Introduction .............................582
16.2 Features ..............................582
16.3 Functional Description .........................583
16.3.1 Power Supply ..........................583
16.3.2 LCD Driver Enable .........................583
16.3.3 LCD Frame Rate and Power Reduction ..................584
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16.3.4 Multiplexing, Bias, and Wave Settings ..................585
16.3.5 LCD Contrast ..........................586
16.3.6 Voltage Levels and Mode Selection ...................587
16.3.7 Frame Rate ...........................587
16.3.8 Data Update ...........................588
16.3.9 Direct Segment Control (DSC) .....................589
16.3.10 Frame Counter (FC) ........................590
16.3.11 LCD Interrupt ..........................590
16.3.12 Blink, Blank, and Animation Features ..................590
16.3.13 LCD in Low Energy Modes .....................593
16.3.14 Register Access .........................593
16.3.15 Waveform Examples........................593
16.4 Register Map.............................614
16.5 Register Description ..........................615
16.5.1 LCD_CTRL - Control Register (Async Reg) ................615
16.5.2 LCD_DISPCTRL - Display Control Register ................616
16.5.3 LCD_SEGEN - Segment Enable Register ................618
16.5.4 LCD_BACTRL - Blink and Animation Control Register (Async Reg) ........619
16.5.5 LCD_STATUS - Status Register ....................621
16.5.6 LCD_AREGA - Animation Register a (Async Reg) ..............621
16.5.7 LCD_AREGB - Animation Register B (Async Reg) ..............622
16.5.8 LCD_IF - Interrupt Flag Register ....................622
16.5.9 LCD_IFS - Interrupt Flag Set Register ..................622
16.5.10 LCD_IFC - Interrupt Flag Clear Register .................623
16.5.11 LCD_IEN - Interrupt Enable Register ..................623
16.5.12 LCD_BIASCTRL - Analog BIAS Control .................624
16.5.13 LCD_SEGD0L - Segment Data Low Register 0 (Async Reg) ..........624
16.5.14 LCD_SEGD1L - Segment Data Low Register 1 (Async Reg) ..........625
16.5.15 LCD_SEGD2L - Segment Data Low Register 2 (Async Reg) ..........625
16.5.16 LCD_SEGD3L - Segment Data Low Register 3 (Async Reg) ..........626
16.5.17 LCD_SEGD0H - Segment Data High Register 0 (Async Reg) .........626
16.5.18 LCD_SEGD1H - Segment Data High Register 1 (Async Reg) .........627
16.5.19 LCD_SEGD2H - Segment Data High Register 2 (Async Reg) .........627
16.5.20 LCD_SEGD3H - Segment Data High Register 3 (Async Reg) .........628
16.5.21 LCD_SEGD4L - Segment Data Low Register 4 (Async Reg) ..........628
16.5.22 LCD_SEGD5L - Segment Data Low Register 5 (Async Reg) ..........629
16.5.23 LCD_SEGD6L - Segment Data Low Register 6 (Async Reg) ..........629
16.5.24 LCD_SEGD7L - Segment Data Low Register 7 (Async Reg) ..........630
16.5.25 LCD_SEGD4H - Segment Data High Register 4 (Async Reg) .........630
16.5.26 LCD_SEGD5H - Segment Data High Register 5 (Async Reg) .........631
16.5.27 LCD_SEGD6H - Segment Data High Register 6 (Async Reg) .........631
16.5.28 LCD_SEGD7H - Segment Data High Register 7 (Async Reg) .........632
16.5.29 LCD_FREEZE - Freeze Register ...................633
16.5.30 LCD_SYNCBUSY - Synchronization Busy Register .............634
16.5.31 LCD_FRAMERATE - Frame Rate ...................635
16.5.32 LCD_SEGEN2 - Segment Enable (32 to 39) ...............636
17. PCNT - Pulse Counter ..........................637
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17.1 Introduction .............................637
17.2 Features ..............................637
17.3 Functional Description .........................638
17.3.1 Pulse Counter Modes ........................638
17.3.2 Hysteresis ...........................645
17.3.3 Auxiliary Counter .........................646
17.3.4 Triggered Compare and Clear .....................647
17.3.5 Register Access..........................648
17.3.6 Clock Sources ..........................648
17.3.7 Input Filter ...........................648
17.3.8 Edge Polarity ..........................648
17.3.9 PRS and PCNTn_S0IN,PCNTn_S1IN Inputs ................649
17.3.10 Interrupts ...........................649
17.3.11 Cascading Pulse Counters......................651
17.4 Register Map.............................652
17.5 Register Description ..........................653
17.5.1 PCNTn_CTRL - Control Register (Async Reg) ...............653
17.5.2 PCNTn_CMD - Command Register (Async Reg) ..............657
17.5.3 PCNTn_STATUS - Status Register ...................657
17.5.4 PCNTn_CNT - Counter Value Register .................658
17.5.5 PCNTn_TOP - Top Value Register ...................658
17.5.6 PCNTn_TOPB - Top Value Buffer Register (Async Reg) ............659
17.5.7 PCNTn_IF - Interrupt Flag Register ...................659
17.5.8 PCNTn_IFS - Interrupt Flag Set Register .................660
17.5.9 PCNTn_IFC - Interrupt Flag Clear Register ................661
17.5.10 PCNTn_IEN - Interrupt Enable Register .................662
17.5.11 PCNTn_ROUTELOC0 - I/O Routing Location Register ............663
17.5.12 PCNTn_FREEZE - Freeze Register ..................664
17.5.13 PCNTn_SYNCBUSY - Synchronization Busy Register ............664
17.5.14 PCNTn_AUXCNT - Auxiliary Counter Value Register ............665
17.5.15 PCNTn_INPUT - PCNT Input Register .................666
17.5.16 PCNTn_OVSCFG - Oversampling Config Register (Async Reg) ........668
18. I2C - Inter-Integrated Circuit Interface.....................669
18.1 Introduction .............................669
18.2 Features ..............................669
18.3 Functional Description .........................670
18.3.1 I2C-Bus Overview .........................671
18.3.2 Enable and Reset .........................675
18.3.3 Safely Disabling and Changing Slave Configuration..............675
18.3.4 Clock Generation .........................675
18.3.5 Arbitration............................676
18.3.6 Buffers .............................676
18.3.7 Master Operation .........................678
18.3.8 Bus States ...........................686
18.3.9 Slave Operation .........................686
18.3.10 Transfer Automation ........................690
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18.3.11 Using 10-bit Addresses .......................691
18.3.12 Error Handling ..........................691
18.3.13 DMA Support ..........................693
18.3.14 Interrupts ...........................693
18.3.15 Wake-up ............................693
18.4 Register Map.............................694
18.5 Register Description ..........................695
18.5.1 I2Cn_CTRL - Control Register ....................695
18.5.2 I2Cn_CMD - Command Register ...................698
18.5.3 I2Cn_STATE - State Register .....................699
18.5.4 I2Cn_STATUS - Status Register ....................700
18.5.5 I2Cn_CLKDIV - Clock Division Register .................701
18.5.6 I2Cn_SADDR - Slave Address Register .................701
18.5.7 I2Cn_SADDRMASK - Slave Address Mask Register .............702
18.5.8 I2Cn_RXDATA - Receive Buffer Data Register (Actionable Reads) ........702
18.5.9 I2Cn_RXDOUBLE - Receive Buffer Double Data Register (Actionable Reads) ....703
18.5.10 I2Cn_RXDATAP - Receive Buffer Data Peek Register ............703
18.5.11 I2Cn_RXDOUBLEP - Receive Buffer Double Data Peek Register ........704
18.5.12 I2Cn_TXDATA - Transmit Buffer Data Register ..............704
18.5.13 I2Cn_TXDOUBLE - Transmit Buffer Double Data Register ..........705
18.5.14 I2Cn_IF - Interrupt Flag Register ...................706
18.5.15 I2Cn_IFS - Interrupt Flag Set Register .................708
18.5.16 I2Cn_IFC - Interrupt Flag Clear Register ................710
18.5.17 I2Cn_IEN - Interrupt Enable Register ..................712
18.5.18 I2Cn_ROUTEPEN - I/O Routing Pin Enable Register ............713
18.5.19 I2Cn_ROUTELOC0 - I/O Routing Location Register .............714
19. USART - Universal Synchronous Asynchronous Receiver/Transmitter ........715
19.1 Introduction .............................715
19.2 Features ..............................716
19.3 Functional Description .........................717
19.3.1 Modes of Operation ........................718
19.3.2 Asynchronous Operation.......................718
19.3.3 Synchronous Operation .......................735
19.3.4 Hardware Flow Control .......................742
19.3.5 Debug Halt ...........................742
19.3.6 PRS-triggered Transmissions .....................742
19.3.7 PRS RX Input ..........................742
19.3.8 PRS CLK Input ..........................743
19.3.9 DMA Support ..........................743
19.3.10 Timer .............................744
19.3.11 Interrupts ...........................749
19.3.12 IrDA Modulator/ Demodulator.....................750
19.4 Register Map.............................751
19.5 Register Description ..........................752
19.5.1 USARTn_CTRL - Control Register ...................752
19.5.2 USARTn_FRAME - USART Frame Format Register .............757
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19.5.3 USARTn_TRIGCTRL - USART Trigger Control Register ............759
19.5.4 USARTn_CMD - Command Register ..................761
19.5.5 USARTn_STATUS - USART Status Register ...............762
19.5.6 USARTn_CLKDIV - Clock Control Register ................763
19.5.7 USARTn_RXDATAX - RX Buffer Data Extended Register (Actionable Reads) ....764
19.5.8 USARTn_RXDATA - RX Buffer Data Register (Actionable Reads) ........764
19.5.9 USARTn_RXDOUBLEX - RX Buffer Double Data Extended Register (Actionable Reads) 765
19.5.10 USARTn_RXDOUBLE - RX FIFO Double Data Register (Actionable Reads) ....766
19.5.11 USARTn_RXDATAXP - RX Buffer Data Extended Peek Register ........766
19.5.12 USARTn_RXDOUBLEXP - RX Buffer Double Data Extended Peek Register ....767
19.5.13 USARTn_TXDATAX - TX Buffer Data Extended Register ...........768
19.5.14 USARTn_TXDATA - TX Buffer Data Register ...............769
19.5.15 USARTn_TXDOUBLEX - TX Buffer Double Data Extended Register .......770
19.5.16 USARTn_TXDOUBLE - TX Buffer Double Data Register ...........771
19.5.17 USARTn_IF - Interrupt Flag Register ..................772
19.5.18 USARTn_IFS - Interrupt Flag Set Register ................774
19.5.19 USARTn_IFC - Interrupt Flag Clear Register ...............776
19.5.20 USARTn_IEN - Interrupt Enable Register ................778
19.5.21 USARTn_IRCTRL - IrDA Control Register ................780
19.5.22 USARTn_INPUT - USART Input Register ................782
19.5.23 USARTn_I2SCTRL - I2S Control Register ................784
19.5.24 USARTn_TIMING - Timing Register ..................786
19.5.25 USARTn_CTRLX - Control Register Extended ..............788
19.5.26 USARTn_TIMECMP0 - Used to Generate Interrupts and Various Delays ......789
19.5.27 USARTn_TIMECMP1 - Used to Generate Interrupts and Various Delays ......791
19.5.28 USARTn_TIMECMP2 - Used to Generate Interrupts and Various Delays ......793
19.5.29 USARTn_ROUTEPEN - I/O Routing Pin Enable Register ...........795
19.5.30 USARTn_ROUTELOC0 - I/O Routing Location Register ...........797
19.5.31 USARTn_ROUTELOC1 - I/O Routing Location Register ...........799
20. UART - Universal Asynchronous Receiver/ Transmitter ..............800
20.1 Introduction .............................800
20.2 Features ..............................801
20.3 Functional Description .........................801
20.4 Register Map.............................801
20.5 Register Description ..........................801
21. LEUART - Low Energy Universal Asynchronous Receiver/Transmitter ........802
21.1 Introduction .............................802
21.2 Features ..............................803
21.3 Functional Description .........................804
21.3.1 Frame Format ..........................805
21.3.2 Clock Source ..........................805
21.3.3 Clock Generation .........................806
21.3.4 Data Transmission .........................806
21.3.5 Data Reception ..........................808
21.3.6 Loopback ............................811
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21.3.7 Half Duplex Communication .....................811
21.3.8 Transmission Delay ........................812
21.3.9 PRS RX Input ..........................812
21.3.10 DMA Support ..........................813
21.3.11 Pulse Generator/ Pulse Extender ...................813
21.3.12 Register Access .........................814
21.4 Register Map.............................814
21.5 Register Description ..........................815
21.5.1 LEUARTn_CTRL - Control Register (Async Reg) ..............815
21.5.2 LEUARTn_CMD - Command Register (Async Reg) .............818
21.5.3 LEUARTn_STATUS - Status Register ..................819
21.5.4 LEUARTn_CLKDIV - Clock Control Register (Async Reg) ...........820
21.5.5 LEUARTn_STARTFRAME - Start Frame Register (Async Reg) .........820
21.5.6 LEUARTn_SIGFRAME - Signal Frame Register (Async Reg) ..........821
21.5.7 LEUARTn_RXDATAX - Receive Buffer Data Extended Register (Actionable Reads) ..821
21.5.8 LEUARTn_RXDATA - Receive Buffer Data Register (Actionable Reads) ......822
21.5.9 LEUARTn_RXDATAXP - Receive Buffer Data Extended Peek Register ......822
21.5.10 LEUARTn_TXDATAX - Transmit Buffer Data Extended Register (Async Reg) ....823
21.5.11 LEUARTn_TXDATA - Transmit Buffer Data Register (Async Reg) ........824
21.5.12 LEUARTn_IF - Interrupt Flag Register .................825
21.5.13 LEUARTn_IFS - Interrupt Flag Set Register ...............826
21.5.14 LEUARTn_IFC - Interrupt Flag Clear Register ...............827
21.5.15 LEUARTn_IEN - Interrupt Enable Register ................828
21.5.16 LEUARTn_PULSECTRL - Pulse Control Register (Async Reg) .........829
21.5.17 LEUARTn_FREEZE - Freeze Register .................830
21.5.18 LEUARTn_SYNCBUSY - Synchronization Busy Register ...........831
21.5.19 LEUARTn_ROUTEPEN - I/O Routing Pin Enable Register ..........832
21.5.20 LEUARTn_ROUTELOC0 - I/O Routing Location Register ...........833
21.5.21 LEUARTn_INPUT - LEUART Input Register ...............834
22. TIMER/WTIMER - Timer/Counter .......................836
22.1 Introduction .............................836
22.2 Features ..............................837
22.3 Functional Description .........................838
22.3.1 Counter Modes ..........................838
22.3.2 Compare/Capture Channels .....................844
22.3.3 Dead-Time Insertion Unit.......................854
22.3.4 Debug Mode ...........................858
22.3.5 Interrupts, DMA and PRS Output ....................858
22.3.6 GPIO Input/Output .........................858
22.4 Register Map.............................859
22.5 Register Description ..........................860
22.5.1 TIMERn_CTRL - Control Register ...................860
22.5.2 TIMERn_CMD - Command Register ..................863
22.5.3 TIMERn_STATUS - Status Register ..................864
22.5.4 TIMERn_IF - Interrupt Flag Register ..................867
22.5.5 TIMERn_IFS - Interrupt Flag Set Register ................868
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22.5.6 TIMERn_IFC - Interrupt Flag Clear Register ................869
22.5.7 TIMERn_IEN - Interrupt Enable Register .................871
22.5.8 TIMERn_TOP - Counter Top Value Register ................872
22.5.9 TIMERn_TOPB - Counter Top Value Buffer Register .............872
22.5.10 TIMERn_CNT - Counter Value Register .................873
22.5.11 TIMERn_LOCK - TIMER Configuration Lock Register ............873
22.5.12 TIMERn_ROUTEPEN - I/O Routing Pin Enable Register ...........874
22.5.13 TIMERn_ROUTELOC0 - I/O Routing Location Register ...........875
22.5.14 TIMERn_ROUTELOC2 - I/O Routing Location Register ...........877
22.5.15 TIMERn_CCx_CTRL - CC Channel Control Register ............879
22.5.16 TIMERn_CCx_CCV - CC Channel Value Register (Actionable Reads) ......882
22.5.17 TIMERn_CCx_CCVP - CC Channel Value Peek Register ...........882
22.5.18 TIMERn_CCx_CCVB - CC Channel Buffer Register .............883
22.5.19 TIMERn_DTCTRL - DTI Control Register ................884
22.5.20 TIMERn_DTTIME - DTI Time Control Register ..............886
22.5.21 TIMERn_DTFC - DTI Fault Configuration Register .............888
22.5.22 TIMERn_DTOGEN - DTI Output Generation Enable Register .........891
22.5.23 TIMERn_DTFAULT - DTI Fault Register .................892
22.5.24 TIMERn_DTFAULTC - DTI Fault Clear Register ..............893
22.5.25 TIMERn_DTLOCK - DTI Configuration Lock Register ............894
23. LETIMER - Low Energy Timer ........................895
23.1 Introduction .............................895
23.2 Features ..............................895
23.3 Functional Description .........................896
23.3.1 Timer .............................896
23.3.2 Compare Registers ........................896
23.3.3 Top Value ............................897
23.3.4 Underflow Output Action .......................903
23.3.5 PRS Output ...........................905
23.3.6 Examples ............................905
23.3.7 Register Access..........................908
23.4 Register Map.............................909
23.5 Register Description ..........................910
23.5.1 LETIMERn_CTRL - Control Register (Async Reg) ..............910
23.5.2 LETIMERn_CMD - Command Register .................912
23.5.3 LETIMERn_STATUS - Status Register ..................912
23.5.4 LETIMERn_CNT - Counter Value Register ................913
23.5.5 LETIMERn_COMP0 - Compare Value Register 0 (Async Reg) .........913
23.5.6 LETIMERn_COMP1 - Compare Value Register 1 (Async Reg) .........914
23.5.7 LETIMERn_REP0 - Repeat Counter Register 0 (Async Reg) ..........914
23.5.8 LETIMERn_REP1 - Repeat Counter Register 1 (Async Reg) ..........915
23.5.9 LETIMERn_IF - Interrupt Flag Register .................915
23.5.10 LETIMERn_IFS - Interrupt Flag Set Register ...............916
23.5.11 LETIMERn_IFC - Interrupt Flag Clear Register ..............917
23.5.12 LETIMERn_IEN - Interrupt Enable Register ...............918
23.5.13 LETIMERn_SYNCBUSY - Synchronization Busy Register ..........918
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23.5.14 LETIMERn_ROUTEPEN - I/O Routing Pin Enable Register ..........919
23.5.15 LETIMERn_ROUTELOC0 - I/O Routing Location Register ..........920
23.5.16 LETIMERn_PRSSEL - PRS Input Select Register .............921
24. CRYOTIMER - Ultra Low Energy Timer/Counter .................925
24.1 Introduction .............................925
24.2 Features ..............................925
24.3 Functional Description .........................925
24.3.1 Block Diagram ..........................926
24.3.2 Operation ............................927
24.3.3 Debug Mode ...........................927
24.3.4 Energy Mode Availability .......................927
24.4 Register Map.............................928
24.5 Register Description ..........................929
24.5.1 CRYOTIMER_CTRL - Control Register .................929
24.5.2 CRYOTIMER_PERIODSEL - Interrupt Duration ..............931
24.5.3 CRYOTIMER_CNT - Counter Value ..................932
24.5.4 CRYOTIMER_EM4WUEN - Wake Up Enable ...............932
24.5.5 CRYOTIMER_IF - Interrupt Flag Register .................933
24.5.6 CRYOTIMER_IFS - Interrupt Flag Set Register ...............933
24.5.7 CRYOTIMER_IFC - Interrupt Flag Clear Register ..............934
24.5.8 CRYOTIMER_IEN - Interrupt Enable Register ...............934
25. VDAC - Digital to Analog Converter .....................935
25.1 Introduction .............................935
25.2 Features ..............................936
25.3 Functional Description .........................936
25.3.1 Power Supply ..........................937
25.3.2 I/O Pin Considerations .......................937
25.3.3 Enabling and Disabling a Channel ...................937
25.3.4 Conversions ...........................938
25.3.5 Reference Selection ........................938
25.3.6 Warmup Time and Initial Conversion ...................939
25.3.7 Analog Output ..........................939
25.3.8 Output Mode ...........................939
25.3.9 Async Mode ...........................940
25.3.10 Refresh Timer ..........................940
25.3.11 Clock Prescaling .........................940
25.3.12 High Speed ...........................940
25.3.13 Sine Generation Mode .......................941
25.3.14 Interrupt Flags ..........................941
25.3.15 PRS Outputs ..........................942
25.3.16 DMA Request ..........................942
25.3.17 LESENSE Trigger Mode ......................942
25.3.18 Opamps ............................942
25.3.19 Calibration ...........................942
25.3.20 Warmup Mode ..........................943
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