Texas Instruments TMS320DM642 EVM OSD FPGA User guide

Brand: Texas Instruments

Model: TMS320DM642 EVM OSD FPGA

Category: Power generators

Type: User guide

TMS320DM642 EVM OSD FPGA

User’s Guide

Literature Number: SPRU295

June 2003

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Preface

Read This First

About This Manual

The document gives explains how to use the TMS320DM642 evaluation mod-

ule with the on-screen display of the field−programmable gate array.

Notational Conventions

This document uses the following conventions.

- Program listings, program examples, and interactive displays are shown

in a special typeface similar to a typewriter’s. Examples use a bold

version of the special typeface for emphasis; interactive displays use a

bold version of the special typeface to distinguish commands that you

enter from items that the system displays (such as prompts, command

output, error messages, etc.).

Here is a sample program listing:

0011 0005 0001 .field 1, 2

0012 0005 0003 .field 3, 4

0013 0005 0006 .field 6, 3

0014 0006 .even

Here is an example of a system prompt and a command that you might

enter:

C: csr −a /user/ti/simuboard/utilities

- In syntax descriptions, the instruction, command, or directive is in a bold

typeface font and parameters are in an italic typeface. Portions of a syntax

that are in bold should be entered as shown; portions of a syntax that are

in italics describe the type of information that should be entered. Here is

an example of a directive syntax:

.asect ”section name”, address

.asect is the directive. This directive has two parameters, indicated by sec-

tion name and address. When you use .asect, the first parameter must be

an actual section name, enclosed in double quotes; the second parameter

must be an address.

Related Documentation From Texas Instruments

- Square brackets ( [ and ] ) identify an optional parameter. If you use an

optional parameter, you specify the information within the brackets; you

do not enter the brackets themselves. Here is an example of an instruction

that has an optional parameter:

LALK 16−bit constant [, shift]

The LALK instruction has two parameters. The first parameter, 16-bit con-

stant, is required. The second parameter, shift, is optional. As this syntax

shows, if you use the optional second parameter, you must precede it with

a comma.

Square brackets are also used as part of the pathname specification for

VMS pathnames; in this case, the brackets are actually part of the path-

name (they are not optional).

- Braces ( { and } ) indicate a list. The symbol | (read as or) separates items

within the list. Here’s an example of a list:

{ * | *+ | *− }

This provides three choices: *, *+, or *−.

Unless the list is enclosed in square brackets, you must choose one item

from the list.

- Some directives can have a varying number of parameters. For example,

the .byte directive can have up to 100 parameters. The syntax for this di-

rective is:

.byte value

[, ... , value

]

This syntax shows that .byte must have at least one value parameter, but

you have the option of supplying additional value parameters, separated

by commas.

Related Documentation From Texas Instruments

The following books describe the TMS320VC5509 and related support tools.

To obtain a copy of any of these TI documents, go to the TI website:

www.ti.com.

TMS320DM642 Video/Imaging Fixed-Point Digital Signal Processor Data

Manual (SPRS200) provides timing and electrical specifications for the

TMS320DM642.

Related Documentation From Spectrum Digital

TMS320C6201/C6701 Peripherals Reference Guide (literature number

SPRU190) describes common peripherals available on the

TMS320C6201 and TMS320C6701 digital signal processors. This book

includes information on the internal data and program memories, the

external memory interface (EMIF), the host port interface (HPI), multi-

channel buffered serial ports (McBSPs), direct memory access (DMA),

enhanced DMA (EDMA), expansion bus, clocking and phase-locked

loop (PLL), and the power-down modes.

Related Documentation From Spectrum Digital

DM642 EVM Technical Reference (Spectrum Digital) describes the evalua-

tion module for the Texas Instruments TMS320DM642.

Trademarks

Trademarks are the property of their respective owners.

Trademarks

This page is intentionally left blank.

Contents

7TMS320DM642 EVM OSD FPGA User’s GuideSPRU295

Contents

1 Features 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1 OSD FPGA System Block Diagram 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 OSD FPGA Signals 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 Architecture 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 Video Interface (IF) 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 Address Decoder 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3 Registers 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4 On-Screen Display (OSD) Data First-In, First-Out (FIFO) 19. . . . . . . . . . . . . . . . . . . . . . . . .

2.5 Direct Memory Access (DMA) Event Generator 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6 OSD Control Logic 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.7 OSD Unpack Module 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.8 OSD Color Look-Up Table(CLUT) 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.9 On-Screen Display (OSD) Multiplexer (MUX) 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.10 Double Data Rate (DDR) Module 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11 Phase-Locked Loop (PLL) Serial Interface (IF) 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3 EMIF Configuration 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1 Registers Read/Write 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2 DMA Transfers 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4 Display Event Generation and Processing 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1 Endian Support and FIFO Unpacking 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2 Address Map 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5 Asynchronous Register Definitions 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.1 OSD Control Register 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.2 DMA Threshold LSB Register 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.3 DMA Threshold MSB Register 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.4 Interrupt Status Register 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.5 Interrupt Enable Register 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.6 GPIO Direction Register 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.7 GPIO Register 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.8 LED Register 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.9 Flash Page Register 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.10 FPGA Version 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6 Synchronous Register Definitions 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.1 Test Register 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contents

8 TMS320DM642 EVM OSD FPGA User’s Guide SPRU295

6.2 PLL Data Register 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.3 OSD XSTART Register 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.4 OSD YSTART Register 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.5 OSD XSTOP Register 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.6 OSD YSTOP Register 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.7 Events-Per-Field Register 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7 Different Video/OSD Modes of Operation 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.1 Timing Constraints 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.2 FPGA Configuration File Generation 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figures

9TMS320DM642 EVM OSD FPGA User’s GuideSPRU295

Figures

1. OSD FPGA System Block Diagram 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2. OSD FPGA Signals 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3. OSD FPGA Architecture 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4. Video Syncs 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5. OSD State Machine Diagram 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6. Logic Diagram for OSD CLUT Module 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7. Video 8-bit, Single-edge Output 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8. Video 16-bit, Double-clock-edge Output 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9. DSP Asynchronous Write 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10. DSP Asynchronous Read 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11. DSP Synchronous Read 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12. DSP Synchronous Write 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13. OSD Control Register 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14. DMA Threshold LSB Register 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

15. DMA Threshold MSB Register 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

16. Interrupt Status Register 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

17. Interrupt Enable Register 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

18. GPIO Direction Register 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

19. GPIO Register 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

20. LED Register 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

21. Flash Page Register 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

22. FPGA Version Register 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

23. Test Register 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

24. PLL Data Register 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

25. OSD XSTART Register 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

26. OSD YSTART Register 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

27. OSD XSTOP Register 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

28. OSD YSTOP Register 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

29. Events-Per-Field Register 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Tables

10 TMS320DM642 EVM OSD FPGA User’s Guide SPRU295

Tables

1. Signal Definitions 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2. OSD State Machine State Deviations 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3. Memory Map of OSD FPGA for CE1 Memory Space 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4. Memory Map of OSD FPGA for CE3 Memory Space 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TMS320DM642 OSD FPGA EVM

This document describes the operation of the on-screen display (OSD) field

programmable gate array (FPGA) used on the TMS320DM642 evaluation

module (EVM). The FPGA is a Xilinx XC2S300E−6PQ208C.

1 Features

The OSD FPGA has the following features:

- Controls eight light-emitting diodes (LEDs) accessible by the DM642 ex-

ternal memory interface (EMIF) through a register

- Controls eight general-purpose input/output (GPIO) bits through registers

accessible by the DM642 EMIF

- Generate control signals (DIR and OEz) for EMIF buffers

- Provides serial control interface to PLL1708.

- Generates three page bits for the FLASH

- Implements an interrupt control logic that monitors interrupt signals from

the dual UART and video decoder and generates an edge-triggered inter-

rupt to the DM642

- Provides an interface between the DM642 video port and the SAA7105

video encoder. This interface can operate in the following modes:

J Transparent mode where the 8-bit video output from the DM642 video

port is passed directly to the SAA7105 video encoder.

J Performs 2:1 multiplex operation to support SVGA and HD. The

DM642 video port outputs 16-bit video data on the rising edge of the

clock to the OSD FPGA. The OSD FPGA converts this to dual clock

edge 8-bit video data where the upper 8 bits are clocked out on the

rising edge of the clock and the lower 8 bits on the falling edge.

J One-bit alpha blending with 7-bit color look-up table (CLUT) for 8-bit

video output from the DM642. The alpha blended video data is then

passed on to the SAA7105 video encoder.

J One-bit Alpha blending with 7-bit CLUT for 16-bit video output from the

DM642 to support HD mode of operation. The alpha blended video

Features

TMS320DM642 OSD FPGA EVM12 SPRU295

data is converted to dual clock edge 8-bit data and passed on to the

SAA7105 video encoder.

1.1 OSD FPGA System Block Diagram

Figure 1. OSD FPGA System Block Diagram

SOE3

CE[3:1]z

ECLKOUT2

ARE

AWE

AOE

EA[22:3]

ED[63:0]

Buffer

XCVR

EMIF

RESET

[22, 7:3]

[31:0]

DC_EMIF_OE

DC_EMIF_DIR

VP2CTL[2:0]

VP2CLK0

VP2CLK1

VP2D[19:0]

Video

Port 2

EXTINT7

EXTINT6

GPO[0]

GPO[2]/CLKOUT6

GPO[1]/CLKOUT4

To LED

Decoder

(SAA7115)

RTS0_A

Decoder

(SAA7115)

RTS0_B

DM642

INT1

FPGA_INIT/INT0

FPGA_PROG

FPGA_DIN

FPGA_CCLK

FPGA_DONE

OSD FPGA

FLASH_PAGE[2:0]

LED[7:0]

GPIO[7:0]

UART_INTB, UART_INTA

UART_RXRDYB, UART_RXRDYA

UART_TXRDYB, UART_TXRDYA

Dual UART

(TL16C752B)

PLL_MS

PLL_MD

PLL_MC

PLL1708

Buffer

(LVC1G126)

Buffer

VSYNC

HSYNC

RGB Out

(DB−15)

DENC_HSYNC

DENC_VSYNC

DENC_FIELD

DENC_BLANK

PIXCLKI

PIXCLKO

DENCDATA[11:0]

HSVGC

VSVGC

FSVGC

CBOz

HSM_CSYNC

VSM

TVD

PIXCLKI

PIXCLKO

PD[11:0]

Encoder

(SAA7105)

R/G/B

Composite Out/

HD Out

(3 RCA Jacks)

S−Video Out

94−Pin Mini DIN)

TVDETECT

OSD FPGA Signals

13TMS320DM642 OSD FPGA EVMSPRU295

1.2 OSD FPGA Signals

Figure 2 shows all the signals going to the OSD FPGA and Table 1 describes

the signals.

Figure 2. OSD FPGA Signals

RESET

FPGA_INIT_EXTINT6*

EXTINT7

CE1

CE2

CE3

ECLKOUT2

ARE

AWE

AOE

SOE3

EA[22, 7:3]

ED[31:0]

VP2CLK0

VP2CLK1

VP2CTL0

VP2CTL1

VP2CTL2

VP2D[19:0]

PLL_MS

PLL_MD

PLL_MC

FLASH_PAGE[2:0]

UART_INTB, UART_INTA

UART_RXRDYB, UART_RXRDYA

UART_TXRDYB, UART_TXRDYA

LED[7:0]

GPIO[7:0]

DC_EMIF_OE

DC_EMIF_DIR

RTS0_A

RTS0_B

DENC_HSYNC

DENC_VSYNC

DENC_FIELD

TVDETECT

PIXCLKI

PIXCLKO

DENCDATA[11:0]

FPGA_INIT_EXTINT6

†

FPGA_PROG

FPGA_DIN

FPGA_CCLK

FPGA_DONE

OSD

FPGA

DM642 EMIF

Signals

DM642

Video Port 2

Signals

PLL1708

Serial

Interface

Video

Decoder

Signals

Video

Encoder

Signals

FPGA

Configuration

Signals

†

FPGA_INIT_EXTINT6 is used as the FPGA INIT signal for configuration when FPGA_PROG is pulled low. When FPGA_PROG

is high, this pin is used as EXTINT6 to the DSP.

Table 1. Signal Definitions

Signal Type Description

Miscellaneous Signals

RESET I Asynchronous system reset

FLASH_PAGE[2:0] O Page bits for flash on EVM

LED[7:0] O LED outputs which drive LEDs on EVM

OSD FPGA Signals

TMS320DM642 OSD FPGA EVM14 SPRU295

Table 1. Signal Definitions (Continued)

Signal DescriptionType

GPIO[7:0] I/O General purpose inputs/outputs which go to the daughtercard connectors on

EVM

DC_EMIF_OE O Output enable for transceiver on EMIF data bus

DC_EMIF_DIR O Direction control for transceiver on EMIF data bus

DM642 Interrupts

EXTINT6 O Edge-driven external interrupt input to the DM642.

EXTINT7 O Edge-driven external interrupt input to the DM642.

DM642 EMIF Signals

CE1

I EMIF memory space 1 enable. This memory space is used for all asynchronous

interfaces on the EVM. This includes the flash, Dual UART, and the OSD FPGA

registers. This bit is also used to generate the DC_EMIF_OE signal.

The CE1 memory space is configured for 8-bit wide asynchronous memory

interface.

CE2 I EMIF memory space 2 enable. This bit is also used to generate the

DC_EMIF_OE

signal.

The CE2 memory space is reserved for the daughtercard interface and can be

configured anyway the daughtercard needs.

CE3

I EMIF memory space 3 enable. This memory space is used for synchronous

assesses to the OSD FPGA and daughtercard interface. This bit is also used to

generate the DC_EMIF_OE signal.

The CE3 memory space is configured for 32-bit wide synchronous memory

interface.

ECLKOUT2 I EMIF output clock 2. Used for synchronous interface on memory space 3.

ARE

I EMIF asynchronous memory read enable/programmable synchronous

interface address strobe or read enable

DM642 EMIF Signals

AWE

I EMIF asynchronous memory write enable/programmable synchronous

interface write enable

AOE

I EMIF asynchronous memory output enable/programmable synchronous

interface output enable

SOE3

I EMIF synchronous memory output enable for memory space CE3

EA[22, 7:3] I EMIF address bus

OSD FPGA Signals

15TMS320DM642 OSD FPGA EVMSPRU295

Table 1. Signal Definitions (Continued)

Signal DescriptionType

ED[31:0] I/O EMIF data bus

DM642 Video Port 2 Signals

VP2CLK0 O Video port 2 clock 0. Input to DM642 video port.

VP2CLK1 I Video port 2 clock 1. Output from DM642 video port.

VP2CTL0 I Video port 2 control 0. Is used to provide HSYNC to OSD FPGA.

VP2CTL1 I Video port 2 control 1. Is used to provide VSYNC to OSD FPGA.

VP2CTL2 I Video port 2 control 2. Is used to provide FIELD to OSD FPGA.

VP2D[19:0] I Video port 2 data bus. Output from DM642 to OSD FPGA.

Video Encoder Signals

TVDETECT I Interrupt if TV is detected at DAC output of SAA7105

PIXCLKI O Pixel clock output from OSD FPGA to SAA7105

PIXCLKO I Pixel clock input to OSD FPGA from SAA7105

DENCDATA[11:0] O Video data

Video Decoder Signals

RTS0_A I Real time status or sync information from SAA7115

RTS0_B I Real time status or sync information from SAA7115

PLL1708 Serial Interface

PLL_MS O Chip select for serial control

PLL_MD O Data for serial control

PLL_MC O Bit clock for serial control

Dual UART Interface

UART_INTB,

UART_INTA

I Interrupts from dual UART chip

UART_RXRDYB

UART_RXRDYA

I Receive ready from dual UART chip

UART_TXRDYB

UART_TXRDYA

I Transmit ready from dual UART chip

OSD FPGA Signals

TMS320DM642 OSD FPGA EVM16 SPRU295

Table 1. Signal Definitions (Continued)

Signal DescriptionType

FPGA Configuration Signals

FPGA_INIT O Delay configuration, indicate configuration clearing or error

FPGA_PROG I Asynchronous reset to configuration logic

FPGA_DIN I Serial configuration data input

FPGA_CCLK I Configuration clock

FPGA_DONE

O Configuration status and start-up control

Architecture

17TMS320DM642 OSD FPGA EVMSPRU295

2 Architecture

Figure 3. OSD FPGA Architecture

OSD

Unpack

Module

8/16

EINT7DataCTL, Addr

Registers

Logic

Control

OSD

8/32

OSD

CLUT

8/16

PLL

Serial

OSD Multiplexer

DDR

Module

To SAA7105 EncoderTo PLL1708

CTL Addr Data Buffer

CTL

EINT7

Address Decoder

From DM642 EMIF

EINT6

DMA Event

Generator

From DM642 Video Port 2

Misc I/O: GPIOs, LEDs, Flash Pages, UART

Interrupts, Interrupts from Decoder

Video IF

Data CTL

OSD FPGA

Alpha Data

1/2

The OSD FPGA interfaces to the DM642 EMIF and video port 2. The FPGA

also interfaces to the video encoder, clock PLL, dual UART, GPIOs, and LEDs.

The different modules in the OSD FPGA and their functionality are described

below.

Architecture

TMS320DM642 OSD FPGA EVM18 SPRU295

2.1 Video Interface (IF)

The Video IF interfaces to the DM642 video port 2. The video port can be con-

figured as either an 8-bit or 16-bit display interface. The Video IF module regis-

ters all the data and control signals received from the video port. The Video IF

module provides data to the OSD MUX module and the control signals to the

OSD Control Logic as well as to the SAA7105 encoder external to the FPGA.

The design in the FPGA adds a 10-clock latency to the video data. The control

signals are also delayed by 10 clock cycles to match the data delay. See

Figure 4.

Figure 4. Video Syncs

VP2CLK1

VP2CTL1(VSYNC)

VP2CTL0(HSYNC)

DENC_VSYNC

DENC_HSYNC

10 clk cycles

10 clk cycles 10 clk cycles

10 clk cycles

2.2 Address Decoder

The address decoder interfaces to the DM642 EMIF interface. The address

decoder module registers all the incoming data and address signals and does

first level of address decoding. It divides the CE1 address space into space

for the Flash, space for dual UART, and space for asynchronous registers in-

side the OSD FPGA. It also divides the CE3 address space into space for ex-

ternal synchronous logic, space for FIFOs inside the FPGA, and space for syn-

chronous registers inside the OSD FPGA.

2.3 Registers

The registers section actually includes two register modules, one for synchro-

nous registers and the other for asynchronous registers.

The synchronous registers can be 32 bits wide. Though the synchronous reg-

isters module has logic for both reads and writes of these registers, the read

back of these registers is reliable only up to ECLKOUT2 clock speed of

70 MHz. The synchronous registers include a test register and a clock PLL

data register.

Architecture

19TMS320DM642 OSD FPGA EVMSPRU295

The asynchronous registers are all 8 bits wide. The asynchronous registers

module also includes interrupt control logic and logic to control both LEDs and

GPIOs.

2.4 On-Screen Display (OSD) Data First-In, First-Out (FIFO)

The OSD data FIFO is 256 words deep and 32 bits wide. The address decoder

module controls the write enable and writes data to the OSD data FIFO. The

unpack module controls the read enable and reads the FIFO data output. The

OSD data FIFO can be written to by writing to the address 0xB000 0040 in the

CE3 address space.

2.5 Direct Memory Access (DMA) Event Generator

The DMA event generator module monitors the OSD data FIFO usage and the

number of events generated per field. It generates a DMA event whenever the

FIFO has space for a DMA equal to the DMA threshold size, the number of

events generated for the current field has not exceeded the number of events

specified in Events Per Field Register, and event generation has been enabled

by the OSD control logic. Once a DMA event is generated, the DMA event gen-

erator stops event generation until the DMA requested is completed. The DMA

event generator counts the writes made to the OSD data FIFO and when the

counter reaches the DMA threshold size, event generation is reenabled. See

Section 4 for further explanation.

2.6 OSD Control Logic

The OSD control logic controls the behavior of the OSD functionality in the

OSD FPGA. It controls the OSD unpack module, the DMA event generator,

and the OSD MUX. The OSD control logic monitors the video control signals

VSYNC and AVID to control the different OSD modules. Provided the OSD

data FIFO is not empty, the OSD data is multiplexed within the OSD window

specified by the OSD XSTART, OSD YSTART, OSD XSTOP and OSD YSTOP

registers. Within the OSD window, the OSD control logic enables reading of

OSD data FIFO, unpacking of OSD data, and multiplexing of video and OSD

data.

The OSD control logic provides a control signal to control the OSD MUX, un-

pack signal to the OSD unpack module, and event enable signal to the DMA

event generator.

Architecture

TMS320DM642 OSD FPGA EVM20 SPRU295

Figure 5. OSD State Machine Diagram

Idle

Initialize

Active

Video

Blanking

OSD_EN=1

OSD_EN=0

OSD_EN=1

AVID=0

VSYNC=1

OSD_EN=1

AVID=0

OSD_EN=1

AVID=1

OSD_EN=0

Table 2. OSD State Machine State Deviations

State Description

Idle The state machine idles in this state till OSD_EN goes active. The video data is passed through

the FPGA when the state machine is in the Idle state.

Initialize Whenever OSD_EN goes active, this state is reached. In this state, the state machine enables

DMA events. The state machine waits in this state till a blanking period is detected.

Blanking The state machine maintains the blanking period as long as AVID is zero. During this state, the

FPGA passes the video through without any modifications. The first time this state is reached

field detection is enabled. Once Field detection completes, the OSD functionality is enabled on

Field 1 to ensure synchronization of OSD data

Active Video

The state machine maintains the active video period as long as AVID is one. If OSD functionality

has been enabled, the state machine signals the OSD MUX module to multiplex the OSD data

with video data based on the alpha information received in the OSD Data FIFO within the OSD

window specified by the OSD XSTART, OSD YSTART, OSD XSTOP and OSD YSTOP provided

the FIFO is not empty. If the FIFO is not empty, unpack signal to the OSD Unpack module is as-

serted.

2.7 OSD Unpack Module

The OSD Unpack Module reads data from the OSD Data FIFO and unpacks

it into 8-bit data. Whenever the video port bus width is 8 bits wide, the OSD

Unpack Module unpacks the data into 8-bit data every other clock cycle.

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Texas Instruments TMS320DM642 EVM OSD FPGA User guide

Brand: Texas Instruments

Model: TMS320DM642 EVM OSD FPGA

Category: Power generators

Type: User guide

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Texas Instruments TMS320DM642 EVM OSD FPGA User guide

Texas Instruments TMS320DM642 EVM OSD FPGA User guide

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