Microsemi IGLOO2 FPGA DSP FIR Filter User manual

Brand: Microsemi

Model: IGLOO2 FPGA DSP FIR Filter

Type: User manual

This manual is also suitable for

SmartFusion2 MSS

UG0451

User Guide

SmartFusion2 and IGLOO2 Programming

50200451. 7.0. 3/18

Microsemi Corporate Headquarters

One Enterprise, Aliso Viejo,

CA 92656 USA

Within the USA: +1 (800) 713-4113

Outside the USA: +1 (949) 380-6100

Fax: +1 (949) 215-4996

Email: [email protected]

www.microsemi.com

rights reserved. Microsemi and the

Microsemi logo are trademarks of

Microsemi Corporation. All other

trademarks and service marks are the

property of their respective owners.

Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or the suitability of

its products and services for any particular purpose, nor does Microsemi assume any liability whatsoever arising out of the

application or use of any product or circuit. The products sold hereunder and any other products sold by Microsemi have

been subject to limited testing and should not be used in conjunction with mission-critical equipment or applications. Any

performance specifications are believed to be reliable but are not verified, and Buyer must conduct and complete all

performance and other testing of the products, alone and together with, or installed in, any end-products. Buyer shall not

rely on any data and performance specifications or parameters provided by Microsemi. It is the Buyer's responsibility to

independently determine suitability of any products and to test and verify the same. The information provided by Microsemi

hereunder is provided “as is, where is” and with all faults, and the entire risk associated with such information is entirely

with the Buyer. Microsemi does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other IP

rights, whether with regard to such information itself or anything described by such information. Information provided in this

document is proprietary to Microsemi, and Microsemi reserves the right to make any changes to the information in this

document or to any products and services at any time without notice.

About Microsemi

Microsemi Corporation (Nasdaq: MSCC) offers a comprehensive portfolio of semiconductor and system solutions for

aerospace & defense, communications, data center and industrial markets. Products include high-performance and

radiation-hardened analog mixed-signal integrated circuits, FPGAs, SoCs and ASICs; power management products;

timing and synchronization devices and precise time solutions, setting the world's standard for time; voice processing

devices; RF solutions; discrete components; enterprise storage and communication solutions, security technologies and

scalable anti-tamper products; Ethernet solutions; Power-over-Ethernet ICs and midspans; as well as custom design

capabilities and services. Microsemi is headquartered in Aliso Viejo, California, and has approximately 4,800 employees

globally. Learn more at

www.microsemi.com.

UG0451 User Guide Revision 7.0 iii

Contents

1 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1 Revision 7.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.2 Revision 6.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.3 Revision 5.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.4 Revision 4.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.5 Revision 3.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.6 Revision 2.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.7 Revision 1.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.8 Revision 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.9 SmartFusion2 List of Changes Table for Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2 Programming Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2.1 Programming Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2 Programming Bitstream Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.2.1 Programming Bitstream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.3 Programming Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3 JTAG Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.1 Programming Interface Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.1.1 JTAG Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.1.2 Design Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.2 Programming Using an External Programmer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.2.1 Power Supply Requirements for Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.3 Programming Using an External Microprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4 SPI Slave Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.1 Programming Interface Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.1.1 Design Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5 Auto Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.1 Programming Interface Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.1.1 Design Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.1.2 Auto Programming of M2S/M2GL050 Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6 MSS ISP (SmartFusion2 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

6.1 Design Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7 In-Application Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7.1 Design Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.1.1 Authenticate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.1.2 Verify . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.1.3 Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

8 Auto Update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

8.1 Configuring the Device for Auto Update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

9 Programming Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

9.1 Programming Recovery Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

9.2 SPI Flash Configuration and Image Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

UG0451 User Guide Revision 7.0 iv

9.2.1 MSS/HPMS SPI_0 Port Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

10 Production Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

11 State of SmartFusion2 and IGLOO2 Components During Programming . . . . . . . . 42

11.1 Use of Flash Freeze Mechanism in Device Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

UG0451 User Guide Revision 7.0 v

Figures

Figure 1 Libero SoC Programming Bitstream Generation Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 2 JTAG Signals Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 3 JTAG Programming Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 4 Programming Microsemi Devices in a JTAG Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 5 JTAG Programming using External Programmer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 6 JTAG Programming of a SmartFusion2 Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 7 Programming Using an External Microprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 8 SPI Slave Programming by External Microprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 9 SPI Slave Programming by External Programmer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 10 SmartFusion2/IGLOO2 MSS/HPMS SPI_0 Port Configured for Auto Programming (Except 050

Device) 22

Figure 11 Timing Relationship of Reset and FLASH_GOLDEN_N Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 12 Auto Programming Scheme for M2S/M2GL050 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 13 MSS ISP Update Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 14 MSS ISP Update Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 15 IGLOO2 In-Application Programming Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 16 SmartFusion2 In-Application Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 17 IAP Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 18 Auto Update Programming Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 19 Enabling Auto Update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 20 Enabling Programming Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 21 Programming Recovery Configuration for SmartFusion2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 22 I/O States During JTAG Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 23 Setting I/O States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

UG0451 User Guide Revision 7.0 vi

Tables

Table 1 SmartFusion2 and IGLOO2 Programming Modes (Except M2S/M2GL050 Device) . . . . . . . . . . . . 3

Table 2 M2S/M2GL050 Programming Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 3 Available Programming Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 4 State of Programming Interface During Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 5 Programming Bitstream Size (All Variations T/S/TS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 6 JTAG Pin Names and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 7 Dedicated SC_SPI Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 8 MSS/HPMS SPI_0 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 9 ISP Programming Service Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 10 ISP Programming Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 11 ISP Programming Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 12 ISP Responses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 13 ISP Programming Service Status Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 14 IAP Service Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 15 IAP Programming Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 16 IAP Programming Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 17 IAP Service Responses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 18 IAP Programming Service Status Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 19 Error Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 20 IAP Bitstream Authorization Error Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 21 Programming Recovery Configuration Settings (UCNFG[16:12]) . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 22 SPI Directory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 23 User Lock Row Strobe Bits for Programming Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 24 SPI Signal Polarity Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 25 Programming Recovery and Auto Update Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 26 ASIC Block and I/O State During Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 27 ASIC Block and I/O State During Programming Recovery/Auto Update . . . . . . . . . . . . . . . . . . . . 44

Revision History

UG0451 User Guide Revision 7.0 1

1 Revision History

The revision history describes the changes that were implemented in the document. The changes are

listed by revision, starting with the most current publication.

1.1 Revision 7.0

The following is a summary of the changes in revision 7.0 of this document.

• The programming method for auto programming SPI Directory was updated inTable 1, page 3.

• Throughout the document the term user security was changed to custom security.

• A reference was added for digest based verification in Programming Bitstream Generation, page 8.

• A precautionary note was added in Design Implementation, page 15.

• Additional references were added in Programming Recovery Implementation, page 37.

1.2 Revision 6.0

The following is a summary of the changes in revision 6.0 of this document.

• Information about IAP flow was updated. For more information, see Figure 17, page 34.

• Information about MSS ISP update flow was updated. For more information, see Figure 14, page 27.

• Information about IAP error codes was updated. For more information, see Figure 19, page 33.

• Information about programming recovery and auto update was updated. For more information, see

Figure 25, page 40.

1.3 Revision 5.0

The following is a summary of the changes in revision 5.0 of this document.

• Information about programming overview was updated. For more information, see Table 1, page 3

and Ta ble 2, page 6.

• Information about programming flow was updated. For more information, see Programming Flow,

page 11.

• Information about design implementation for JTAG programming was updated. For more

information, see Design Implementation, page 15.

• Information about programming interface for SPI slave programming was updated. For more

information, Programming Interface Overview, page 13.

• Information about design implementation for auto programming was updated. For more information,

see Design Implementation, page 21.

• Information about auto programming of M2S/M2GL050 devices was added. For more information,

see Auto Programming of M2S/M2GL050 Device, page 23.

• Information about design implementation for MSS IP was updated. For more information, see

Design Implementation, page 24.

• Information about auto update was updated. For more information, see Auto Update, page 35.

• Information about configuring the MSS/HPMS SPI_0 port was updated. For more information, see

MSS/HPMS SPI_0 Port Configuration, page 39.

• Information about production programming was updated. For more information, see Production

Programming, page 41.

• Information about I/O sates was updated. For more information, see State of SmartFusion2 and

IGLOO2 Components During Programming, page 42.

• Changed the document to the new template.

1.4 Revision 4.0

Updated introduction of Auto Programming chapter (SAR 67871).

1.5 Revision 3.0

The following is a summary of the changes in revision 3.0 of this document.

Revision History

UG0451 User Guide Revision 7.0 2

• Merged SmartFusion2 and IGLOO2 user guide.

• Updated Table 3-1 (SAR 57679 and 63009).

• Updated Table 1-1 (SAR 59429).

• Updated Programming Bitstream Generation section (SAR 62487).

1.6 Revision 2.0

The M2GL005 device was added to Table 1-2. Figure 2-5, Figure 2-7, and Figure 3-1 were revised. SPI

content added throughout.

1.7 Revision 1.0

Corrected the FlashPro4 pin number for TMS/VPUMP in Figure 2-5 (SAR 51653).

1.8 Revision 0

Revision 0 was the first publication of this document.

1.9 SmartFusion2 List of Changes Table for Reference

Date Changed Chapters

Revision 5

(May 2014)

The M2S005 device was added to Table 1-2. Figure 2-5 and Figure 2-7 were revised. SPI

content updated throughout.

Revision 4

(February 2014)

Revamped the User Guide (SAR 51186).

Revision 3

(December 2013)

Updated the JTAG Programming chapter (SAR 51652).

Revision 2

(September 2013)

Updated the JTAG Programming chapter (SAR 48287).

Revision 1

(April 2013)

Restructured the user guide.

Revision 0

(October 2012)

Initial release.

Programming Overview

UG0451 User Guide Revision 7.0 3

2 Programming Overview

The SmartFusion

2 and IGLOO

2 devices support multiple programming modes and can address various

platform requirements. Specific programming modes can be implemented based on:

• End user application

• System requirements

• Package selected

• Design phase

For information about limitations on programming capabilities by package, see Programming Interface,

page 7.

SmartFusion2 and IGLOO2 devices support programming via an external master as well as self-

programming. An external master such as a microprocessor or a programmer accesses either the

system controller's dedicated JTAG or SPI port (SC_SPI) to program the device.

Programming modes using these ports are:

• JTAG programming

• SPI-Slave programming

SmartFusion2 and IGLOO2 devices also support self-programming and those programming modes are:

• Auto programming

• Auto update

• Microcontroller Subsystem (MSS) In-System Programming (ISP) (SmartFusion2 only)

• In-Application programming

Additionally, these devices can be programmed by a standalone programmer or automatic test

equipment (ATE) before mounting them on the board. This programming mode is called production

programming. The following tables list the different programming modes and interfaces/ports used for

these modes. In the following chapters these programming methods are discussed in detail.

Table 1 • SmartFusion2 and IGLOO2 Programming Modes (Except M2S/M2GL050 Device)

Description/

Programming

Mode

JTAG/

SPI-Slave

Programming

Auto

Programming Auto Update MSS ISP 2 Step IAP

Production

Programming

Definition An external

programmer or

processor

programs the

device mounted

on the board

System

controller

programs a

blank device

when the flash

golden pin is

asserted at

device power

System

controller

programs a pre-

configured

device with a

newer image

stored in SPI

flash when the

device is

powered up

Cortex-M3 in

the MSS

fetches

bitstream from

outside the chip

and calls ISP

system service,

which programs

the FPGA

Cortex-M3 or

user logic

programs the

bitstream into

the SPI flash

connected to

SPI_0 port and

calls IAP

service call,

which programs

the FPGA

A standalone

programmer or

test equipment

programs the

FPGA before it

is surface

mount using an

adapter module

or a test fixture

Port used JTAG or

SC_SPI

MSS/HPMS

SPI_0

MSS/HPMS

SPI_0

Any

communication

peripheral

MSS/HPMS

SPI_0

JTAG

Bitstream

location

PC or on-board

flash device

External SPI

flash device

connected to

SPI_0

External SPI

flash device

connected to

SPI_0

Remote host or

on-board flash

device

External SPI

flash device

connected to

SPI_0

Programming Overview

UG0451 User Guide Revision 7.0 4

Bitstream

version

Any bitstream

(no version

dependency)

Any bitstream

(no version

dependency)

Bitstream

version has to

be greater than

existing

bitstream

version

programmed in

the FPGA.

Otherwise, auto

update does

not initiate, and

the device

powers up with

the existing

bitstream.

Any bitstream

(no version

dependency)

Any bitstream

(no version

dependency)

Any bitstream

(no version

dependency)

Bitstream

address

location in

external SPI

flash

Not applicable Non-zero

address

location of the

external SPI

flash device

SPI directory

defines where

the update

and/or golden

image is

located. Both

images have to

be in non-zero

address

location, as

address zero is

reserved for

SPI directory.

Not applicable SPI directory

defines where

the update

and/or golden

image is

located. Both

images have to

be in non-zero

address

location, as

address zero is

reserved for

SPI directory.

Not applicable

Table 1 • SmartFusion2 and IGLOO2 Programming Modes (Except M2S/M2GL050 Device)

Description/

Programming

Mode

JTAG/

SPI-Slave

Programming

Auto

Programming Auto Update MSS ISP 2 Step IAP

Production

Programming

Programming Overview

UG0451 User Guide Revision 7.0 5

SPI directory Not applicable You must

export SPI

directory while

exporting

bitstream and

program it into

the external

flash device in

address zero

location.

You must

export the SPI

directory while

exporting

bitstream and

program it into

the external

flash device in

address zero

location.

System

controller reads

the SPI

directory for the

image version.

Every time a

new image is

programmed,

you need to

export SPI

directory (by

setting

appropriate

design version

and/or address)

and program

the flash device

before initiating

auto update.

Not applicable You must

export SPI

directory while

exporting

bitstream and

program it into

the external

flash device in

address zero

location.

Not applicable

Programming

recovery

support

Not supported Not supported

since the

device is blank

(recovery bit

has not been

programmed

into the device)

Supported. If

you turn on the

auto update

switch in Libero

SoC, recovery

is turned on by

default. If power

fails, the

system

controller uses

the golden

image defined

in the SPI

directory.

Supported.

First, the FPGA

needs to be

programmed

with recovery

setting enabled

in Libero SoC.

Supported.

First, the FPGA

needs to be

programmed

with recovery

setting enabled

in Libero SoC.

Not supported

Bitstream

format

JTAG

Programming—

Libero SoC

default/STAPL/

DAT

SPI-Slave-DAT

SPI SPI SPI SPI STAPLE, SVF

1. Production support for SVF is not available. Contact technical support, if you need to use the SVF format.

Table 1 • SmartFusion2 and IGLOO2 Programming Modes (Except M2S/M2GL050 Device)

Description/

Programming

Mode

JTAG/

SPI-Slave

Programming

Auto

Programming Auto Update MSS ISP 2 Step IAP

Production

Programming

Programming Overview

UG0451 User Guide Revision 7.0 6

Table 2 • M2S/M2GL050 Programming Modes

Description/

Programming

Mode

JTAG/SPI-Slave

Programming

Auto

Programming

MSS ISP 2 Step IAP

Production

Programming

Definition An external

programmer or

processor

programs the

device mounted on

the board

System controller

programs a blank

device when the

flash golden pin is

asserted at device

power up

Cortex-M3 in the

MSS fetches the

bitstream from

outside the chip

and calls ISP

system service,

which programs

the FPGA

Cortex-M3 or user

logic programs the

bitstream into the

SPI flash

connected to

SPI_0 port and

calls IAP service

call, which

programs the

FPGA

A standalone

programmer or test

equipment

programs the

FPGA before it is

surface mount

using an adapter

module or a test

fixture

Port used JTAG or SC_SPI SC_SPI Any

communication

peripheral

MSS/HPMS SPI_0 JTAG

Bitstream

location

PC or on-board

flash

External SPI flash

device connected

to SC_SPI

Remote host or on-

board flash device

External SPI flash

device connected

to SPI_0

Bitstream

version

Any bitstream (no

version

dependency)

Any bitstream (no

version

dependency)

Any bitstream (no

version

dependency)

Any bitstream (no

version

dependency)

Any bitstream (no

version

dependency)

Bitstream

address

location in

external SPI

flash

Not applicable Address 0x00

location of the

external SPI flash

device

Not applicable SPI directory

defines where the

update and/or

golden image is

located. Both

images have to be

in non-zero

address location,

as address zero is

reserved for SPI

directory.

Not applicable

SPI directory Not applicable Not needed Not applicable You must export

SPI directory while

exporting the

bitstream and

program it into the

external flash

device in the

address zero

location.

Not applicable

Programming

recovery

support

Not supported Not supported Not supported Not supported Not supported

Bitstream

format

JTAG

Programming—

Libero SoC

default/STAPL/DAT

SPI-Slave -DAT

SPI SPI SPI STAPLE, SVF

Programming Overview

UG0451 User Guide Revision 7.0 7

2.1 Programming Interface

SmartFusion2 and IGLOO2 devices support the programming interfaces listed in the following table.

However, some interfaces are not available in all the device packages. The SC_SPI port is used for auto

programming. All other devices use the MSS/HPMS SPI_0 port for auto programming.

All the packages mentioned in this table are available with lead and lead free. (G) indicates that the

package is RoHS 6/6 compliant/Pb-free.

1. Production support for SVF is not available. Contact technical support, if you need to use the SVF format.

Table 3 • Available Programming Interfaces

Devices Package JTAG SPI_0 Flash_GOLDEN_N

System Controller SPI Port

(SC_SPI)

M2S005/M2GL005 TQ(G)144 Yes Yes No No

M2S010/M2GL010 Yes Yes No No

M2S005/M2GL005 VF(G)256 Yes Yes Yes Yes

M2S010/M2GL010 Yes Yes Yes No

M2S025/M2GL025 Yes Yes Yes No

M2S025/M2GL025 FCS(G)325 Yes Yes No No

M2S050/M2GL050 Yes Yes No No

M2S060/M2GL060 Yes Yes No No

M2S090/M2GL090 Yes Yes No No

M2S005/M2GL005 VF(G)400 Yes Yes Yes Yes

M2S010/M2GL010 Yes Yes Yes Yes

M2S025/M2GL025 Yes Yes Yes Yes

M2S050/M2GL050 Yes Yes Yes Yes

M2S060/M2GL060 Yes Yes Yes Yes

M2S150/M2GL150 FCV(G)484 Yes Yes Yes Yes

M2S005/M2GL005 FG(G)484 Yes Yes Yes Yes

M2S010/M2GL010 Yes Yes Yes Yes

M2S025/M2GL025 Yes Yes Yes Yes

M2S050/M2GL050 Yes Yes Yes Yes

M2S060/M2GL060 Yes Yes Yes Yes

M2S090/M2GL090 Yes Yes Yes Yes

M2S150/M2GL150 FCS(G)536 Yes Yes Yes Yes

M2S060/M2GL060 FGG676 Yes Yes Yes Yes

M2S090/M2GL090 Yes Yes Yes Yes

M2S050/M2GL050 FG(G)896 Yes No Yes Yes

M2S150/M2GL150 FC(G)1152 Yes Yes Yes Yes

Programming Overview

UG0451 User Guide Revision 7.0 8

For board level design, it is important to know the state of these interfaces during reset. The following

table summarizes the state of these interfaces during different reset.

2.2 Programming Bitstream Generation

The Libero SoC software is used to generate the programming bitstream formats required to support the

different programming modes. Table 5, page 10 shows the different bitstream file types and sizes for

SmartFusion2 and IGLOO2 devices.

Programming is integrated into the Libero SoC software design flow. With the enhanced Libero SoC

design flow, you can program the device directly, without launching the programming software tool

(FlashPro) separately. When the design is ready for production, the programming bitstream can be

exported using the Libero SoC software.

Note: FlashPro cannot be invoked from within the Libero SoC software for SmartFusion2 and IGLOO2 devices.

The programming bitstream contains the following components, which can be selected during bitstream

generation:

• Images of FPGA fabric only

• Full or partial image of eNVM only

• Custom Security

Custom security can be implemented in the bitstream from Configure Security under Program and Debug

Design Options menu of the Design flow in the Libero SoC software.

When the bitstream is exported the digest of the selected components is printed in the Libero log window

and saved in a file under the export folder. This digest can be used to verify whether intended bitstream

was used during programming or not. For more information, see the "Digest-Based Verification Method"

section of the SmartFusion2 and IGLOO2 FPGA Security Best Practices User Guide.

The following figure shows the Libero SoC programming bitstream generation flow. There are two

programming options:

• Option 1: The programming bitstream file is generated by clicking Generate Programming Data.

SmartFusion2 and IGLOO2 devices can be programmed from within the tool, provided the target

board is connected with the FlashPro4/FlashPro5 programmer. Option 1 is used for JTAG

programming mode.

• Option 2: After implementation of the design, the appropriate programming bitstream can be

exported and later used in any of the supported programming modes.

Table 4 • State of Programming Interface During Reset

Programming

Interface

During Power on

Reset

During

DEVRST_N

1. DEVRST_N is an asynchronous reset pin and must be asserted only when the device is unresponsive because of some

unforeseen circumstances.Do not assert the DEVRST_N pin during programming operation, which might cause severe

consequences including corrupting the device configuration.

During System Control

Reset During MSS Reset

JTAG port JTAG I/Os are

enabled

JTAG I/Os are

enabled

JTAG I/Os enabled, but not

functional as JTAG operation

within the system controller

relies on TRSTB being

negated but held asserted for

system controller’s suspend

mode

Unaffected

System control SPI port

(SC_SPI)

Disabled (floating,

no pull ups)

Disabled

(floating, no

pull ups)

Active but not functional Unaffected

MSS/HPMS SPI_0 port Disabled (floating,

no pull ups)

Disabled

(floating, no

pull ups)

Depends on user

configuration

Depends on user

configuration

Programming Overview

UG0451 User Guide Revision 7.0 9

Figure 1 • Libero SoC Programming Bitstream Generation Flow

2.2.1 Programming Bitstream

The programming bitstream contains programming data for FPGA fabric and/or eNVM (partial or full

content). Programming bitstream is always encrypted with the default key.

For additional security, custom security keys can be set in the security policy manager (SPM). For more

information, see the SPM section in the Libero SoC User Guide. If custom security is used default key

will be disabled.

The following table lists the bitstream size. Size does not change with device utilization. For information

about devices offering with and without transceivers and data security (T, TS, S), see the SmartFusion2

Product Brief and IGLOO2 Product Brief.

Create Design

Handoff Design for Production

- Export Bitstream

- Export Programming Job

FlashPro/FlashPro Express

All other Programming Methods

Post-Compile PDC file

- Post-Compile I/O PDC file generated

automatically if you explicitly add/modify your

I/O constraints after compilation

Post-Compile I/O Editor

- Assign pins and attributes

- Check rules

- State Management on Modifications

Pre-Compile Constraint Editor

- I/O constraint and Floorplan constraint

files are separated

- Enables you to import timing constraint (SDC)

files before compilation

Create Constraints

Compile

Place-and-Route

Program Design

- Generate Bitstream

- Run Program Action

Synthesis

Option 1

Option 2

Programming Overview

UG0451 User Guide Revision 7.0 10

Note:

Table 5 • Programming Bitstream Size (All Variations T/S/TS)

Device File Type

Full Fabric

(in KB)

Full eNVM

(in KB)

Full Fabric + Full

eNVM (in KB)

Full Fabric + Full eNVM +

Custom Security (in

KB)

1. File size with custom security is larger because of the encryption added to the file.

M2S005/M2GL005 STAPL 522 270 731 1409

SPI

2. SPI file size with and without custom security option is the same, because the security component in it is small.

296 135 429 429

DAT 297 135 431 860

M2S010/M2GL010 STAPL 933 482 1354 2655

SPI 556 269 823 823

DAT 557 269 825 1648

M2S025/M2GL025 STAPL 1945 482 2367 4679

SPI 1195 269 1463 1463

DAT 1197 269 1464 2926

M2S050/M2GL050 STAPL 3792 482 4213 8373

SPI 2363 269 2630 2630

DAT 2364 269 2632 5261

M2S060/M2GL060 STAPL 3799 480 4211 8360

SPI 2363 263 2624 2624

DAT 2364 263 2625 5248

M2S090/M2GL090 STAPL 5690 900 6526 12996

SPI 3561 532 4092 4092

DAT 3564 533 4095 8186

M2S150/M2GL150 STAPL 9539 900 10376 20696

SPI 5996 532 6527 6527

DAT 5997 533 6528 13054

Programming Overview

UG0451 User Guide Revision 7.0 11

2.3 Programming Flow

The following steps summarize the SmartFusion2 and IGLOO2 programming flow:

1. Checks if the device ID matches with that of the file loaded. If yes, the device enters programming

mode.

Note: I/O settings are driven by the BSR during programming.

2. Checks if the security settings of the device matches with that of the programming bitstream. If yes,

the bitstream is authenticated.

3. The following operations occur while the SmartFusion2 and IGLOO2 programming bitstream is

processed:

a. Erases all the features selected (fabric, fabric configuration, and security) to be programmed.

eNVM is not erased; it is reprogrammed only when eNVM programming is selected.

b. If the custom security features are selected to be programmed, they are programmed before

programming the fabric and eNVM.

c. If the FPGA fabric is selected for programming in the bitstream, the fabric is programmed while

processing the bitstream. Verification is built into the programming. If programming is interrupted

or fails in the middle of bitstream, the device is not enabled. The fabric is enabled only after the

entire bitstream is successfully programmed.

Note: The programming action in STAPL provides an optional DO_VERIFY step. This is a separate verification

process that takes additional programming time. This is disabled by default.

d. If eNVM programming is selected, the eNVM blocks are programmed (X = 0,1, depending on the

die size). Verification is built into the eNVM programming.

e. Exits programming mode. I/O control is transferred from BSR to the fabric design.

Note: Upon completion of the programming, the system controller resets the entire device to implement the

new design. If the Cortex-M3 processor (SmartFusion2 only) is used to update the eNVM, the rest of the

device continues to operate.

JTAG Programming

UG0451 User Guide Revision 7.0 13

3JTAG Programming

SmartFusion2 and IGLOO2 devices support programming using a dedicated JTAG port. The system

controller implements the functionality of a JTAG slave and complies to IEEE 1532 and IEEE 1149.1

standards. The JTAG port communicates with the system controller using:

• A command register that sends the JTAG instruction to be executed.

• A 128-bit data buffer that transfers any associated data.

To start programming using JTAG, the device must not be in Flash*Freeze (F*F) mode. When a device is

not in a programmed state, all user I/O pins are disabled, that is, tristated. This is achieved by keeping

the global IO_EN signal internal signal deactivated, which disables the input buffers. I/O states during

JTAG programming can be configured in Libero SoC. For more information, see State of SmartFusion2

and IGLOO2 Components During Programming, page 42.

3.1 Programming Interface Overview

SmartFusion2 and IGLOO2 devices can be programmed through the dedicated JTAG interface. An

external programmer (such as FlashPro4/5) or a microprocessor is used to program the device. The

devices can be programmed in both single and chain modes. SmartFusion2 and IGLOO2 devices have

JTAG pins in a dedicated bank. The location of the bank varies depending on the package. For more

information about the bank and its location, see SmartFusion2 Pin Descriptions.

JTAG signals can be operated at 1.2 V, 1.5 V, 1.8 V, 2.5 V, or 3.3 V. Therefore, the JTAG bank voltage

can be set to any of these voltages. The logic level of the JTAG signals depends on the JTAG bank

voltage. The following table lists the JTAG pin names, descriptions, and their termination details.

Note: If the JTAG programming mode is not used, JTAG pins must be terminated.

Table 6 • JTAG Pin Names and Description

Name Direction

Weak

Pull Up Termination Description

JTAGSEL Input Yes Terminate with

1 K pull up to

JTAG power

supply

JTAG controller selection.

If JTAGSEL is pulled high, an external TAP controller

connects the JTAG interface to the system controller TAP.

This is the recommended setup for programming and

microcontroller debug through SoftConsole.

Tie to GND

through 1 K

If JTAGSEL is pulled low, an external TAP controller

connects to either the Cortex-M3 JTAG TAP (if debug is

enabled) or an auxiliary TAP (if debug is disabled).

This is the recommended setup for microcontroller

debugging using tools such as IAR or KEIL (SmartFusion2

only). For IGLOO2 based designs, this signal must be held

high through the 1 K pull-up resistor.

JTAG_TCK/

M3_TCK

Input No Microsemi

recommends

TCK to be tied to

VSS or VDDI

through a resistor

on the board

when unused.

This is according

to IEEE 1532

requirements.

Clock input to JTAG controller and UJTAG

If JTAG is not used, Microsemi recommends tying it off. The

tied off resistor must be placed close to the FPGA pin. This

prevents creation of totem-pole current due to random

oscillations on the input buffer and operation if TMS enters

an undesired state.

JTAG Programming

UG0451 User Guide Revision 7.0 14

3.1.1 JTAG Timing Diagram

The following figure shows the JTAG signals timing diagram. The JTAG 1532 Timing Characteristics table

of the SmartFusion2 and IGLOO2 Datasheet specifies the timing numbers to be met to ensure proper

operation of the JTAG circuitry.

Figure 2 • JTAG Signals Timing Diagram

JTAG_TDI/

M3_TDI

Input Yes Not required Serial data input to JTAG boundary scan, UJTAG, and ISP.

UJTAG uses this pin or this pin aids another component to

use JTAG, ISP, and UJTAG.

JTAG_TDO/

M3_TDO

Output No Not required Serial data output from JTAG boundary scan, UJTAG, and

ISP. UJTAG uses this pin or this pin aids another component

to use JTAG, ISP, and UJTAG.

JTAG_TMS/

M3_TMS

Input Yes Not required The TMS pin controls the use of the following IEEE1532

boundary scan pins: TCK, TDI, TDO, and TRSTB.

JTAG_TRSTB/

M3_TRSTB

Input Yes Tie to GND

through 1 K

Reset pin for JTAG controller.

The TRSTB pin functions as an active low input to

asynchronously initialize or reset the boundary scan

circuitry. If JTAG is not used, an external pull-down resistor

can be included to ensure that the TAP is held in reset

mode. In critical applications, an upset in the JTAG circuit

could lead to an undesired JTAG state. In such cases,

Microsemi recommends tying off TRSTB to GND through a

resistor placed close to the FPGA pin.

1. Available only in SmartFusion2.

2. The UJTAG macro is a special purpose macro. It provides access to the user JTAG circuitry on-board the chip. You must

instantiate a UJTAG macro in the design to make use of the user JTAG feature. The TMS, TDI, TCK, TRSTB, and TDO pins of

the macro must be connected to the top-level ports of the design.

Table 6 • JTAG Pin Names and Description (continued)

Name Direction

Weak

Pull Up Termination Description

DISU

DIHD

TMSSU

TMSHD

TCK

TMS

TDI

TDO

TCK2Q

Tristate

JTAG Programming

UG0451 User Guide Revision 7.0 15

3.1.2 Design Implementation

FPGA fabric, embedded non volatile flash memory (eNVM), and custom security settings can be

programmed using JTAG programming mode. These can be programmed individually, or at the same

time.

Note: During JTAG or SPI-Slave programming, do not run any of the AES/DRBG/ECC Point Multiplication

system services when System controller is processing the initial component of the bitstream (BITS). The

system service may corrupt the bitstream information if the user design requests AES/DRBG/ECC Point

Multiplication system services. This issue does not exist in Auto-update, IAP or Programming recovery. If

these security system services must be run during programming, you must generate a STAPL/DAT file

using Libero 11.8 SP3 or contact soc_tech@microsemi.com to use older Libero versions.

• During programming, the board must provide power to the following pins: VPP, VPPNVM, VDD, and

VDDIOx (x: number of the JTAG I/Os). VDDIOx provides power to the JTAG circuitry. For information

about the voltage range, see the SmartFusion2 and IGLOO2 Datasheet.

• A USB-based FlashPro4/5 programmer

can be used to program the SmartFusion2 and IGLOO2

devices using this dedicated JTAG interface. Libero SoC (or standalone FlashPro) software

executes the programming from a PC connected to the programmer.

The following figure shows the FlashPro4/5 programmer connected to the JTAG ports of the

SmartFusion2 device. Only this programming mode is supported by the current version of the Libero SoC

software.

Figure 3 • JTAG Programming Mode

A single FlashPro4/5 programmer can program multiple FPGAs (same or different family) with multiple

non-Microsemi devices in a single JTAG chain, concurrently, as shown in the following figure.

The TDO pin of the JTAG header represents the beginning of the chain and the TDI pin of the last device

is connected back to the JTAG header. While programming any Microsemi device in the chain, the Libero

SoC (or standalone FlashPro) software puts non-Microsemi devices in the chain into bypass mode. Once

a device is in bypass mode, its data register length becomes one and does not react to any programming

instructions given by the programmer. To put the device into bypass mode, the programmer must know

its instruction register (IR) length.

For Microsemi devices, the IR length is obtained from the database built in the FlashPro software. For

non-Microsemi devices, the boundary scan description language (BSDL) file must be loaded or the IR

length manually entered in the FlashPro software. For more information, see the FlashPro User Guide.

SmartFusion2/IGLOO2

System

Controller

FlashPro4/5*

USB

*The FlashPro3 programmer can be used in JTAG programming mode but it has been discontinued.

JTAG I/Os

Page is loading ...

Microsemi IGLOO2 FPGA DSP FIR Filter User manual

Brand: Microsemi

Model: IGLOO2 FPGA DSP FIR Filter

Type: User manual

This manual is also suitable for

SmartFusion2 MSS

Download PDF

report

Microsemi IGLOO2 FPGA DSP FIR Filter User manual

This manual is also suitable for

Microsemi IGLOO2 FPGA DSP FIR Filter User manual

Related papers

Other documents