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Eurotech CPU-161-18 Owner's manual

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CPU-161-18
COM Express CPU Module
CARRIER BOARD DESIGN GUIDE
CARRIER BOARD DESIGN GUIDE
First edition – June 2017 – B35071J0-MN003-00_UserMan_En_1
© 2017 Eurotech
Preface
This document provides information to design a carrier board for CPU-161-18 which is COM Express CPU
Module. Please read this document so that you may obtain the greatest benefit from the device.
Trademarks
All trademarks both marked and unmarked appearing in this document are the property of their respective owners.
This document does not give permission to the implementation of patents or other rights held by Eurotech or third
parties.
Revision history
Revision
Description
Date
1
First release
28 June 2017
CPU-161-18 Carrier Board Design Guide Table of contents
B35071J0-MN003-00_UserMan_En_1
Table of contents
Preface ........................................................................................................................................................................ 2
Trademarks .................................................................................................................................................................. 2
Revision history ........................................................................................................................................................... 2
Table of contents .......................................................................................................................................................... 3
Conventions ................................................................................................................................................................. 5
1. Overview .................................................................................................................................................................... 7
2. Mechanism ................................................................................................................................................................. 8
3. Serial Console and Video Output ............................................................................................................................ 9
4. Boot Device.............................................................................................................................................................. 10
5. Power Source .......................................................................................................................................................... 11
6. Control Signal .......................................................................................................................................................... 13
6.1. Reset Signal ....................................................................................................................................................... 13
6.2. Power Button Signal ........................................................................................................................................... 13
6.3. Battery Low Voltage Sense Signal ..................................................................................................................... 13
7. I/O Port ..................................................................................................................................................................... 14
7.1. High Speed Signal .............................................................................................................................................. 14
7.2. Signal Trace Guideline ....................................................................................................................................... 15
7.3. PEG / PCI Express ............................................................................................................................................. 16
7.4. USB .................................................................................................................................................................... 20
7.5. SATA .................................................................................................................................................................. 22
7.6. Ethernet .............................................................................................................................................................. 23
7.7. UART .................................................................................................................................................................. 24
7.8. Analog VGA ........................................................................................................................................................ 24
7.9. DisplayPort ......................................................................................................................................................... 24
7.10. Embedded DisplayPort ..................................................................................................................................... 24
7.11. I
2
C ..................................................................................................................................................................... 24
7.12. SMBus .............................................................................................................................................................. 25
7.13. LPC ................................................................................................................................................................... 25
7.14. HD Audio .......................................................................................................................................................... 26
7.15. GPIO ................................................................................................................................................................. 26
7.16. Speaker ............................................................................................................................................................ 27
7.17. SPI .................................................................................................................................................................... 27
7.18. THRM ............................................................................................................................................................... 27
8. Connector Signal .................................................................................................................................................... 28
9. Carrier Board Design Checklist ............................................................................................................................. 36
Notes ............................................................................................................................................................................ 37
CPU-161-18 Carrier Board Design Guide Important User Information
B35071J0-MN003-00_UserMan_En_1
Conventions
The following table describes the conventions for signal names used in this document.
Convention
Explanation
GND
Digital ground plane
#
Active low signal
+
Positive signal in differential pair
-
Negative signal in differential pair
NC
No connection
RSVD
Use is reserved to Eurotech
PU
Pull-up
PD
Pull-down
R **Ω
Series connection with **Ω resistor
C **F
Series connection with **F capacitor
I/O
Bidirectional signal
I
Input signal
O
Output signal
OD
Open-drain output signal
PI
Power input
CPU-161-18 Carrier Board Design Guide Overview
B35071J0-MN003-00_UserMan_En_1
1. Overview
This document is a design guide for designing a carrier board on which CPU-161-18 is mounted.
CPU-161-18 is a COM Express CPU Module, featuring Intel Xeon Processor D-1500 series or Pentium
Processor D1500 series, and compatible with PICMG COM.0 R2.1. Combining CPU-161-18 with a carrier board
that meets the customer’s needs allows a variety of integrated systems to be built as desired.
In conjunction with this document, refer to the documents below.
• PICMG COM Express Carrier Design Guide Revision 2.0
• CPU-161-18 Instruction Manual
Mechanism CPU-161-18 Carrier Board Design Guide
B35071J0-MN003-00_UserMan_En_1
2. Mechanism
Use the 0.5 mm pitch 440 pin connector pair to connect CPU-161-18 to the carrier board. CPU-161-18 is
equipped with the Tyco Electronics connector 3-1827231-6 or the equivalent. For a stacking connector to be
mounted on the carrier board, use the Tyco Electronics connector 3-1827233-6 or the equivalent for a board to
board spacing of 5mm, and use 3-5353652-6 of the same manufacturer or the equivalent for a board to board
spacing of 8 mm. (To meet the exacting mounting accuracy for the connector, it is recommended to use 3-
1827233-6 or 3-5353652-6. The connector 3-1827233-6 or 3-5353652-6 has a jig to keep the distance between
two connectors, enabling excellent mounting accuracy. When mounting two 220 connectors without using a
stacking connector, two connectors cannot be kept parallel to each other, which may cause a fitting failure.)
The relative position of the connectors to be mounted on the carrier board and the mounting holes for CPU-161-
18 is as shown in Fig.1. The connector pin numbers are also given in Fig.1. The component mounting height in
the overlapped part of CPU-161-18 on the carrier board (The outline of CPU-161-18 is indicated by the dashed
lines in Fig.1.) is limited. For a board to board spacing of 5 mm, the height is limited to 1.0 mm. For a board to
board spacing of 8 mm, the height is limited to 4.0 mm.
CPU-161-18 has 5 mounting holes for fixing the board (Fig.1). Place 4 or 5 mounting holes on the carrier board to
fix the board. Especially in the two areas closest to the connector, place mounting holes to secure the board to
the carrier board. It is recommended to create a Φ2.7 mm through hole with a Φ6 mm pad as a mounting hole.
Connect the pad to the digital ground of the carrier board.
To mount a connector for a board to board spacing of 8 mm, use a M2.5×8 mm spacer. To mount a connector for
a board to board spacing of 5 mm, use a M2.5×5 mm spacer.
CPU-161-18 has additional holes for fixing the heatsink. When using this hole for fixing the board, the male and
female threads for the screw fixing the heatsink are changed.
Figure 1. The position of the connector to be mounted on the carrier board and the mounting holes
CPU-161-18 Carrier Board Design Guide Serial Console and Video Output
B35071J0-MN003-00_UserMan_En_1
3. Serial Console and Video Output
CPU-161-18 supports a serial console. It is possible to display the BIOS menu, EFI-Shell, DOS, Linux, etc. on the
serial console Figure 2 and Figure 3 show examples of BIOS and Linux. The serial console outputs to UART Port
0(SER_TX0, SER_RX0).
CPU-161-18 uses a standard BIOS without super I/O. Customizing the BIOS allows Super I/O to be connected to
the LPC bus. To connect Super I/O, contact our sales representative with your model number.
CPU-161-18 does not have a video output, such as VGA. To output a screen to an LCD or other display, connect
a video chip, such as Silicon Motion SM750, to the PCI Express.
Figure 2. BIOS display example
Figure 3. Linux display example
Boot Device CPU-161-18 Carrier Board Design Guide
B35071J0-MN003-00_UserMan_En_1
4. Boot Device
CPU-161-18 can boot the OS from a USB device or an SATA device, as a boot device. To use HDD, SSD, CFast,
mSATA, M.2, etc., use an SATA interface. To use an SD card, convert from the USB interface to the SD interface
by using a USB-SD bridge, such as USB2244 manufactured by Microchip. To use a eUSB memory, connect the
eUSB device to the USB interface. Normally, SATA devices are faster than USB devices. CPU-161-18 does not
support booting from the PCI Express device.
CPU-161-18 Carrier Board Design Guide Power Source
B35071J0-MN003-00_UserMan_En_1
5. Power Source
The three types of power sources below are necessary to supply the power from the carrier board to CPU-161-18.
VCC_12V:
The 12V power source is used for normal operation of CPU-161-18.
VCC_5V_SBY:
The 5V power source is used for normal operation of CPU-161-18.
VCC_RTC:
Power source for battery backup. The power source is used to hold the RTC information and BIOS
set values.
Table 1 indicates specifications of each power source.
Specification of power supply
Power source
name
Use
Rated
voltage
Voltage range
Current
consumption
VCC_12V
Main power source
12V
11.4~12.6V
3.89Atyp *1
VCC_5V_SBY
Main power source
5V
4.75~5.25V
0.388Atyp *1
VCC_RTC
Power source for battery
backup
3V
2.0~3.3V
6uAmax
*1 The consumption current of main power source is the maximum current measured with a 45W processor.
Figure 4 and Table 2 show the sequence of power sources from the carrier board to CPU-161-18. Also, each
power source needs to monotonously increase. Table 3 indicates the slew rate restriction.
Figure 4. Power sequence of power supply
Power sequence (T1–T6)
No.
Sequence
Standard
T1
From activation of VCC_RTC to activation of VCC_5V_SBY
≧0ms
T2
From activation of VCC_5V_SBY to activation of VCC_12V
Not specified *1
T3
From activation of VCC_12V to assertion of PWROK
≧0ms
T4
From deassertion of PWROK to power-off of VCC_12V
≧0ms
T5
From power-off of VCC_12V to power off of VCC_5V_SBY
Not specified *1
T6
From power-off of VCC_5V_SBY to power off of VCC_RTC
≧0ms
*1 The rising orders of VCC_12V and VCC_5V_SBY are not restricted. Rising can be conducted in the order of VCC_12V and VCC_5V_SBY.
Similarly, the falling orders are not restricted. Falling can be conducted in the order of VCC_5V_SBY and VCC_12V.
VCC_RTC
VCC_12V
VCC_5V_SBY
PWR_OK
95%
95%
95%
T1
T3
T2
T4
T5
T6
Power Source CPU-161-18 Carrier Board Design Guide
B35071J0-MN003-00_UserMan_En_1
Slew rate restriction of power source
Power source name
Item
min
max
VCC_12V
Slew rate in rising
0V/ms
120V/ms
Slew rate in falling
0V/ms
12V/ms
VCC_5V_SBY
Slew rate in rising
0V/ms
50V/ms
Slew rate in falling
0V/ms
10V/ms
CPU-161-18 Carrier Board Design Guide Control Signal
B35071J0-MN003-00_UserMan_En_1
6. Control Signal
6.1. Reset Signal
CPU-161-18 is supporting a reset signal input. In the case of mounting a reset button on a carrier board, please
input this signal to CPU-161-18 as SYS_RESET# signal.
In addition, CB_RESET# signal is a reset signal output from CPU-161-18. When SYS_RESET# signal or the
PWR_OK signal will be low and software reset will be done, this signal will be asserted low.
PWR_OK signal is a signal indicating the 12V power is in a right range. As CPU-161-18 does not have a
supervisor circuit for 12V, a carrier board must control the PWR_OK signal based on the 12V power.
Reset signal
Signal
Pin
I/O
Pwr Rail
Description
SYS_RESET#
B49
I-CMOS
3.3V
System reset *1
CB_RESET#
B50
O-CMOS
3.3V
Carrier board reset *2
PWR_OK
B24
I-CMOS
3.3V
12V power monitor
* I/O is the direction from CPU-161-18 side.
*1 When not in use, please be left unconnected. (This signal is pulled up on CPU-161-18.)
*2 Minimum pulse width is 1 ms.
6.2. Power Button Signal
CPU-161-18 supports a power button signal input. In the case of mounting a power button on a carrier board,
please input this signal to CPU-161-18 as PWRBTN# signal.
Power button signal
Signal
Pin
I/O
Description
PWRBTN#
B12
I
Power button signal
* I/O is the direction from CPU-161-18 side.
* When not in use, please be left unconnected. (This signal is pulled up on CPU-161-18.)
* CPU-161-18 boots automatically when power is supplied with default BIOS settings. Users can change this setting
to wait for PWRBTN# assertion.
6.3. Battery Low Voltage Sense Signal
CPU-161-18 supports a battery low voltage sense signal input. BATLOW# signal is connected to GPIO14 pin of
the Xeon D SoC. Users can read the state (High/Low) from a GPIO register.
Battery low voltage sense signal
Signal
Pin
I/O
Description
BATLOW#
A27
I
Battery low voltage sense
* I/O is the direction from CPU-161-18 side.
* When not in use, please be left unconnected. (This signal is pulled up on CPU-161-18.)
I/O Port CPU-161-18 Carrier Board Design Guide
B35071J0-MN003-00_UserMan_En_1
7. I/O Port
7.1. High Speed Signal
There is a high speed signal in CPU-161-18, which restricts the wiring in length. Thus, attention should be paid in
designing. The following lists major high speed signals and their transmission rates. Refer to the list in designing.
The high speed signals should be wired in a preferential manner in the artwork. The next item describes on
specific provisions.
COMe PEG/PCI Express signal
･PEG_RX[0-15]P/N, PEG_TX[0-15]P/N 8Gbps
･PCIE_RX[0-7]P/N, PCIE_TX[0-7]P/N 5Gbps
Serial ATA signal
･SATA[0-3]_RXP/N, SATA[0-3]_TXP/N 6Gbps
USB3.0 signal
･USB_SSRX[0-3]P/N, USB_SSTX[0-3]P/N 5Gbps
USB2.0 signal
･USB[0-6]P/N 0.5Gbps
Clock signal
･PCIE_CK_REFP/N 100MHz
･SPI_CLK 50MHz
･LPC_CLK 33MHz
For wiring the high speed signals, the reference plane (adjacent layer) is connected to GND.
The high speed signals should be set apart from the switching power source.
CPU-161-18 Carrier Board Design Guide I/O Port
B35071J0-MN003-00_UserMan_En_1
7.2. Signal Trace Guideline
Please design along the following guidelines generally when designing a printed circuit board.
• Route traces by strip line or microstrip line. (Reference plane is digital ground recommendation)
• Maintain reference plane of traces.
• Turn traces more than 135 degree. (See Figure 5)
Figure 5. In the case of turning traces
• Route signals which are no trace length instruction as short as possible without redundancy.
• Route differential pair signals on the same layer.
• Maintain trace width and space between differential pairs signals.
• Place vias of target pair signals symmetrically in the case of transferring the layer of differential pair signals.
In addition, place two GND vias per a pair within 1.27mm of vias of the target pair signals. (See Figure 6)
Figure 6. In the case of transferring the layer of differential pair signals
• Place AC coupling capacitors symmetrically in the case of needing them for differential pair signals.
• Do not route traces under crystals, crystal oscillators, clock synthesizers, magnetic devices or ICs that use or
generate clocks.
• Avoid stubs on signals because stubs cause signal reflections and affect signal quality.
B
C
A
∠
・α is more than 135 degree.
・A is more than 4 times of trace width.
・B and C are more than 1.5 times of trace width.
Max 1.27mm
I/O Port CPU-161-18 Carrier Board Design Guide
B35071J0-MN003-00_UserMan_En_1
7.3. PEG / PCI Express
CPU-161-18 is equipped with the PEG/ PCI Express interface. CPU-161-18 is a root complex, to which PCI
Express devices such as a switch, bridge, and end point can be connected.
Table 7 indicates the link setting of PEG15..0. The link setting of PEG can be modified on the BIOS menu.
Table 8 indicates the link setting of PCIE7..4. Table 9 indicates the link setting of PCIE3..0. When the link
configuration is modified from the Default, BIOS is necessary to be modified. Please contact to sales.
PEG link configuration
COM Express
Pin Label
PCI Express Lane
Link setting 1
Link setting 2
Link setting 3
(Default)
PEG15
15
X 4
X 8
X 16
PEG14
14
PEG13
13
PEG12
12
PEG11
11
X 4
PEG10
10
PEG9
9
PEG8
8
PEG7
7
X 4
X 8
PEG6
6
PEG5
5
PEG4
4
PEG3
3
X 4
PEG2
2
PEG1
1
PEG0
0
PCI Express link configuration (PCIE[7..4])
COM
Express
Pin Label
PCI Express
Lane
Link setting 1
(Default)
Link setting 2
Link setting 3
Link setting 4
PCIE7
7
X 1
X 1
X 2
X 4
PCIE6
6
X 1
X 1
PCIE5
5
X 1
X 2
X 2
PCIE4
4
X 1
PCI Express link configuration (PCIE[3..0])
COM
Express
Pin Label
PCI Express
Lane
Link setting 1
(Default)
Link setting 2
Link setting 3
Link setting 4
PCIE3
3
X 1
X 1
X 2
X 4
PCIE2
2
X 1
X 1
PCIE1
1
X 1
X 2
X 2
PCIE0
0
X 1
Table 32 and Table 33 indicate the PCI Express signals and wiring rules.
For PEG_RX[0..15]+/-, PCIE_RX[0..7]+/-signals, an AC coupling capacitor should be implemented on the PCI
Express device side on the carrier board. Table 34 describes specifications of the AC coupling capacitor. For the
PCI Express slot, the AC coupling capacitor has been mounted on the PCI express card. Thus, the capacitor is
not necessary to mount on the carrier board.
CPU-161-18 Carrier Board Design Guide I/O Port
B35071J0-MN003-00_UserMan_En_1
PEG,PCI Express signals
Signal
Pin
I/O
Description
PCIE_CLK_REF+
A88
O
PCI Express clock signal(+)
PCIE_CLK_REF-
A89
O
PCI Express clock signal(-)
PEG_TX0+
D52
O
PEG lane.0 TX signal(+)
PEG_TX0-
D53
O
PEG lane.0 TX signal(-)
PEG_TX1+
D55
O
PEG lane.1 TX signal(+)
PEG_TX1-
D56
O
PEG lane.1 TX signal(-)
PEG_TX2+
D58
O
PEG lane.2 TX signal(+)
PEG_TX2-
D59
O
PEG lane.2 TX signal(-)
PEG_TX3+
D61
O
PEG lane.3 TX signal(+)
PEG_TX3-
D62
O
PEG lane.3 TX signal(-)
PEG_TX4+
D65
O
PEG lane.4 TX signal(+)
PEG_TX4-
D66
O
PEG lane.4 TX signal(-)
PEG_TX5+
D68
O
PEG lane.5 TX signal(+)
PEG_TX5-
D69
O
PEG lane.5 TX signal(-)
PEG_TX6+
D71
O
PEG lane.6 TX signal(+)
PEG_TX6-
D72
O
PEG lane.6 TX signal(-)
PEG_TX7+
D74
O
PEG lane.7 TX signal(+)
PEG_TX7-
D75
O
PEG lane.7 TX signal(-)
PEG_TX8+
D78
O
PEG lane.8 TX signal(+)
PEG_TX8-
D79
O
PEG lane.8 TX signal(-)
PEG_TX9+
D81
O
PEG lane.9 TX signal(+)
PEG_TX9-
D82
O
PEG lane.9 TX signal(-)
PEG_TX10+
D85
O
PEG lane.10 TX signal(+)
PEG_TX10-
D86
O
PEG lane.10 TX signal(-)
PEG_TX11+
D88
O
PEG lane.11 TX signal(+)
PEG_TX11-
D89
O
PEG lane.11 TX signal(-)
PEG_TX12+
D91
O
PEG lane.12 TX signal(+)
PEG_TX12-
D92
O
PEG lane.12 TX signal(-)
PEG_TX13+
D94
O
PEG lane.13 TX signal(+)
PEG_TX13-
D95
O
PEG lane.13 TX signal(-)
PEG_TX14+
D98
O
PEG lane.14 TX signal(+)
PEG_TX14-
D99
O
PEG lane.14 TX signal(-)
PEG_TX15+
D101
O
PEG lane.15 TX signal(+)
PEG_TX15-
D102
O
PEG lane.15 TX signal(-)
PEG_RX0+
C52
I
PEG lane.0 RX signal(+)
PEG_RX0-
C53
I
PEG lane.0 RX signal(-)
PEG_RX1+
C55
I
PEG lane.1 RX signal(+)
PEG_RX1-
C56
I
PEG lane.1 RX signal(-)
PEG_RX2+
C58
I
PEG lane.2 RX signal(+)
PEG_RX2-
C59
I
PEG lane.2 RX signal(-)
PEG_RX3+
C61
I
PEG lane.3 RX signal(+)
PEG_RX3-
C62
I
PEG lane.3 RX signal(-)
PEG_RX4+
C65
I
PEG lane.4 RX signal(+)
PEG_RX4-
C66
I
PEG lane.4 RX signal(-)
PEG_RX5+
C68
I
PEG lane.5 RX signal(+)
PEG_RX5-
C69
I
PEG lane.5 RX signal(-)
PEG_RX6+
C71
I
PEG lane.6 RX signal(+)
PEG_RX6-
C72
I
PEG lane.6 RX signal(-)
PEG_RX7+
C74
I
PEG lane.7 RX signal(+)
PEG_RX7-
C75
I
PEG lane.7 RX signal(-)
PEG_RX8+
C78
I
PEG lane.8 RX signal(+)
PEG_RX8-
C79
I
PEG lane.8 RX signal(-)
PEG_RX9+
C81
I
PEG lane.9 RX signal(+)
PEG_RX9-
C82
I
PEG lane.9 RX signal(-)
PEG_RX10+
C85
I
PEG lane.10 RX signal(+)
PEG_RX10-
C86
I
PEG lane.10 RX signal(-)
PEG_RX11+
C88
I
PEG lane.11 RX signal(+)
I/O Port CPU-161-18 Carrier Board Design Guide
B35071J0-MN003-00_UserMan_En_1
PEG_RX11-
C89
I
PEG lane.11 RX signal(-)
PEG_RX12+
C91
I
PEG lane.12 RX signal(+)
PEG_RX12-
C92
I
PEG lane.12 RX signal(-)
PEG_RX13+
C94
I
PEG lane.13 RX signal(+)
PEG_RX13-
C95
I
PEG lane.13 RX signal(-)
PEG_RX14+
C98
I
PEG lane.14 RX signal(+)
PEG_RX14-
C99
I
PEG lane.14 RX signal(-)
PEG_RX15+
C101
I
PEG lane.15 RX signal(+)
PEG_RX15-
C102
I
PEG lane.15 RX signal(-)
PCIE_TX0+
A68
O
PCI Express lane.0 TX signal(+)
PCIE_TX0-
A69
O
PCI Express lane.0 TX signal(-)
PCIE_TX1+
A64
O
PCI Express lane.1 TX signal(+)
PCIE_TX1-
A65
O
PCI Express lane.1 TX signal(-)
PCIE_TX2+
A61
O
PCI Express lane.2 TX signal(+)
PCIE_TX2-
A62
O
PCI Express lane.2 TX signal(-)
PCIE_TX3+
A58
O
PCI Express lane.3 TX signal(+)
PCIE_TX3-
A59
O
PCI Express lane.3 TX signal(-)
PCIE_TX4+
A55
O
PCI Express lane.4 TX signal(+)
PCIE_TX4-
A56
O
PCI Express lane.4 TX signal(-)
PCIE_TX5+
A52
O
PCI Express lane.5 TX signal(+)
PCIE_TX5-
A53
O
PCI Express lane.5 TX signal(-)
PCIE_TX6+
D19
O
PCI Express lane.6 TX signal(+)
PCIE_TX6-
D20
O
PCI Express lane.6 TX signal(-)
PCIE_TX7+
D22
O
PCI Express lane.7 TX signal(+)
PCIE_TX7-
D23
O
PCI Express lane.7 TX signal(-)
PCIE_RX0+
B68
I
PCI Express lane.0 RX signal(+)
PCIE_RX0-
B69
I
PCI Express lane.0 RX signal(-)
PCIE_RX1+
B64
I
PCI Express lane.1 RX signal(+)
PCIE_RX1-
B65
I
PCI Express lane.1 RX signal(-)
PCIE_RX2+
B61
I
PCI Express lane.2 RX signal(+)
PCIE_RX2-
B62
I
PCI Express lane.2 RX signal(-)
PCIE_RX3+
B58
I
PCI Express lane.3 RX signal(+)
PCIE_RX3-
B59
I
PCI Express lane.3 RX signal(-)
PCIE_RX4+
B55
I
PCI Express lane.4 RX signal(+)
PCIE_RX4-
B56
I
PCI Express lane.4 RX signal(-)
PCIE_RX5+
B52
I
PCI Express lane.5 RX signal(+)
PCIE_RX5-
B53
I
PCI Express lane.5 RX signal(-)
PCIE_RX6+
C19
I
PCI Express lane.6 RX signal(+)
PCIE_RX6-
C20
I
PCI Express lane.6 RX signal(-)
PCIE_RX7+
C22
I
PCI Express lane.7 RX signal(+)
PCIE_RX7-
C23
I
PCI Express lane.7 RX signal(-)
WAKE0#
B66
I
PCI Express Wake-up signal *1
* The above shows the I/O direction seen from CPU-161-18.
* Leave the signal unconnected when unused.
*
1
The signal is pulled up on CPU-161-18.
CPU-161-18 Carrier Board Design Guide I/O Port
B35071J0-MN003-00_UserMan_En_1
PCI Express signal trace routing rule
Parameter
Min
Typ
Max
Unit
PCIE_CLK_REF+/-
Characteristic impedance (differential)
77
85
93
Ω
Signal length (PCI Express device)
402
mm
Signal length (PCI Express slot)
228
mm
Length matching between differential pairs
0.127
mm
Spacing from other signals
0.508
mm
Via Usage
2
PEG_TX/RX[0..15]+/-, PCIE_TX/RX[0..7]+/-
Characteristic impedance (differential)
77
85
93
Ω
Signal length (PCI Express Gen1,Gen2 device)
402
mm
Signal length (PCI Express Gen3 device)
254
mm
Signal length (PCI Express Gen1,Gen2 slot)
228
mm
Signal length (PCI Express Gen3 slot)
101
mm
Length matching between differential pairs
0.127
mm
Spacing from other signals
0.508
mm
Via Usage (TX)
2
Via Usage (RX Gen1,Gen2,Gen3 device)
4
Via Usage (RX Gen1,Gen2 slot)
4
Via Usage (RX Gen3 slot)
2
* There are no trace length rules in other single-ended signals. Please route with a 50Ω±10% characteristic impedance.
PCI Express AC coupling capacitors
Parameter
Gen1
Gen2
Gen3
Unit
Capacitance
0.1
0.1
0.22
μF
Tolerance
±10
±10
±10
%
Package size
< 1608
< 1608
< 1608
mm
Temperature characteristic
X7R
X7R
X7R
PCI Express clock (PCIE_CLK_REF+/-) is output from CPU-161-18. In the case of mounting a PCI Express
device or slot on a carrier board, please connect PCIE0_CLK_REF+/- signal to a PCI Express device or slot.
(See Figure 7.)
In the case of mounting more than two PCI Express devices or slots on a carrier board, please distribute PCI
Express clock to each device or slot by using a clock buffer (IDT:ICS9DBL411BGILF or equivalent).
(See Figure 8.)
CLK
Source
CPU-161-18
Carrier board
PCIe Device/Slot
L0
for PCIe Device ：L0 ≤ 402mm
for PCIe Slot ：L0 ≤ 228mm
Figure 7. In the case of supplying PCI Express clock to a PCI Express device or slot
I/O Port CPU-161-18 Carrier Board Design Guide
B35071J0-MN003-00_UserMan_En_1
CLK
Source
CPU-161-18
Clock buffer
REF
CLKOUT1
CLKOUT2
Carrier board
PCIe Device1/Slot1
PCIe Device2/Slot2
L0
L1
L2
for PCIe Device：
L0+L1 ≤ 402mm, L0+L2 ≤ 402mm
for PCIe Slot：
L0+L1 ≤ 228mm, L0+L2 ≤ 228mm
Figure 8. In the case of distributing PCI Express clock to multiple PCI Express devices or slo
7.4. USB
CPU-161-18 is equipped with 4 ports of USB3.0 interfaces and 7 ports of USB2.0 interfaces, to which a USB
device can be connected respectively.
USB3.0 uses 4 signals lines of USB_SSTX[n]+/- and USB_SSRX[n]+/-.
USB2.0 uses 2 signal lines of USB[n]+/-.
When corresponding to the both of USB3.0 and USB2.0, 6 signal lines are used for USB_SST[n]+/-,
USB_SSRX[n]+/-, and USB[n]+/-.
Table 13 to Table 15 indicate the USB signals and wiring rules.
The USB bus power (5V) should be supplied with the carrier board, and an over-current sensing circuit should be
placed. If USB0 or USB1 becomes over-current, the USB_0_1_OC#signal should be set an open collector or
open drain signal that becomes LOW. If USB6 becomes over-current, the USB_6_7_OC#signal should be set an
open collector or open drain signal that becomes LOW. The USB_SSTX[0..3]+/-signals, and
USB_SSRX[0..3]signals, and USB[0..2]+/-signals are for USB ports built in PCH.
USB[3..6]+/-signals are used for the USB port of USB HUB. BIOS is debugged with the USB2.0 port (USB1+/-
signals).
USB signal
Signal
Pin
I/O
Description
USB_SSTX0+
D4
O
USB 3.0 port0 TX signal(+)
USB_SSTX0-
D3
O
USB 3.0 port0 TX signal(-)
USB_SSRX0+
C4
I
USB 3.0 port0 RX signal(+)
USB_SSRX0-
C3
I
USB 3.0 port0 RX signal(-)
USB_SSTX1+
D7
O
USB 3.0 port1 TX signal(+)
USB_SSTX1-
D6
O
USB 3.0 port1 TX signal(-)
USB_SSRX1+
C7
I
USB 3.0 port1 RX signal(+)
USB_SSRX1-
C6
I
USB 3.0 port1 RX signal(-)
USB_SSTX2+
D10
O
USB 3.0 port2 TX signal(+)
USB_SSTX2-
D9
O
USB 3.0 port2 TX signal(-)
USB_SSRX2+
C10
I
USB 3.0 port2 RX signal(+)
USB_SSRX2-
C9
I
USB 3.0 port2 RX signal(-)
USB_SSTX3+
D13
O
USB 3.0 port3 TX signal(+)
USB_SSTX3-
D12
O
USB 3.0 port3 TX signal(-)
USB_SSRX3+
C13
I
USB 3.0 port3 RX signal(+)
USB_SSRX3-
C12
I
USB 3.0 port3 RX signal(-)
USB0+
A46
I/O
USB 2.0 port0 signal(+)
USB0-
A45
I/O
USB 2.0 port0 signal(-)
USB1+
B46
I/O
USB 2.0 port1 signal(+)
USB1-
B45
I/O
USB 2.0 port1 signal(-)
USB2+
A43
I/O
USB 2.0 port2 signal(+)
/