Cypress CY2048WAF is a flash-programmable capacitor tuning array die for a crystal oscillator (XO). It enables fine-tuning of the output clock frequency by adjusting the capacitive load of the crystal. With low clock output jitter (4 ps typ. RMS period jitter and ±30 ps typ. peak-to-peak period jitter), the CY2048WAF is suitable for applications requiring precise timing.
Key Features:
- Flash-programmable capacitor tuning array for low ppm initial frequency clock output
- Enables fine-tuning of output clock frequency by adjusting CLoad of the crystal
- Two-pin programming interface enables programming of output frequency after packaging
Cypress CY2048WAF is a flash-programmable capacitor tuning array die for a crystal oscillator (XO). It enables fine-tuning of the output clock frequency by adjusting the capacitive load of the crystal. With low clock output jitter (4 ps typ. RMS period jitter and ±30 ps typ. peak-to-peak period jitter), the CY2048WAF is suitable for applications requiring precise timing.
Key Features:
- Flash-programmable capacitor tuning array for low ppm initial frequency clock output
- Enables fine-tuning of output clock frequency by adjusting CLoad of the crystal
- Two-pin programming interface enables programming of output frequency after packaging
Flash Programmable Capacitor Tuning Array Die
for Crystal Oscillator(XO)
CY2048WAF
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07738 Rev. *A Revised December 12, 2005
Features
• Flash-programmable capacitor tuning array for low
ppm initial frequency clock output
• Low clock output jitter
— 4 ps typ. RMS period jitter
— ±30 ps typ. peak-to-peak period jitter
• Flash-programmable dividers
• Two-pin programming interface
• On-chip oscillator runs from 10–48-MHz crystal
• Five selectable post-divide options, using reference
oscillator output
• Programmable asynchronous or synchronous OE and
PWR_DWN modes
• 2.7V to 3.6V operation
• Controlled rise and fall times and output slew rate
Benefits
• Enables fine-tuning of output clock frequency by
adjusting C
Load
of the crystal
• Allows multiple programming opportunities to correct
errors, and control excess inventory
• Enables programming of output frequency after
packaging
• PPM clock output error can be adjusted in package
• Provides flexibility in output configurations and testing
• Enables low-power operation or output enable function
• Provides flexibility for system applications through
selectable instantaneous or synchronous change in
outputs
• Enables encapsulation in small-size, surface-mount
packages
Block Diagram
Die Pad Description
Horizontal Scribe
Vertical
Scribe
Y (max)
X(max)
6
OUT
2
3
4
VDD
XIN
PD#/OE
5
7C80330A
1
XOUT
die#/rev
VSS
Notes:
X(max): 980 µm, Y(max): 988 µm
Bond pad opening: 85 µm x 85 µm
Pad pitch: 175 µm (min.)
Scribe: X = 70 µm, Y = 86 µm
Wafer thickness: 11 mils (Typ.)
PD#/OE
VSS
VDD
(SDATA/VPP)
XIN
XOUT
CRYSTAL
OUT
/ 1, 2, 4, 8, 16
OSCILLATOR
CONFIGURATION
(SCL)
[+] Feedback
CY2048WAF
Document #: 38-07738 Rev. *A Page 2 of 7
Die Pad Summary (Pad coordinates are referenced from the center of the die (X = 0, Y = 0))
Name Pad Number Description X coordinate (µm) Y coordinate (µm)
VDD 1 Voltage Supply –360.8 353.7
XOUT 2 Oscillator Drain –360.8 134.1
XIN 3 Oscillator Gate –360.8 –42.6
PD#/OE 4 Programmable power-down or output enable pin –360.8 –275.9
VPP High voltage for programming NV memory
SDATA Serial data pin used for programming in test mode
OUT 6 Clock output 360.0 353.7
SCL Serial clock for programming in test mode
VSS 5 Ground 360.0 –354.5
[+] Feedback
CY2048WAF
Document #: 38-07738 Rev. *A Page 3 of 7
Absolute Maximum Conditions
(Above which the useful life may be impaired.
For user guidelines, not tested.)
Supply Voltage (V
DD
)........................................–0.5 to +7.0V
DC Input Voltage......................................–0.5V to V
DD
+ 0.5
Output Short Circuit Current.....................................± 50 mA
Storage Temperature (Non-condensing) .... –55°C to +125°C
Junction Temperature................................ –40°C to +125°C
Data Retention @ Tj = 125°C................................> 10 years
ESD (Human Body Model) MIL-STD-883.................> 2000V
Note:
1. Not 100% tested.
Crystal Specifications
[1]
Parameter Description Comments Min. Typ. Max. Unit
F
NOM
Nominal crystal frequency Fundamental mode, AT cut 10 – 48 MHz
R
1
Equivalent series resistance (ESR) Fundamental mode – – 40 Ω
R
3
/R
1
Ratio of third overtone mode ESR to
fundamental mode ESR
Ratio used because typical R
1
values are
much less than the maximum spec
4.5 – – –
C
0
Crystal shunt capacitance – – 5 pF
C
1
Crystal motional capacitance 2 – – fF
Operating Conditions
Parameter Description Min. Typ. Max. Unit
V
DD
Operating Voltage 2.7 – 3.6 V
T
J
Junction Temperature –40 – 125 °C
C
XIN
Capacitance XIN, all tuning caps OFF – 10 – pF
C
XOUT
Capacitance XOUT, all tuning caps OFF – 10 – pF
C
L
All tuning Caps OFF 4 5 6 pF
All tuning Caps ON 9.2 10 11.4 pF
C
OUT
Output Load Capacitance – – 15 pF
t
RAMP
Power-up time for V
DD
to reach minimum specified
voltage (power ramps must be monotonic)
0.05 – 500 ms
T
S
Start up time, 90% V
DD
to valid frequency on output – – 10 ms
DC Electrical Specifications TJ = –40 to 125°C over the operating range
Parameter Description Condition Min. Typ. Max. Unit
V
IL
Input Low Voltage CMOS Levels – – 20 %VDD
V
IH
Input High Voltage CMOS Levels 80 – – %VDD
V
OL
Output Low Voltage V
DD
= 2.7V–3.6V, I
OL
= 8 mA – – 0.4 V
V
OH
Output High Voltage V
DD
= 2.7V–3.6V, I
OL
= –8 mA V
DD
–0.4 – – V
I
IL
Input Low Current Input = V
SS
–110µA
I
IH
Input High Current Input = V
DD
–110µA
I
OZL
Output Leakage Current Output = V
SS
–110µA
I
OZH
Output Leakage Current Output = V
DD
––50µA
I
DD
Power Supply Current No Load, V
DD
= 3.3V, 48 MHz – – 20 mA
I
PD
Power Down Current PD# = 0V – – 25 µA
R
UP
Input Pull-up resistor V
IN
= V
SS
136MΩ
V
IN
> = 0.8V
DD
80 120 150 kΩ
R
DN
Output Pull-down resistor V
IN
= 0.5V
DD
500 900 1500 kΩ
C
IN
Input Pin Capacitance PD#/OE pin – – 7 pF
R
F
Crystal Feedback R XIN = 0 300 – 800 kΩ
[+] Feedback
CY2048WAF
Document #: 38-07738 Rev. *A Page 4 of 7
Notes:
2. T
PJ2
measured using DTS-2075, # of events set to 10, 000.
AC Electrical Specifications
[1]
over the operating range, except as noted
Parameter
[1]
Description Condition Min. Typ. Max. Unit
F
OUT
Output Frequency 0.625 – 48 MHz
DC Output Duty Cycle XTAL Buffered or Divided 45 50 55 %
T
R
Rise Time Output Clock Rise Time, Measured from 20% to
80% of V
DD
, C
OUT
= 15 pF.
2.5 ns
T
F
Fall Time Output Clock Fall Time, Measured from 80% to
20% of V
DD
, C
OUT
= 15 pF.
2.5 ns
t
PJ1
RMS Period Jitter XIN = 10–48 MHz. Measured at V
DD
/2 – 4 15 ps
t
PJ2
[2]
Peak-to-peak Period Jitter XIN = 10–48 MHz. Measured at V
DD
/2 – 30 80 ps
DL Crystal drive level 48-MHz crystal, C
L
= 7 pF, C
0
= 2 pF,
R1 = 10 Ohms, Temp. = 25°C, V
DD
= 3.6V
350–400 µW
–R Negative Resistance Measured at 48 MHz, C
L
= 10 pF, C
0
= 5 pF – – –150 Ω
F
DRIFT
Output Frequency Drift 3.0V ± 10%, 3.3V ± 10% for Temp. = 25°C –2 – 2 ppm
Phase Noise, Temp = 25°C, V
DD
= 3.3V,
F
NOM
= 10MHz, X
CAP
= 7F (Hex)
Offset dBc/Hz (Typ)
10 Hz –90
100 Hz –115
1 kHz –130
10 kHz –140
100 kHz –140
1 MHz –140
Crystal Oscillator Tuning Capacitor Values
Capacitor Bit Capacitance (pF) per Side
C
7
5.000
C
6
2.500
C
5
1.250
C
4
0.625
C
3
0.313
C
2
0.156
C
1
0.078
C
0
0.039
XOUT
C0C1C2C3C4C5C6C7 C7C6C5C4C3C2C1C0
XIN
C
XIN
C
XOUT
Figure 1. Programmable Load Capacitance
[+] Feedback
CY2048WAF
Document #: 38-07738 Rev. *A Page 5 of 7
Timing Parameters over the operating range
Parameter Description Min. Max. Unit
T
STP,SYNC
Time from falling edge on PD# to stopped output, synchronous mode, T=1/F
out
1.5T + 350 ns
T
STP,ASYNC
Time from falling edge on PD# to stopped output, asynchronous mode 350 ns
T
PU,SYNC
Time from rising edge on PD# to output at valid frequency, synchronous mode,
T=1/F
out
3ms
T
PU,ASYNC
Time from rising edge on PD# to output at valid frequency, asynchronous mode 3 ms
T
PZX,SYNC
Time from rising edge on OE to running output, synchronous mode, T=1/F
out
1.5T + 350 ns
T
PZX,ASYNC
Time from rising edge on OE to running output, asynchronous mode 350 ns
T
PXZ,SYNC
Time from falling edge on OE to high impedance output, synchronous mode,
T=1/F
out
1.5T + 350 ns
T
PXZ,ASYNC
Time from falling edge on OE to high impedance output, asynchronous mode 350 ns
Figure 2. Power-down Timing
CLOC
K
ASYN
C
CLOC
K
SYNC
P
D
T
T
STP
T
PU
T
STP
Weakly pulled LOW
Weakly pulled LOW
CLOCK
A
SYNC
CLOCK
SYNC
OE
T
T
PZX
T
PZX
Weakly pulled LOW
Weakly pulled LOW
T
PXZ
T
PXZ
Figure 3. Output Enable Timing
t
RAMP
T
S
V
DD
- 10%
0V
POWER
OUT
Figure 4. VDD Power-up Timing
[+] Feedback
CY2048WAF
Document #: 38-07738 Rev. *A Page 6 of 7
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Voltage and Timing Definitions
All product or company names mentioned in this document may be the trademarks of their respective holders.
Test and Measurement Set-up
0.1 µF
VDD
Output
C
LOAD
GND
DUT
Ordering Information
Ordering Code Package Type Operating Range (TJ)
CY2048WAF
[3]
Wafer Industrial,–40 °C to 125°C
Note:
3. The product is offered as tested die-on-wafer form. Contact Cypress Sales for additional programming information and support.
Clock
Output
V
DD
50% of V
DD
0V
t
1
t
2
Figure 5. Duty Cycle Definition
Clock
Output
t
R
t
F
V
DD
80% of V
DD
20% of V
DD
0V
Figure 6.
[+] Feedback
CY2048WAF
Document #: 38-07738 Rev. *A Page 7 of 7
Document History Page
Document Title: CY2048WAF Flash Programmable Capacitor Tuning Array Die
for Crystal Oscillator(XO)
Document Number: 38-07738
REV. ECN NO. Issue Date
Orig. of
Change Description of Change
** 319840 See ECN RGL New data sheet
*A 413511 See ECN RGL Minor Change: Pls. post in the web
[+] Feedback
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Cypress CY2048WAF is a flash-programmable capacitor tuning array die for a crystal oscillator (XO). It enables fine-tuning of the output clock frequency by adjusting the capacitive load of the crystal. With low clock output jitter (4 ps typ. RMS period jitter and ±30 ps typ. peak-to-peak period jitter), the CY2048WAF is suitable for applications requiring precise timing.
Key Features:
- Flash-programmable capacitor tuning array for low ppm initial frequency clock output
- Enables fine-tuning of output clock frequency by adjusting CLoad of the crystal
- Two-pin programming interface enables programming of output frequency after packaging
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