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NVMe-IP Demo Instruction
Rev2.1 30-Nov-17
This document describes the instruction to run NVMe-IP demo on FPGA development board by
using AB16-PCIeXOVR board. The demo is designed to write/verify data with NVMe PCIe SSD.
User can control test operation through Serial console.
1 Environment Requirement
To demo NVMe-IP on FPGA development board, please prepare following hardware/
software.
1) Supported FPGA Development board: KC705/VC707/VC709/ZC706/KCU105/ZCU106/
Zynq Mini-ITX (7Z045 model)
2) PC with Xilinx programmer software (iMPACT/Vivado) and Serial console software
3) AB16-PCIeXOVR board + power adapter cable from AB16 delivery set
Note: Zynq Mini-ITX has built-in PCIe Female connector, so the adapter board is not
required.
4) Xilinx Power adapter for Xilinx board or ATX power supply for Zynq Mini-ITX board
5) NVMe PCIe SSD connecting to PCIe Female connector on AB16/Mini-ITX board
6) micro USB cable for programming FPGA between FPGA board and PC
7) mini/micro USB cable for Serial console, connecting between FPGA board and PC
Figure 1-1 NVMe-IP Demo Environment Setup on KC705 (PCIe Gen2)
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Figure 1-2 NVMe-IP Demo Environment Setup on VC707 (PCIe Gen2)
Figure 1-3 NVMe-IP Demo Environment Setup on VC709 (PCIe Gen3)
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Figure 1-4 NVMe-IP Demo Environment Setup on ZC706 (PCIe Gen2)
Figure 1-5 NVMe-IP Demo Environment Setup on KCU105 (PCIe Gen3)
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Figure 1-6 NVMe-IP Demo Environment Setup on ZCU106 (PCIe Gen3)
Figure 1-7 NVMe-IP Demo Environment Setup on Zynq Mini-ITX (PCIe Gen2)
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2 Demo setup
1) Power off system.
2) DIP Switch setup.
a) For ZC706 board only,
i. Set SW11=”00000” to configure PS from JTAG, as shown in Figure 2-1.
ii. Set SW4=”01” to connect JTAG with USB-to-JTAG interface, as shown in Figure
2-2.
Figure 2-1 SW11 setting to configure PS from JTAG on ZC706 board
Figure 2-2 SW4 setting to use USB-to-JTAG on ZC706 board
b) For Zynq Mini-ITX board only,
i. Set SW7=”00000” to configure PS from JTAG, as shown in Figure 2-3.
ii. As shown in Figure 2-4, install a jumper on JP1 pins 1-2 to enable JTAG chain.
Install the power module on the board via J8, J9, J10 connectors, and connect
power adapter cable to FPGA board via P2 connector.
Then, user can skip to Step 5) to setup NVMe SSD for Mini-ITX board.
Figure 2-3 SW7 setting to configure PS from JTAG on Zynq Mini-ITX
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Figure 2-4 The power module installed onto the board
c) For ZCU106 only
i. Set SW6=”0000” to configure PS from JTAG, as shown in Figure 2-5.
Figure 2-5 SW6 setting to configure PS from JTAG on ZCU106
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3) Connect power adapter cable from AB16-PCIeXOVR delivery set to power connector on
FPGA board, on AB16-PCIeXOVR board, and on Xilinx power adapter as shown in Figure
2-6.
Figure 2-6 Connect power adapter cable to FPGA board, AB16, and Xilinx adapter
4) Connect A Side of PCIe connector on AB16-PCIeXOVR board to PCIe connector on Xilinx
development board, as shown in Figure 2-7. Also, check that two mini jumpers are
inserted at J5 connector on AB16.
Figure 2-7 Connect PCIe connector between AB16 and FPGA board
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5) Connect NVMe PCIe SSD to B Side of PCIe connector on AB16-PCIeXOVR board or to
PCIe Female connector on Mini-ITX board, as shown in Figure 2-8.
Figure 2-8 Connect NVMe PCIe SSD to AB16/Mini ITX board
6) a) For KC705/VC707/VC709/ZC706, connect micro USB cable from Xilinx development
board to PC for JTAG programming, and connect mini USB cable from Xilinx board to PC
for Serial console.
b) For Zynq Mini-ITX/KCU105/ZCU106, connect two micro USB cables for JTAG
programming and Serial console.
Figure 2-9 USB cable connection
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7) Power on FPGA development board and AB16-PCIeXOVR board, as shown in Figure
2-10 and Figure 2-11.
Figure 2-10 Power switch on AB16 board
Figure 2-11 Power switch on FPGA board
8) Open Serial console such as TeraTerm, HyperTerminal. Set Buad rate=115,200 Data=8 bit
Non-Parity Stop=1.
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9) Download bit file or bat file to configure FPGA and firmware.
a) For Zynq-7000 boards (Zynq Mini-ITX/ZC706), open Vivado TCL shell, change
directory to ready_for_download, run MiniITX/zc706_nvmeTest.bat, as shown in
Figure 2-12
Figure 2-12 Command script for download demo file to ZC706/Mini-ITX by Vivado tool
b) For ZCU106 board, open Vivado TCL shell, change directory to ready_for_download,
type exec xsdb ipi_app_download.tcl, as shown in Figure 2-13
Figure 2-13 Command script for download demo file to by ZCU106 Vivado tool
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c) For other boards (KC705/VC707/VC709/KCU105), use Vivado tool to program bit file,
as shown in Figure 2-14.
Figure 2-14 Programmed by Vivado
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10) Check LED status on FPGA board. The description of LED is as follows.
GPIO LED
ON OFF
0/D4 Normal operation Clock is not locked or reset button is pressed
1/R/D5 System is busy Idle status
2/C/D6 IP Error detect Normal operation
3/L/D7 Data verification fail
Normal operation
Table 2-1 LED Definition
KC705/VC707/VC709/KCU105
ZC706
Zynq Mini ITXZCU106
Figure 2-15 4-bit LED Status for user output
11) After programming completely, LED[0] and LED[1] are ON during PCIe initialization
process. Then, LED[1] is OFF to show that PCIe completes initialization process. After
that, system is ready to receive command from user. PCIe speed is displayed on the
console and then Main menu is displayed, as shown in Figure 2-16.
KC705/VC707/VC709/KCU105ZC706
Zynq Mini ITX
ZCU106
Figure 2-16 LED status after program configuration file and PCIe initialization complete
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Figure 2-17 Main menu after program configuration file and PCIe initialization complete
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3 Test Menu
3.1 Identify Device
Select ‘0’ to send Identify command to NVMe PCIe SSD. When operation is completed, SSD
capacity and model name are displayed on the console.
Figure 3-1 Result from Identify Device menu
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3.2 Write SSD
Select ‘1’ to send Write command to NVMe PCIe SSD. Three inputs are required for this
menu.
1) Start LBA: Input start address of SSD in sector unit. The input can be decimal unit or add
“0x” as a prefix for hexadecimal unit.
2) Sector Count: Input total transfer size in sector unit. The input can be decimal unit or add
“0x” as a prefix for hexadecimal unit.
3) Test pattern: Select test pattern of test data for writing to SSD. Five types can be selected,
i.e. 32-bit increment, 32-bit decrement, all 0, all 1, and 32-bit LFSR counter.
As shown in Figure 3-2, if all inputs are valid, the operation will be started. During writing
data, current transfer size is displayed on the console to show that system still be alive.
Finally, test performance, total size, and total time usage are displayed on the console as
test result.
Figure 3-2 Input and result of Write SSD menu
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Figure 3-3 Example Test data in sector#0/#1 by increment/LFSR pattern
Test data of each sector has different 64-bit header which consists of 48-bit LBA address
and 16-bit all 0 value. 48-bit LBA address is unique value for each sector. After that, the test
pattern is filled following user selection such as 32-bit increment pattern (left window of
Figure 3-3), 32-bit LFSR pattern (right window of Figure 3-3).
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Figure 3-4 – Figure 3-6 show the error message when user input is invalid. “Invalid input”
message are displayed on the console. Then, it returns to main menu to receive new
command.
Figure 3-4 Invalid Start LBA input
Figure 3-5 Invalid Sector count input
Figure 3-6 Invalid Test pattern input
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3.3 Read SSD
Select ‘2’ to send Read command to NVMe PCIe SSD. Three inputs are required for this
menu.
1) Start LBA: Input start address of SSD in sector unit. The input can be decimal unit or add
“0x” as a prefix for hexadecimal unit.
2) Sector Count: Input total transfer size in sector unit. The input can be decimal unit or add
“0x” as a prefix for hexadecimal unit.
3) Test pattern: Select test pattern to verify data from SSD. Test pattern must be matched
with the test pattern which is used during write test. Five types can be selected, i.e. 32-bit
increment, 32-bit decrement, all 0, all 1, and 32-bit LFSR counter.
Similar to write test if all inputs are valid, test system will read data from SSD. Test
performance, total size, and total time usage are displayed after end of transfer. “Invalid
input” will be displayed if some inputs are out-of-range.
Figure 3-7 Input and result of Read SSD menu
Figure 3-8 and Figure 3-9 show the error message when data verification is failed. “Verify
fail” message is displayed with error address, expected data, and read data. User can press
keyboard to cancel read operation or wait until all read process complete.
“RESET” button must be pressed to restart the system when user cancels the operation.
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Figure 3-8 Data verification is failed, but wait until read complete
Figure 3-9 Data verification is failed, and input any keys to cancel operation
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4 Revision History
Revision Date Description
1.0 2-Jun-16 Initial version release
1.1 17-Jun-16 Support KCU105 board
1.2 5-Sep-16 Support ZC706 board
1.3 9-Sep-16 Support KC705 board
1.4 29-Sep-16 Support Zynq Mini-ITX board
1.5 28-Oct-16 Support VC709 board
1.6 14-Dec-16 Update performance result of new buffer system
2.0 8-Jun-17 New NVMe-IP version
2.1 27-Jul-17 Add LFSR pattern
2.2 30-Nov-17 Support ZCU106 board
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