Digilent Genesys ZU Reference guide

Brand: Digilent

Model: Genesys ZU

Type: Reference guide



GenesysZUReferenceManual

TL;DR

Theblackmatteboardyouareholdinginyourhandisaprototypingandevaluationboardproudly

designedbyDigilent.AtitsheartisaXilinxZynqUltraScale+MPSoCARM‐FPGAhybrid,coupledwith

upgradeablememory,networkandmultimediainterfaces,andawidevarietyofexpansionconnectors

makingitaversatilecomputingplatform.

Availableintwovariants,3EGand5EV,differentiatedbytheMPSoCmodelandsomeperipherals.Ifthe

fanstickersays5EV,ontopof3EGyougetslightlyfasterDDR4,moreFPGA,videocodecandGTH

transceiversallowingHDMISource,SinkandSFP+10G.

Usedstand‐alonewithaheartybundleinthebox,poweredbythe12Vpowersupply,itstraightup

bootsLinuxfromthemicroSDcard.ConnecttheUSBmicroBcabletoaPCandopenaterminal(115200‐

8‐N‐1)tothefirstCOMportoutofthetwothatappear.Loginandpasswordareboth“root”.Thered

buttonlabeled“POR”alwaysresetstheMPSoCandstartsthebootprocessagain.

Wanttodivedeepintodevelopment?HeadovertoourGitHubpageandusethereposthereasa

startingpoint.BuildyourownbootimageontheSDcardandbootitliketheOOBdemo.Notenough?

ConnectingtheJTAG‐HS1/HS2cabletoheaderJ28willallowforon‐the‐flyprogramminganddebug

usingXilinxVivadoandSDK.



TheDigilentGenesysZUisastand‐aloneZynqUltraScale+MPSoCprototypinganddevelopmentboard.

Itisanadvancedcomputingplatformwithpowerfulmultimediaandnetworkconnectivityinterfaces.

Theexcellentmixofon‐boardperipherals,upgrade‐friendlyDDR4,MiniPCIeandmicroSDslots,multi‐

cameraandhigh‐speedexpansionconnectorsareboundtosupportawidenumberofuse‐cases.

Furthermore,theGenesysZUisavailableintwovariantswithdifferentMPSoCoptionsandadditional

featuresforevenmoreflexibility.Differencesarehighlighted*throughoutthisdocument.

TheXilinxZynqUltraScale+MPSoCattheheartoftheGenesysZUisabigleapfromtheZynq‐7000

series.Fasterandmoreprocessorcores,upgradedmemoryinterface,integratedgigabittransceivers

bringsupportforDDR4,USBType‐C3.1,PCIe,SATA,DisplayPort,SFP+*andHDMI*.TheGenesysZUis

primarilytargetedtowardsLinux‐basedapplicationsthatallowseasyaccesstoWi‐Fi,cellularradio

(WWAN),SSD,USBSuperSpeedand4Kvideo.ThebundledmicroSDcardincludesanout‐of‐boxdemo

thatbootsaLinuximagebuiltinPetalinuxandincludessometestscriptsforsomeoftheperipherals.



Features

Featuregroup Sub‐feature GenesysZU‐3EG GenesysZU‐5EV Zedboard

Processor

APU QuadA53 DualA9

RPU DualR5

✘

MainMemory

DDR4,4GB,1866

MT/s,upgradeable

DDR4,4GB,2133

MT/s,upgradeable

DDR3,512MB,

1066MT/s,

soldered

GPU

✔ ✘

VideoCodec

✘ ✔ ✘

Programmable

logic

#oflogiccells 154K 256K 85K

Peripheral

connectivity

USBType‐C3.1Gen1

Dual‐RoleDevice

✔ ✘

MiniPCIe/mSATA

dualslot

Half‐/Full‐size

✘

USB2.0Host 2xType‐A 1xOTG

On‐boardWi‐Fi 2.4GHz

✘

Featuregroup Sub‐feature GenesysZU‐3EG GenesysZU‐5EV Zedboard

Network

connectivity

Ethernet1Gw/IEEE

1588

✔

✘(w/oIEEE1588)

WLAN/WWAN/

LoRa

option‐MiniPCIe

✘

SFP+10GEthernet

✘ ✔ ✘

Storage

SD 104MB/s 25MB/s

SSD option‐mSATA

✘

Flash ISSI256MibSNOR 128Mib

Multimedia

DisplayPort 1.2aDual‐Lane

✘

Pcam 2xDual‐Lane

✘

HDMISource

✘ ✔ ✔

HDMISink

✘ ✔ ✘

AudioCodec

✔ ✔

Expansion

Lowspeed‐Pmod 4x 5x

Mid‐speed‐SYZYGY

✔ ✘

Mid‐speed‐FMC

✔ ✔

High‐speed‐FMC

Gigabit

✘ ✔ ✘

UserI/O

LED,Buttons,

Switches

✔ ✔



FigureI:GenesysZU‐3EGcalloutdiagram

CalloutwithDescription

Callout

#



Description

Callout

#

Description

Callout

#

Description

1

6‐pinPCIepower

connector

13 Coinbatteryretainer 25 Type‐CUSB3.1

2 ExternalJTAGport 14 Pmodheaders 26 Powerswitch

3



USBJTAG/UARTport 15

Dualdigital/analog

Pmod

27

ZynqUltrascale+,heat

sinkandfan

Callout

#



Description

Callout

#

Description

Callout

#

Description

4

USB2.0host

connectors

16 Userbuttons 28 SystemMonitorheader

5



Wi‐Fichip 17 Userswitches 29

SIMcardslot(onthe

bottomside)

6

4GiBDDR4SODIMM

module

18 MiniPCIe/mSATAslot



7 Audiojacks 19 Userbuttons



8

Bootmodeselect

umper

20

MIPI(Pcam)

connectors



9



Resetbuttons 21

WirelessandSSD

activityLEDs



10

INIT,DONE,ERRand

STSLeds

22 MicroSDCardSlot



11

Zmod(SYZYGY)

connector

23 MiniDisplayPort



12 FMCLPCconnector 24 1GEthernetport





SoftwareSupport

ZynqUltraScale+MPSoCplatformsarewell‐suitedtobeembeddedLinuxtargets,andtheGenesysZUis

noexception.DigilentprovidesaPetalinuxprojectthatwasusedtobuildtheout‐of‐boximage.

TheGenesysZUisfullycompatiblewithXilinx’shigh‐performanceVivado®DesignSuiteHLWebPACK™

Edition.ThistoolsetmeldsFPGAlogicdesignandembeddedARMsoftwaredevelopmentintoaneasy

touse,intuitivedesignflow.Itcanbeusedfordesigningsystemsofanycomplexity,fromacomplete

operatingsystemrunningmultipleserverapplications,downtoasimplebare‐metalprogramthat

controlssomeLEDs.ItisalsopossibletotreattheMPSoCasastandaloneFPGAforthosenotinterested

inusingtheprocessorintheirdesign.ThetwoMPSoCpartstheGenesysZUisavailablewith,XCZU3EG

andXCZU5EV,aresupportedunderVivado'sfreeWebPACK™license,whichmeansthesoftwareis

completelyfreetouse,includingtheLogicAnalyzerandHigh‐levelSynthesis(HLS)features.TheLogic

Analyzerassistswithdebugginglogicthatisrunninginhardware,andtheHLStoolallowsCcodetobe

directlycompiledintoHDL.

InthekityouwillalsofindafreevoucherfortheXilinxMIPICSI‐2IPcores.Followtheinstructionsonthe

vouchersliptoactivatethelicense.ThisisatemporarymeasureuntilVivado2020.1hits,whichshould

includealicensefortheseIPsfreeofcharge.SeethenexttableforIP‐supportstatusforother

peripherals.

TableI:IPsupportstatus

Feature/Peripheral IPsupport Version

DDR4memory

controller

PShard‐core,WebPACKbuilt‐in 2019.1

MIPICSI‐2/Pcam PLsoft‐core,MIPICSIControllerSubsystems,bundledvoucher 2019.1

DisplayPortcontroller PShard‐core,WebPACKbuilt‐in 2019.1

Ethernet1G PShard‐core,WebPACKbuilt‐in 2019.1

USB2.0/3.0 PShard‐core,WebPACKbuilt‐in 2019.1

PCIeRoot/MiniPCIe PShard‐core,WebPACKbuilt‐in 2019.1

SATA/mSATA PShard‐core,WebPACKbuilt‐in 2019.1

On‐boardWi‐Fi/SPI

controller

PShard‐core,WebPACKbuilt‐in,open‐sourceLinuxdriver 2019.1

SFP+* PLsoft‐core,10G/25GEthernetSubsystem,licenserequired 2019.1

HDMI2.0Source/Sink* PLsoft‐core,HDMISubsystem,licenserequired 2019.1

VideoPHYController*

PLsoft‐core,WebPACKbuilt‐in,requiresprotocol‐implementationlike

theHDMISubsystemabove,supportedby5EVonly

2019.1

TheinitialVivadoversionsupportedbyDigilentforGenesysZU‐relatedprojectsis2019.1.Digilent

currentlydoesnotprovidehardwareplatformsorexamplesforXilinx'sVitisUnifiedSoftwarePlatform,

howeverVitissupportisplannedforthenearfuture.

Designresources,exampleprojects,andtutorialsareavailablefordownloadattheGenesysZU

ResourceCenter.



ZynqUltraScale+MPSoCArchitecture

ZynqUltraScale+MPSoCistheXilinxsecond‐generationZynqplatform,combiningapowerfulprocessing

system(PS)anduser‐programmablelogic(PL)intothesamedevice.TheZynqUltraScale+Processing

SystemcoreactsasalogicconnectionbetweenthePSandtheProgrammableLogic(PL)whileassisting

youtointegratecustomizedandintegratedIPcoreswiththeprocessingsystemusingtheVivadoIP

integrator.Asyoumayseeinthepicturebelow,theprocessingsystemfeaturestheArmflagshipCortex

‐A5364‐bitquad‐corerunningupto1.5GHzandCortex‐R5dual‐corereal‐timeprocessoralongwith

otherinterfacessuchas:DDRMemoryController,High‐Connectivity,GeneralConnectivity,System

Functionsetc.TheZynqUltraScale+MPSoCProcessingSystemwrapperinstantiatestheprocessing

systemsectionoftheZynqUltraScale+MPSoCfortheprogrammablelogicandexternalboardlogic.The

wrapperincludesunalteredconnectivitywiththeonespresentedabove.



FigureII:ZynqUltraScale+EG

ThePSandPLcanbecoupledwithmultipleinterfacesandothersignalstoeffectivelyintegrateuser‐

createdhardwareacceleratorsandotherfunctionsinthePLlogicthatareaccessibletotheprocessors.

Theinterfacesbetweentheprocessingsystemandprogrammablelogicmainlyconsistofthreemain

groups:theextendedmultiplexedI/O(EMIO),programmablelogicI/O,andtheAXII/Ogroups.Besides

those,thereareupto78MultiplexedI/O(MIO)portsavailablefromtheprocessingsystem.The78MIO

signalsaredividedintothreebanks,andeachbankincludes26devicepins.Eachbank(500,501,and

502)hasitsownpowerpinsforthehardwareinterface.

MIO0‐25:Bank500

MIO

500

3.3

V

Peripherals

Pin QSPI

Mini

PCIe/

SATA

DDR4

SODI

MM

MIO

Butt

ons

WI‐FI UART

O

D

I2CMUXUSB3.0

8‐bitI/O

Expander

0

QSPI_SCLK

0OUT

  

1 QSPI_D1

  

2 QSPI_D2

  

3 QSPI_D3

  

4 QSPI_D0

  

5

QSPI_SS_O

UTN

  

6(N/

C)

 

7



PCIE_PE

RSTN

    

8



DDR_S

CL

    

9



DDR_S

DA

    

10



BTN1



11



BTN0



12



WIFI_PORTEX

SCK



WIFI_PORTEX

SCK

13

 

PORTEXP_RES

ETN

14

 

PORTEX_SSN

15



WIFI_SSN



16



WIFI_PORTEX

MISO



WIFI_PORTEX

MISO

17



WIFI_PORTEX

MOSI



WIFI_PORTEX

MOSI

18



UART_TXD

IN

  

19



UART_RXD

OUT

  

20



PCIE_WA

KEN

    

21

 

0



22

 

MUX_SC

L_LS



23

 

MUX_SD

A_LS



24

 

USB30_I

NTN



25

 

PORTEXP_INT

N

Note:TheWI‐FIsignalsaresharedbythesamebusthatgoesthroughtheI/Oexpander.

MIO26‐51:Bank501

MIO5011.8VPeripherals

Pin Ethernet SD

26 ETH_TX_CLK



27 ETH_TX_D0



28 ETH_TX_D1



29 ETH_TX_D2



30 ETH_TX_D3



31 ETH_TX_CTL



32 ETH_RX_CLK



33 ETH_RX_D0



34 ETH_RX_D1



35 ETH_RX_D2



36 ETH_RX_D3



37 ETH_RX_CTL



38 ETH_INTN_PWDNN



39



SDIO_SEL

40



SDIO_DIR_CMD

41



SDIO_DIR_DAT0

42



SDIO_DIR_DAT1_3

43



SDIO_POW_EN

44 ETH_RSTN



45



SDIO_CDN

46



SDIO_R_DAT0

47



SDIO_R_DAT1

48



SDIO_R_DAT2

49



SDIO_R_DAT3

50



SDIO_R_CMD

51



SDIO_R_SCLK



MIO52‐77:Bank502

MIO5021.8VPeripherals

Pin USB2.0 Ethernet

52 USB20_CLK



53 USB20_DIR



54 USB20_DATA2



55 USB20_NXT



56 USB20_DATA0



57 USB20_DATA1



58 USB20_STP



59 USB20_DATA3



60 USB20_DATA4



61 USB20_DATA5



62 USB20_DATA6



63 USB20_DATA7



64 USB20H_CLK



65 USB20H_DIR



66 USB20H_DATA2



67 USB20H_NXT



68 USB20H_DATA0



69 USB20H_DATA1



70 USB20H_STP



71 USB20H_DATA3



72 USB20H_DATA4



73 USB20H_DATA5



74 USB20H_DATA6



75 USB20H_DATA7



76



ETH_MDC

77



ETH_MDIO



FunctionalDescription

1.PowerSupplies

1.1.PowerInput

TheGenesysZUpowerdistributionnetworkwasdesignedtomeetthespecificrequirementsofXilinx

ZynqUltraScale+MPSoCsandofthesupportedperipheraldevices.Powertotheboardisprovidedviaa

2×3PCIeATXpowerconnector.XilinxevaluationboardsuseapinoutthatisnotcompatiblewithATX,

thereforemixingpowersuppliesisnotpossible.Thebundledsupplyis12V60W‐100W,dependingon

variant.TheboardpowersuppliesareturnedonoroffwiththeSW5slideswitch.



1.2.PowerSpecifications

Figure1.2.1givesanoverviewoftheGenesysZUpowerdistributionnetwork.



Figure1.2.1:GenesysZUpowerdistributionnetworkandsupplysequencing

Note:TheVCC0V9_MGTAVCC*andVCC0V9_VCU*railsarenotusedontheGenesysZU‐3EGvariant.

Whentheboardisturnedon,the12VinputvoltageprovidedbythebundledPCIeATXsupplyisfiltered

andfedtotheseriesMOSFETsoftheprotectioncircuit.TheLM5060ICmonitorstheinputvoltageand

thecurrentdrawnbytheentireboard.Ifaninputovervoltage/undervoltageoranovercurrentcondition

isdetected,theLM5060isolatestheVCC12V0netfromtheexternalsupplybyturningofftheseries

MOSFETs.

DuringnormaloperationtheMOSFETsprovidealowimpedancepathandtheVCC12V0netiscorrectly

biasedwith12V.ThisvoltageservesbothasoutputrailfortheFMCportandpowerinputfor

downstreamvoltages.

Table1.2.1describesthelistofpowersupplyrailsimplementedonGenesysZU.Thistablecanbeused

toestimatetheavailablepowerbudgetforagivenproject.

Table1.2.1:GenesysZUpowerrails

VoltageRail Generatedfrom Min/Typ/MaxVoltage

Max

current

Usedfor

VCC12V0

12Vpower

input

12V+‐5% 8.5A

FMC,powerinputfor

otherrails

VCC5V0_STABLE VCC12V0 5V+‐5% 0.306A

IC81+IC80,

VCC3V3_STABLE

VCC5V0 VCC12V0 5V+‐5% 4A

SYZYGY,RGBLED,

Audio,USB‐s,HDMIRx

AUX

VCC3V3_STABLE VCC5V0_STABLE3.16V/3.3V/3.465V 0.224A

PlatformMCU,Supply

I2Cpull‐ups,FMC,SFP,

HDMIClock,PCIe

REFCLK

VCC3V3 VCC12V0 3.154V/3.3V/3.4V 7.64A

DDR4VDDSPD(I2C

interface),PCAMs,

LEDs,SFP,HDMI,FMC,

FPGAInternals,

SYZYGY,PMODs,PCIe,

SDCard,WI‐FI,USB

3.0,USB2.0Hub,USB

Config,DisplayPort,

Flash

VADJ VCC12V0

Selectable‐1.2V/1.5V/1.8V+‐

5%

2.4A FMC,SYZYGY,FPGA

VCC2V5 VCC12V0 2.375V/2.5V/2.625V 2.1A

DDR4VPP,MGT

Oscillators,Ethernet

VCC1V8_AUX VCC12V0 1.746V/1.8V/1.854V 1.59A

FPGAInternals,

Ethernet,DisplayPort,

Audio,USB3.0,USB

2.0,USBProg,SDCard

VCC1V8_MGT VCC2V7_LDOIN 1.746V/1.8V/1.854V 0.09A FPGAInternals

VCC1V5_PCI VCC12V0 1.5V=‐5% 0.5A PCIeport

VREF1V25 VCC3V3 1.25V+‐5% 0.01A XADCreference

VCC1V2_MGTAVTT VCC12V0 1.164V/1.2V/1.236V 0.77A FPGAInternals

VCC1V2_PSDDR VCC12V0 1.14V/1.2V/1.26V 6.87A FPGAInternals,DDR4

VCC1V1 VCC1V8_AUX 1V/1.1V/1.155V 0.49A Ethernet,HDMI

VCC0V9_MGTAVCC* VCC12V0 0.873V/0.9V/0.927V 0.55

FPGAInternals(5EV

variantonly)

VCC0V9_VCU* VCC12V0 0.873V/0.9V/0.927V 2A

FPGAInternals(5EV

variantonly)

VCC0V85_PSMGTRAVCCVCC2V7_LDOIN 0.825V/0.85V/0.875V 0.3A FPGAInternals

VCC0V85_INT VCC12V0 0.825V/0.85V/0.875V 11A FPGAInternals

VTT0V6 VCC1V2_PSDDR

0.6V(0.49xVCC1V2_PSDDR‐

0.02V…

…0.51xVCC1V2_PSDDR+0.02V)

1A DDR4VTT

VREF0V6 VCC1V2_PSDDR

0.6V(0.49xVCC1V2_PSDDR…

…0.51xVCC1V2_PSDDR)

0.01A

DDR4reference

voltage



1.3.PowerSequencing

TheboardispoweredupbyslidingtheSW5switchtotheONposition.Thevoltagesuppliesstart‐up

sequenceisdefinedbyimplementingapowergooddaisychainthatselectivelyenablesgroupsof

voltagesthatshouldstarttogether.Allsuppliesuseasoftstartmechanismtoreducethesurgecurrents

duringturnon.Thestart‐upsequenceissuggestedinFigure1.2.1andcanbedescribedinthefollowing

steps:

WhentherampingVCC12V0exceedstheturn‐ONthresholdofIC78,theVCC5V0_STABLErailstartsup.

ThistriggerstheVCC3V3_STABLEsupplyandpowerstheIC81internallogic.TheVCC3V3_STABLErail

powerstheplatformMCU.ItsvalidstateismarkedbythegreenAuxpowerONLED(LD19).

Whentheprotectioncircuitdetectsavalid12Vinput,itassertstheINPUT_PGDsignalthattriggersthe

VCC5V0startup.ThisvoltagepowerstheinternallogicofIC83andIC84.

IfVCC5V0reachesitspower‐goodthreshold,thePGOOD0=En1signalisasserted.Thisenablesthe

VCC0V85_INT,VCC0V9_MGTAVCC*,VCC2V7_LDOINandVCC0V9_VCU*voltages.Thepower‐good

signalsofallthesesuppliesarejoinedinawiredANDconfigurationandactivatePGOOD1whenallrails

havereachedtheirnominalvoltages.

Whenallvoltagesfromthefirststartinggrouphavecrossedtheirpower‐goodthresholds,the

PGOOD1=En2signalisasserted.ThisenablestheVCC1V8_AUXandVCC0V85_PSMGTRAVCCvoltagesof

thesecondgroup.

Asimilartriggermechanismappliestothethird(PGOOD2=En3)andthefourth(PGOOD3=En4)voltage

groupsasillustratedinFigure1.2.1.ThefourthgroupalsoincludesthededicatedDDR4powersupply

withallitsoutputvoltages.

Ifallvoltagesfromthefourthgrouphavesuccesfullyreachedtheirdesignedvalues,theirpower‐good

(PG_ALL)lightsupthegreenMainPowerONLED(LD20).Atthispointtheboardisfullyfunctional.

Note:theVADJrailiscontrolledseparatelybytheplatformMCUthatmustfirstsetVADJdependingon

theperipheralsusingthosevoltage.VADJisinthefourthstart‐upgroupbutitisconditionedbyavalid

EN_VADJ_CTRLsignalgeneratedbytheplatformMCU.



SlidingtheSW5switchtotheOFFpositiondisablesthepowersuppliesbypullingINPUT_PGDtoground.

ThecapacitorC405connectedtotheENterminaloftheLM5060monitoringICdelaystheVCC12V0turn

offwithapproximately200msuntilallpowersupplieshavebeensafelypoweredoff.



2.MPSoCBootProcess



Figure2.1:GenesysZUBootDiagram

2.1.JTAGBootMode

JTAGisthemostimportantcomponentofthedebugfeaturesforsoftwareandPLdevelopment.The

JTAGarchitecturehasthreeTestAccessPort(TAP)controllers:

PSTAP(mainPScontrollerwithIDCODE)

PLTAP(usedforPLconfigurationandboundaryscan)

DAP(usedforARMdebugging,Realtimeprocessingunit(RPU)andApplicationProcessingUnit(APU))

Takingintoaccountthisarchitecture,whenplacedinJTAGbootmode,theprocessor(APU)willwait

untilsoftwareisloadedbyahostcomputerusingtheXilinxtools.Aftersoftwarehasbeenloaded,itis

possibletoeitherletthesoftwarebeginexecuting,orstepthroughitlinebylineusingXilinxSDK.

ItisalsopossibletodirectlyconfigurethePLoverJTAG,independentoftheprocessor.Thiscanbedone

usingtheVivadoHardwareServer.

TheGenesysZUisconfiguredtobootinCascadedJTAGmode,whichallowsthePStobeaccessedvia

thesameJTAGportasthePL.

YouneedaJTAGprogrammertoconnectintotheJTAGchainoftheGenesysZU.Thereisanon‐board

USB‐JTAGcontrollerforwhichVivadosupportisexpectedinversion2020.1.Untilbuilt‐inVivado

supportisavailableaDigilentJTAG‐HS1orJTAG‐HS2programmingcablewillbebundledwiththekit.

Thiscableconnectstothe6‐pinheaderJ28andisalreadysupportedbyVivado.

Connectingboththeon‐boardprogrammerandthebundledprogrammingcabletothePCmightcause

conflictinVivadoHardwareServerwithnottherightcablebeingopenedandnotargetsbeingfound.

ThesolutionislaunchingHardwareServermanuallybeforeanyconnectionattemptismade,orafter

killinganyautomaticallylaunchedinstancesofhw_server.exe.LaunchingHardwareServermanuallycan

bedonefromtheVivadoTclShellusingthecommandbelow.

Vivado%hw_server‐e"setjtag‐port‐filter210205,210249"

WARNING:[Common17‐259]UnknownTclcommand'hw_server‐esetjtag‐port‐filter210205,210249'

sendingcommandtotheOSshellforexecution.Itisrecommendedtouse'exec'tosendthecommand

totheOSshell.



******Xilinxhw_serverv2019.1

****Builddate:May242019at15:13:31



INFO:hw_serverapplicationstarted

INFO:UseCtrl‐Ctoexithw_serverapplication



INFO:Toconnecttothishw_serverinstanceuseurl:TCP:<hostname>:3121

VivadoHardwareServerislaunchedintheshellandwillbelisteninguntiltheshellisclosed.Allother

XilinxtoolswillautomaticallyconnecttothisinstanceoftheHardwareServer.

FormoredetailsaboutJTAGsee“JTAGFunctionalDescription”sectioninZynqUltraScale+Device

TechnicalReferenceManual(UG1085).



2.2.microSDBootMode

TheGenesysZUsupportsbootingfromamicroSDcardinsertedintoconnectorJ9.TheSDsupported

versionis3.0.ThisbootmodesuportFAT16/32filesystemsforreadingthebootimages.Imagesearch

formulti‐bootissupported.ForSDbootmode,thebootimagefileshouldbeattherootoffirstpartition

oftheSDcard(notinsideanydirectory).ThefollowingprocedurewillallowyoutoboottheZynq

UltraScale+frommicroSDwithastandardZynqUltraScale+BootImagecreatedwiththeXilinxtools:

FormatthemicroSDcardwithaFAT32filesystem.

CopytheZynqUltraScale+BootImagecreatedwithXilinxSDKtothemicroSDcard.

RenametheZynqUltraScale+BootImageonthemicroSDcardtoBOOT.bin.

EjectthemicroSDcardfromyourcomputerandinsertitintoconnectorJ9ontheGenesysZU.

AttachapowersourcetotheGenesysZU.

PlaceasinglejumperonJP3,shortingthepinslabeled“SD”.

Turntheboardon.TheboardwillnowboottheimageonthemicroSDcard.

FormoredetailsaboutSDbootmodesee“SDBootMode”sectioninZynqUltraScale+MPSoCSoftware

DeveloperGuide(UG1137).



2.3.QuadSPIBootMode

TheGenesysZUhasanon‐board256MbitQuad‐SPIFlashfromISSIthattheZynqUltraScale+canboot

from.DocumentationavailablefromXilinxdescribeshowtouseXilinxSDKtoprogramaZynq

UltraScale+BootImageintoaFlashdeviceattachedtotheZynqUltraScale+.OncetheQuadSPIFlash

hasbeenloadedwithaZynqUltraScale+BootImage,thefollowingstepscanbefollowedtobootfrom

it:

AttachapowersourcetotheGenesysZU.

PlaceasinglejumperonJP3,shortingthetwocenterpins(labeled“QSPI”).

Turntheboardon.TheboardwillnowboottheimagestoredintheQuadSPIflash.

FormoredetailsaboutQuadSPIbootmodesee“QSPI24andQSPI32BootModes”sectioninZynq

UltraScale+MPSoCSoftwareDeveloperGuide(UG1137).



2.4.USBBootMode

ItistheonlybootmodeapartfromJTAGwheretheMPSoCtakesaslaverole.ItshowsupasaDFU

(DeviceFirmwareUpgrade)USBdevicetothePC,waitingforaconfiguration.Usingthisbootmodeyou

willbeabletoloadthenewlycreatedimageonZynqUltraScale+viatheUSBPort.Formoredetailssee

the“BootSequenceforUSBBootMode”modeinZynqUltraScale+MPSoC:EmbeddedDesignTutorial

(UG1209).



2.5.StatusLEDs

TheGenesysZUhasfourstatusLEDs:

ERR:itisassertedforaccidentallossofpower,ahardwareerrororanexceptioninthePlatform

ManagementUnit(PMU);

STS:itisassertedinsecurelockdownstate;

INIT:indicatesthePLisinitializedafterthepower‐onreset(POR);

DONE:itisassertedwhenthePLconfigurationiscompleted;

Formoredetailsaboutconfigurationpinssee“Clock,Reset,andConfigurationPins”sectioninZynq

UltraScale+DeviceTechnicalReferenceManual(UG1085).

3.MainMemory

Mainmemoryisasingle‐slotpopulatedDDR4SODIMM,alwaysupgradeablebytheuser.Itiswiredto

thePS(ProcessingSystem)sideusingthehard‐corememorycontroller.Thebundledmoduleisa4GiB

KingstonHyperXHX424S14IB/4.AlthoughthemodulesupportsDDR4‐2400CL14‐14‐14timing,datarate

islimitedbytheMPSoCandtheboard.The5EVboardvariantsupportsDDR4‐2133*,whilethe3EG

supportsDDR4‐1866.

AlthoughthebundledmoduleisnotECC‐capable,theGenesysZUis.JustpairitwithanECCmoduleand

enablethefeatureintheVivadoMPSoCPSConfigurationWizard.

3.1.Implementation

ThereisasingleSODIMMslotonthetopsideoftheGenesysZUjustnorthoftheMPSoC.Itiswiredto

thePS‐sidememorycontrollerandsupportsanySODIMMmodulecomplyingwiththememory

controller'srestrictions.ThesearedetailedintheZynqUltraScale+DeviceTechnicalReferenceManual

(UG1085),butcommonmodulesof1R/2R,x8/x16,64b/72baresupported.

Theserialpresencedetect(SPD)interfaceiswiredtoMIO8(DDR_SCL)andMIO9(DDR_SDA),accessible

throughtheI2C1controller.

ForbetterroutingsomebyteswapswereperformeddetailedinTable3.1.1.Nonibbleorbitswapswere

needed.

Table3.1.1:DDR4interfacebyteswaps.

System 7 6 5 4 3 2 1 0 8

Slot 0 1 2 3 4 5 6 7 8



ECCbyte(lane8)isequivalenttoanyofthedatabytesfromtheperspectiveoftheDRAMcomponents.

ThecontrollerandSODIMMconnectorhavededicatedECCpins(CBx),whicharenotusedonnon‐ECC

systems.ThereforetheECClane(CBx)cannotbeswappedwithotherlanes.However,byteandbit

swapsindatalanesaretransparenttotheECCfeaturesinceanyswapperformeduponwriteisreversed

backuponread.

TheWriteCRCisanewfeatureofDDR4andiscomplementaryandunrelatedtotheECCfeature.Write

CRCprotectsdataintransit,ECCprotectsdatainstorage.CRCiscalculatedbothbythecontrollerand

theDRAMtoavoiddatacorruptioninthethewritedataburst.Itcandetectsinglebit,doublebit,odd

countandonemulti‐bitUIverticalcolumnerrors.Uponerrordetection,DRAMwillasserttheALERT_n

line.Thecontrollershouldretrythewriteuponerror.

Itshouldbeenabledinsystemsthatexpectahighamountofsignalintegrityissuesandwherehigh

reliabilityisdesired.Ittradesdatarateforreliability.CRCsupportisoptionalinSODIMMmodules.Even

ifthemodulesupportsit,implementationisnoteasy.ForCRCtoworkthecontrollermustknowwhat

pinswapswereperformedonthememoryinterface.IncaseofSODIMMmodules,therearesome

restrictedpinswapspossibleandmustbedocumentedintheSPDEEPROM.Thecontrollerisexpected

toreadthese,combineitwithpinswapsonthesystemboardandassignthebitstoCRCinputs

accordingly.AccordingtoAR#68788thiscanbeachievedthroughtheDDRC.DQMAPregisters,notwell

documented.



4.Storage

4.1.Quad‐SPIFlash

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Digilent Genesys ZU Reference guide

Digilent Genesys ZU Reference guide

Digilent Genesys ZU Reference guide

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