Renesas RC32504A User manual

RC32504A
Renesas
Brand
Renesas
Model
RC32504A
Type
User manual

Renesas RC32504A is a Clock Generator that provides best-in-class performance with four output pairs programmable to CMOS, LVDS, or HCSL styles. It supports Jitter Attenuator and Synthesizer functionality for the RC32504A and only Synthesizer functionality for the RC22504A. Easily configure and program frequencies using Renesas' RICBox™ Software via USB connection and upload to the evaluation board. The combination evaluation with Renesas Low Noise power supply regulators and Renesas Low Noise fan-out buffer enables direct connection of clock output pairs to test equipment through coax cables.

Renesas RC32504A is a Clock Generator that provides best-in-class performance with four output pairs programmable to CMOS, LVDS, or HCSL styles. It supports Jitter Attenuator and Synthesizer functionality for the RC32504A and only Synthesizer functionality for the RC22504A. Easily configure and program frequencies using Renesas' RICBox™ Software via USB connection and upload to the evaluation board. The combination evaluation with Renesas Low Noise power supply regulators and Renesas Low Noise fan-out buffer enables direct connection of clock output pairs to test equipment through coax cables.

Evaluation Board Manual
RC32504A /
RC22504A
R31UH0001EU0100 Rev.1.0
Apr 21, 2021
Page 1
© 2021 Renesas Electronics
The RC32504A / RC22504A evaluation board (EVB)
is designed to help users evaluate the RC32504A
and RC22504A Clock Generators, also known as
FemtoClock 2. The RC32504A supports Jitter
Attenuator and Synthesizer functionality, and the
RC22504A supports only Synthesizer functionality.
When the evaluation board (EVB) is connected via
USB to the user’s computer running the Renesas’
RICBox™ Software, FemtoClock 2 can be configured
and programmed to generate frequencies with best-
in-class performance. FemtoClock 2 has four output
pairs that can be programmed to CMOS style, LVDS
style, or HCSL style outputs.
Features
■ Develop configurations with Renesas RICBox
software and upload to the EVB through USB
■ Can be powered from the USB connection
■ EVB is a combination evaluation with Renesas
Low Noise power supply regulators and Renesas
Low Noise fan-out buffer
■ Clock output pairs are AC coupled and can be
connected directly to test equipment through coax
cables.
Board Contents
■ Renesas RS32504A ultra-low noise synthesizer
and jitter attenuator
■ Renesas RAA214020 low-noise power supply
regulators
■ Renesas 8P34S1208I low-noise fan-out buffer
■ FTDI FT232HQ USB-to-I2C bridge
Figure 1. RC32504A / RC22504A Board
RC32504A / RC22504A Evaluation Board Manual
R31UH0001EU0100 Rev.1.0
Apr 21, 2021
Page 2
Contents
1. Functional Description .................................................................................................................................. 3
1.1 Connecting the Board to a Computer .................................................................................................... 3
1.2 Board Power Supply .............................................................................................................................. 4
1.3 Differential Output Termination Selectors ............................................................................................. 4
1.4 Miscellaneous Selectors ........................................................................................................................ 5
1.5 On-Board Crystal ................................................................................................................................... 7
1.6 Bypassing the Fan-Out Buffer at OUT0 ................................................................................................. 7
1.7 Setup and Configuration ........................................................................................................................ 8
2. Board Design................................................................................................................................................ 12
2.1 Schematic Diagrams............................................................................................................................ 15
2.2 Bill of Materials .................................................................................................................................... 17
3. Ordering Information ................................................................................................................................... 19
4. Revision History .......................................................................................................................................... 19
Figures
Figure 1. RC32504A / RC22504A Board .................................................................................................................. 1
Figure 2. Power Source Selector Example ............................................................................................................... 4
Figure 3. Power Source Selector for VDDD ............................................................................................................. 4
Figure 4. Termination Bias Jumpers ......................................................................................................................... 5
Figure 5. Termination Bias Schematic ...................................................................................................................... 5
Figure 6. OE Pin Control ........................................................................................................................................... 5
Figure 7. Lock Pin and SDA Pin Latch Control ......................................................................................................... 6
Figure 8. Buffer Input Select ..................................................................................................................................... 6
Figure 9. Crystal and XIN Input ................................................................................................................................ 7
Figure 10. OE Pin Control ......................................................................................................................................... 7
Figure 11. RC32504A / RC22504 EVB – Block Diagram ....................................................................................... 12
Figure 12. RC32504A / RC22504A Board – Top View .......................................................................................... 13
Figure 13. RC32504A Evaluation Board Schematics – Page 1 ............................................................................. 15
Figure 14. RC32504A Evaluation Board Schematics – Page 2 ............................................................................. 16
Figure 15. RC32504A Evaluation Board Schematics – Page 3 ............................................................................. 16
Figure 16. RC32504A Evaluation Board Schematics – Page 4 ............................................................................. 17
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R31UH0001EU0100 Rev.1.0
Apr 21, 2021
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1. Functional Description
1.1 Connecting the Board to a Computer
The evaluation board can be connected to a computer via the USB connector (see Figure 4). This board has a
USB-C type connector. The on-board USB-to-I2C bridge (FTDI chip) handles the data communication, and the
+5V in the USB bus powers the on-board regulators. Using a bench power supply with the VDD jacks is optional.
The board can fully function with just the USB cable to a computer.
Renesas’ RICBox Software can control the RC32504A on the board. RICBox is compatible with both the on-
board USB-to-I2C bridge and the Aardvark adapter. RICBox uses a software wizard for entering the overall
configuration and has several tools to fine tune the configuration (e.g., block diagram GUI).
The Bus Source connector J30 can be used to select the source of the communication bus. The bus will be I2C
for most communication but can also be SPI for specific tests. Pins 1 and 2 in J30 are SDA and SCL from the
FTDI chip. Pins 3 and 4 pass the SDA and SCL to the I2C level shifter. To use the on-board FTDI chip, install
jumpers on pins 1-3 and 2-4. The board will be shipped with these jumpers installed. Theoretically, any I2C
adapter can be connected to pins 3 and 4 for SDA and SCL. Pin 6 can be used as the ground connection for the
I2C connection. Pins 3, 4, 5, and 6 are arranged such that an Aardvark connector can be plugged onto pins 3, 4,
5, and 6 only (see Figure 5).
The Bus Type connector J33 is added to allow bypassing the I2C Level Shifter in case the connection type is
SPI. For default I2C operation, jumpers are installed on pins 1-3 and 2-4.
Figure 4. Communication Path Block Diagram
Figure 5. Connect Aardvark Adapter to J30
In Figure 14 the Aardvark adapter communicates with the RC32504A and the FTDI bridge chip is disconnected.
USB can still be used to power the board.
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R31UH0001EU0100 Rev.1.0
Apr 21, 2021
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1.2 Board Power Supply
The power source for each VDD pin can be selected with jumpers. The voltage for each pin, except one, is 1.8V.
The exception is VDDD, which can be powered with 1.8V or 3.3V.
The power source can be either an on-board voltage regulator or the VDD_J jack. Most power source selectors
have only two choices, 1.8V from the on-board 1.8V regulator or connect to the VDD_J J21 jack. The jack can
connect to a bench supply; this connection can be useful, for example, to measure supply current into pins.
In Figure 2 the source for the pin VDDXO is chosen to be the on-board 1.8V regulator. The two pins on the
bottom are both connected to the VDDXO pin through a power filter. The top left pin is connected to the on-
board 1.8V regulator and the top right pin is connected to the VDD_J jack. `
Figure 2. Power Source Selector Example
In Figure 3 the source for the pin VDDD is chosen to be the on-board 3.3V regulator. J25 allows three choices
for VDDD: 1.8V, 3.3V, or the VDD_J jack. The three pins on the right are all connected to the VDDD pin through
a power filter. The top left pin is connected to the on-board 3.3V regulator, the mid left pin is connected to the on-
board 1.8V regulator, and the bottom left pin is connected to the VDD_J Jack.
Figure 3. Power Source Selector for VDDD
1.3 Differential Output Termination Selectors
Each of the four differential output pairs can be programmed to LVDS, HCSL, or CMOS logic type. CMOS is a
single-ended logic type and the output pair will essentially be two CMOS outputs of the same frequency. HCSL
is the most versatile output because it can be customized. The HCSL driver is a current driver that simply turns a
current on and off. Standard HCSL turns 15mA on and off to make 750mVpp swing in 50Ω termination.
The RC32504A HCSL driver can be programmed to drive 4mA to 19mA levels. When AC coupled, the HCSL
driver can be compatible with LVDS, CML, and LVPECL signal swing requirements. Because of the output
architecture, it needs a DC coupled termination to ground to drive the current into. The circuit at each output
splits the termination into a DC part and an AC coupled RF part. The RF part is connected to the SMA edge
connectors of each output and the DC part is controlled by the termination selectors.
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Figure 4. Termination Bias Jumpers
Figure 4 shows J36 for applying DC load to OUT0. When HCSL is selected and the on-chip termination is
disabled, a jumper must be placed to provide the required DC load to ground. No jumper is needed for LVDS or
LVCMOS, and when the on-chip termination is enabled with HCSL.
Separating DC load from AC coupled RF load helps increase the signal swing on the SMA connectors for better
noise measurements. This method can also be used in the end application when the receiver input has on-chip
termination, is AC coupled, and a large signal swing is required.
Figure 5. Termination Bias Schematic
1.4 Miscellaneous Selectors
Figure 6. OE Pin Control
J32 pins 2, 4, and 6 connect together to the OE pin of the RC32504A. Apply a jumper on pins 1 and 2 to pull the
OE pin high or on 5 and 6 to pull the OE pin low. The RC32504A can be programmed to pull high or low on the
chip so in most cases no jumpers are needed on J32.
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A pull-up or pull-down jumper can also be used to latch a specific programmed configuration at power up.
When experimenting with SPI, a jumper can be applied to pins 3 and 4 to pass the CS (Chip Select) signal from
the FTDI chip to the RC32504A.
Figure 7. Lock Pin and SDA Pin Latch Control
J34 can be used to latch a specific level on the LOCK pin at power up. J35 can be used to latch a specific level
on the SDA pin at power up.
Both are used to select a specific pre-programmed configuration. It is not needed to program OTP of the
RC32504A on the evaluation board. Every possible configuration can be set up with RICBox in volatile registers.
It is not recommended to attempt to program the OTP memory because of the risk that a mistake or error can
destroy the chip.
Figure 8. Buffer Input Select
J48 can be used to select the input source for the 8P34S1208I fan-out buffer. The CLK0 input pair on the buffer
is connected to OUT0 of the FemtoClock 2, and the CLK1 input pair is connected to SMAs J46 and J47. By
default, the jumper is on CLK0 for passing OUT0 of FC2 through the buffer. Changing the jumper to CLK1 and
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another output can be passed through the buffer by connecting a pair of coax cables from that output to the
buffer input SMA pair.
The CLK0 input is DC coupled to OUT0 on FC2 to demonstrate a connection with minimum components. OUT0
on FC2 must be configured as LVDS for this to work properly. The 8P34S1208I is an LVDS fan-out buffer.
The CLK1 input is AC coupled, using the buffer VREF for DC bias, to make that input compatible with any
differential swing applied to the buffer input SMA pair.
1.5 On-Board Crystal
The evaluation board is assembled with a crystal. The default frequency for the crystal is 60MHz but Renesas
can ship the board with a different crystal frequency to better match the specific application where the
RC32504A will be used. The default 60MHz crystal is best suited for jitter attenuator applications. Synthesizer
applications with output frequencies like 156.25MHz or 312.5MHz work better with a 62.5MHz crystal, or even
better, with a 78.125MHz crystal. The crystal footprint U1 has a universal shape to allow assembly of
3.2 × 2.5 mm and 2.5 × 2.0 mm size crystals.
Figure 9. Crystal and XIN Input
1.6 Bypassing the Fan-Out Buffer at OUT0
Remove R60 and place at R59. Also remove R61 and place R58. The red rectangles are the new positions.
These two resistors are 0Ω and the change will route the OUT0 clock to the J4 and J6 SMA connectors as
opposed to the fan-out buffer input in the R60 and R61 positions.
When the fan-out buffer is not used, it is a good idea to remove jumper J49 (VDDFO) to remove power from the
fan-out buffer.
Figure 10. OE Pin Control
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1.7 Setup and Configuration
Complete the following steps to set up the RC32504A / RC22504A EVB using I2C and start the configuration of
the board.
1. Connect J31 to a USB port of the user’s computer using the USB cable supplied with the board.
2. Launch Renesas’ RICBox Software according to the instructions in the FemtoClock 2 RICBox User Guide.
The software and guide are downloadable from the RC32504A product page.
3. Following the “Getting Started” steps in the RICBox Software, an I2C connection is established between the
GUI software and the RC32504A.
4. Open an existing settings file (click Browse) or start a new configuration (click New).
Configurations that were saved recently will show in the “Recent Files” box. Double-click on a file to load the
configuration.
5. When starting a new configuration, the software first needs to know what product family to load the “Virtual
Environment” for:
This screen shows only FemtoClock 2 but it is possible to install multiple Virtual Environments for various
product families. At item 1, select FemtoClock 2 then select the specific product at item 2 and click “OK”.
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6. Select the “Operation Mode”: Synthesizer or Jitter Attenuator.
On the right are explanations and instructions. Click “Next” to go to the next screen.
7. Screen 2 has a list of Jitter Attenuator settings.
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8. Screen 3 sets up the outputs.
a. Fill in the desired output frequencies. Leave blank unused outputs.
b. Click on “Advanced Settings” at the red arrow to select Logic Type and Signal Amplitude.
c. Click “Finish” to end the Wizard and enter the main configuration utility.
9. The main configuration utility.
The buttons on the top left are Control Panel (the above screen), Wizard, Configuration, Registers, and
Block Diagram.
For more information, see the FemtoClock 2 RICBox User Guide located on the RC32504A product page.
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10. Transfer the Configuration from RICBox into the FemtoClock 2 device:
The bottom right of the screen has buttons to control the I2C connection with the device.
a. Click the “Not Connected” button to connect.
b. Click the small button to the right of “Program” to connect.
The small button next to “Read” opens I2C settings and starts a search for connected devices.
The “Connection Settings” screen allows you to select a specific device and Connect.
After attempting to Connect:
The small Connect button turns green to indicate that the connection was successful. Now click “Program” to
transfer all settings to the device.
CONNECT
SETTINGS
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2. Board Design
Figure 11. RC32504A / RC22504 EVB – Block Diagram
Each differential output clock is available on a pair of SMA connectors. Each pair of SMA connectors is AC
coupled on the board. The termination selector can provide a DC path to ground for the HCSL output type when
the on-chip termination is disabled.
Power is provided through the USB connection and regulated with RAA214020 low noise LDOs. Each power pin
can also be switched to a banana plug jack for supply current measurements or other tests.
The board has an FTDI USB-to-I2C bridge for programming FemtoClock 2 from a computer. Renesas RICBox
software is available for easy development of configurations and uploading these configurations to the
FemtoClock 2 device.
To demonstrate the use of FemtoClock 2 with fan-out buffers, an 8P34S1208I is added at OUT0 of
FemtoClock 2. When the buffer is not desired, the board can be easily modified by moving two 0Ω resistors to
pass OUT0 to its own pair of SMA connectors, just like the other outputs. The buffer has one of its two inputs
connected to OUT0 and the other connected to an SMA pair so the buffer can always be used to pass a clock
from any output through a pair of coax cables.
The LOCK pin drives an LED and the LED lights up when the pin is high. Default function assigned to the LOCK
pin is “APLL Lock” so the LED shows if the APLL is locked or not. Several other status items can be assigned to
the LOCK pin.
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Figure 12. RC32504A / RC22504A Board – Top View
Table 1. RC32504A / RC22504A – EVB Pins and Functions
Note: See Figure 12 for reference numbers in the following table.
Ref.
Name
On-Board Connector Label
Function
1 Output 0 J4, J6 Differential Clock Output 0 (not active with typical assembly)
2
Termination 0
J36
Termination Selector for Output 0 (not active with typical
assembly)
3
VDDO0
J18
Power Source Selector for pin VDDO0
4
Output 1
J7, J9
Differential Clock Output 1
5
Termination 1
J37
Termination Selector for Output 1
6
VDDO1
J20
Power Source Selector for pin VDDO1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
21
20
23
24
25
26
22
27
28
29
30
31
32
33
34
35
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Ref.
Name
On-Board Connector Label
Function
7
Output 2
J10, J12
Differential Clock Output 2
8
Termination 2
J38
Termination Selector for Output 2
9
VDDO2
J23
Power Source Selector for pin VDDO2
10
Output 3
J13, J15
Differential Clock Output 3
11
Termination 3
J39
Termination Selector for Output 3
12
VDDO3
J26
Power Source Selector for pin VDDO3
13
LED_5V
D2
LED lights when 5V USB Supply is present
14
USB Interface
J31
USB-C Type Jack for connection with the user’s computer
and interaction with Renesas RICBox Software.
15
LOCK LED
D1
LED lights up LOCK pin goes high. Default the LOCK pin
signals APLL locking.
16
DIF_IN
J2, J3
Differential Reference Clock Input
17
Power VDD Jack
J21
External Power Supply, Positive Terminal
18
Power GND Jack
J16
External Power Supply, Negative Terminal or Ground
19
VDDXO
J19
Power Source Selector for pin VDDXO (Crystal Oscillator
Power)
20
VDDA
J17
Power Source Selector for pin VDDA (Analog Power)
21
VDDREF
J22
Power Source Selector for pin VDDREF (Ref Clock Input
Power)
22
VDDD
J25
Power Source Selector for pin VDDD (Digital Power)
23
XIN
J1
Overdrive XIN pin with External Clock
24
Crystal
U9
Quartz Crystal
25
RC32504A
U2
Evaluation Device. The RC32504A can also demonstrate
RC22504A functionality.
26
Bus Source
J30
Select Communication Bus Source
27
Bus Type
J33
Select Communication Bus Type
28
OE / SPI CS
J32
OE pin Pull-Up / -Down or Latch High / Low or Pass SPI Chip
Select
29
LOCK Latch
J34
Lock pin Latch High / Low
30
SDA Latch
J35
SDA pin Latch High / Low
31
GND
GND_J1/2/3/4
Miscellaneous Ground Points
32
OUT0 Buffer Output
J41, J42
Differential Fan-Out Buffer Output
33
2nd Buffer Input
J46, J47
Alternative Fan-Out Buffer Input
34
VDDFO
J49
Power Source Selector for 8P34S1208I Fan-Out Buffer
35
Buffer Input Select
J48
Select between CLK0 = FemtoClock 2 OUT0 and
CLK1 = Buffer Input SMA pair.
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2.1 Schematic Diagrams
Figure 13. RC32504A Evaluation Board Schematics – Page 1
U9
SMD_3225-4
G2
2G4 4
S1 1
S33
DIF_INA
VDDA
RC32504A
U2
QFN24
OSCI
1
OSCO
2
VDDXO
3
VDDREF
4
CLK
5
NCLK
6VDDO3 13
NOUT2 14
OUT2 15
VDDO2 16
NOUT1 17
OUT1 18
VDDO1 19
OUT0 20
NOUT0 21
VDDO0 22
VDDA 23
LOCK 24
OE_NCS
7
SCL_SCK
8
SDA_DIO
9
VDDD
10
NOUT3
11
OUT3
12
EP
EP
J3 1
CK_EXC0
DIFFCCLKT0
LED is on
when Lock
Pin is high.
VDDO1
N1
SCL
VDDO2
C97
0.010uF
12
DIFFTERM
N3
CK_EXT1
VDDD
VDDXO
J1
1
VDDO0
D1
LED Green
A
K
R13
DNI_R0402
2
1
U3
BSS138
SOT23-3
G
1
S
2D3
SMA_X1
PLACE R2~10 NEAR
U1 OUTPUT PINS
N#0
R6
220
0603
2
1
DIFF_CLKT0
R12
50
21
R4 0
2
1
DIF_INA#
XIN
N2
1.8V
LOCKPIN
C6
0.1uF
12
LOCKPIN
LEDK
C2
DNI_C0402
1 2
R3 0
2
1
VDDREF
N0
VDD_USB
R5 0
2
1
DIFF_CLKC0
R11
50
21
C4 0.1uF
12
R2 0
2
1
J2 1
CK_EXC1
CK_EXC2
OVERLAP C1 PIN1
AND XTAL S1
R7 0
2
1
CK_EXT0
OE_NCS
Enlarge Xtal pads
towards center of
footprint to be
able to assemble
down to 2.0x1.6mm
size crystals
R63
4.70K
2
1
LEDA
50 ohm SE
R14
DNI_R0402
2
1
LOCKPIN
C3
DNI_C0402
1 2
N#2
LOCK_SMA
DIFFCCLKC0 CK_EXC[3..0]
N#1
DIFFCCLKT0
J45
1
LOCK PIN
TEST CLOCK
R8 0
2
1
DIFFCCLKC0
N#3
VDDO3
R10 0
2
1
XOUT
50 ohm SE
CK_EXT3
C5 0.1uF
12
R9 0
2
1
PLACE C4, C5, C6, R11 AND R12
NEAR U1 DIFF INPUT PINS
SDA
CK_EXC3
BSS
CK_EXT2
R1
50
21
CK_EXT[3..0]
C1
DNI_0.010uF
1 2
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Figure 14. RC32504A Evaluation Board Schematics – Page 2
Figure 15. RC32504A Evaluation Board Schematics – Page 3
CK_EXT[3..0]
C13 0.1uF
12
MATCHED LENGTH
SINGLE ENDED
STRIPLINE
50 OHM TRACES
J41
1
R72 50
2
1
CK_EXT1
R71 50
2
1
J38
2
1
CLK1 CLK0
BUF_Q2
VDDFO
CLK0T_DC
C101 4700pF
12
TERMINATION BIAS
OUT2
C16 0.1uF
12
FB7 2
1
FB3 2
1
R16 50
2
1
Voltage
Reference
Voltage
Reference
f Ref
VDD
VDD
U12
8P34S1208I
1
GND_1
Q7
2
NQ7
3
SEL
4
CLK1
5
NCLK1
6
VREF1
7
Q1
16
NQ1
17
Q2
18
NQ2
19
Q3
20
NQ3
21
Q4
22
NQ4
23
Q5
24
NQ5
25
Q6
26
NQ6
27
28
VDD_28
8
VDD_8
CLK0
9
NCLK0
10
VREF0
11
Q0
12
NQ0
13
14
GND_14
15
VDD_15
EP
EP
R59 0.00
2
1
C20 0.1uF
12
FB8 2
1
J48
3
2
1
J36
2
1
J39
2
1
CK_EXT2
TERMINATION BIAS
OUT3
CLK1T
C93 4700pF
12
BUF_CLK1
BUF_OUT_T
CLK3C
CK_EXT3
CLK1_AC
R64 100
2
1
Buf_Q2_OUT
R61 0.00
2
1
TBIAS0
VDDFO
BUF_NCLK1
C22 4700pF
12
CLK1C
R17 50
2
1
C21 0.1uF
12
R73
100
21
Buf_NCLK1_IN
Buffer
Input Select
FB4 2
1
FB1 2
1
CK_EXC2
R65 100
2
1
BUF_VREF
CK_EXC3
CLK3T
CLK0C_DC
CK_EXT0
BUF_CLK0
R21 50
2
1
J42
1
CLK2C
Buf_NQ2_OUT
C12 0.1uF
12
CK_EXC[3..0]
OVERLAP R59 PIN1
AND R60 PIN 1
R18 50
2
1
BUF_OUT_C
CK_EXC1
J47 1
R66 100
2
1
FB5 2
1
R22 50
2
1
SEL_JMP
J4
1
TBIAS3
FB6 2
1
C100
0.1uF
1
2
C102 4700pF
12
OVERLAP R58 PIN1
AND R61 PIN 1
CK_EXC[3:0]
J6
1
J7
1
C92 4700pF
12
J9
1
J10
1
J12
1
J13
1
J15
1
C7, C10, C11, C14, C15
C18, C19 and C22 are
U2J dielectric capacitors.
R67 100
2
1
C17 0.1uF
12
BUF_NCLK0
C19 4700pF
12
TBIAS2
C18 4700pF
12
CLK2T
C8 0.1uF
12
R60 0.00
2
1
BUF_NQ2
R68 100
2
1
C15 4700pF
12
NCLK1_AC
J37
2
1
FB2 2
1
FLOAT=CLK0
TERMINATION BIAS
OUT1
Buf_CLK1_IN
C14 4700pF
12
R15 50
2
1
J46 1
C11 4700pF
12
R69 100
2
1
CK_EXT[3:0]
C10 4700pF
12
R62
100
2
1
R19 50
2
1
TERMINATION BIAS
OUT0
CLK0C
R70 100
2
1
BUF_SEL
R20 50
2
1
C7 4700pF
12
R58 0.00
2
1
C9 0.1uF
12
TBIAS1
CK_EXC0
CLK0T
C35
4.7uF
1 2
FB12
21
PG_1V8
VDD_J
1.8V
C87
0.1uF
12
C36
0.1uF
1
2
V1
C91
0.1uF
12
C32
0.1uF
12
D2
LED Green
A
K
VDD_J
GND_J1
1
R53
27.0K
21
EN_3V3
C31
10uF
12
VDD_J
J29
Standof f 20mm
C26
10uF
12
1.8V
R55
10.0K
21
FB17
600
2
1
C76
0.1uF
12
FB15
21 C39
10uF
1 2
C42
0.1uF
12
C25
0.1uF
12
C29
4.7uF
1 2
VDD_J
VDD_J
V5
1.8V
J27
Standof f 20mm
C85
1uF
1
2
CS_1V8
VDDO3
R54
10.0K
21
R26
220
0603
2
1
1.8V
VDD_USB
R25
1
2
1
VDD_J
C81
4700pF
12
C74
0.1uF
12
FB11
2
1
VDDFO
1.8V
C47
10uF
1 2
USB_5VIN
FB_1V8
PG_3V3
C73
0.1uF
12
GND_J
J49 1
34
2
J25
Headerstrip 2X3
4
1 2
3
65
VDD_J
C27
0.1uF
12
USB_5VIN
FB14
21
VDDA
V9
C90
10uF
1 2
J24
Standof f 20mm
EN_1V8
V2
J28
Standof f 20mm
J17 1
3
4
2
C40
0.1uF
12
R24
1
2
1
3.3V
J19 1
3
4
2V8
C75
0.1uF
12
3.3V
C37
10uF
1 2
C82
4700pF
12
VDDO1
C88
1uF
1
2
FB10
21
J20 1
34
2
C84
4700pF
12
C44
10uF
1 2
VDD_USB
FB9
21
C23
10uF
1 2
VDD_J
FID2
Fiducial
U10
RAA214020
VIN_1
1
VIN_2
2
EN
3
PG
4
GND_5
5FB 6
CSET 7
GND_8 8
VOUT_9 9
VOUT_10 10
EP
EP
U11
RAA214020
VIN_1
1
VIN_2
2
EN
3
PG
4
GND_5
5FB 6
CSET 7
GND_8 8
VOUT_9 9
VOUT_10 10
EP
EP
C86
0.1uF
1
2
CS_3V3
C24
10uF
12
V7
J21
Banana Red
2 1
C77
0.1uF
1
2
VDDXO
C46
10uF
1 2
VDDREF
VDDD
VDDO0
R56
10.0K
21
C83
4700pF
12
C33
10uF
1 2
R50
10.0K
21
FB18
600
21
J26 1
34
2
R23 1
2
1
VDD_J
3.3V
One 0.1uF capacitor near each
VDD pin on fanout buffer U12.
1.8V
GND_J4
1
J18 1
34
2V4
C38
0.1uF
12
C43
10uF
0603
6.3V
12
VBUS R51
10.0K
21
VBUS
1.8V
FID1
Fiducial
R52
10.0K
21
R48 1
2
1
1.8V
C89
0.1uF
12
FID3
Fiducial
FB16
21
J22 1
34
2
C99
0.1uF
12
C79
0.1uF
12
GND_J3
1
VDD_J
C81, C82, C83 and C84
are U2J dielectric capacitors.
V3
FB13
21
C34
10uF
1 2
R57
10.0K
21
V5
J23 1
34
2
C28
10uF
1 2
J16
Banana Black
2 1
VDDO2
1.8V FB21
21
C41
10uF
1 2
V6
C30
0.1uF
1
2
C80
0.1uF
12
VBUS 1.8V
C78
0.1uF
1
2
1.8V
FB_3V3
GND_J2
1
C98
0.1uF
12
RC32504A / RC22504A Evaluation Board Manual
R31UH0001EU0100 Rev.1.0
Apr 21, 2021
Page 17
Figure 16. RC32504A Evaluation Board Schematics – Page 4
2.2 Bill of Materials
Item
Qty
Reference
Value
Part Number
Manufacturer
1 1 C1 DNI_0.010uF GRM155R71E103J
2
2
C2,C3
DNI_C0402
DNI_C0402
3 46
C4,C5,C6,C8,C9,C12,C13,C16,C17,C
20,C21,C25,C27,C30,C32,C36,C38,C4
0,C42,C50,C52,C55,C56,C57,C58,C59
,C61,C62,C66,C67,C68,C73,C74,C75,
C76,C77,C78,C79,C80,C86,C87,C89,
C91,C98,C99,C100
0.1uF GRM155R71C104KA88D Murata Electronics
4 16
C7,C10,C11,C14,C15,C18,C19,C22,C
81,C82,C83,C84,C92,C93,C101,C102 4700pF GRM1557U1A472JA01D Murata Electronics
5 18 C23,C24,C26,C28,C31,C33,C34,C37,
C39,C41,C43,C44,C46,C47,C51,C53,
C54,C90 10uF GRM188D70J106MA73D Murata Electronics
6
2
C29,C35
4.7uF
ZRB15XR61A475ME01
7 1 C60 DNI_47pF GRM1555C1E470J Murata Electronics
8
1
C63
47pF
GRM1555C1E470J
Murata Electronics
9 2 C64,C65 27pF GRM1555C1E270J Murata Electronics
CS
FTDI_REF
R47 DNI_0
21
VPHY
C68 0.1uF
1
2
FTDI_OSCO
FTDI_CS2
SDA
OE_PD
R42
4.70K
2
1
J32
Headerstrip 2X3
4
12
3
6
5
C51
10uF
12
FLOAT=NO LATCH
C67 0.1uF
1
2
R32
4.70K
2
1
OE/nCS pin
J33
Headerstrip 2X3
4
1 2
3
65
FTDI Controls
I2C/SPI
USB_DM
J30
Headerstrip 2X3
4
1 2
3
6
5
C65 27pF
12
VDD_USB
J35
3
2
1
SPI
C50
0.1uF
12
PCA_SDA_A
0.1uF near pins 39 , 12 , 24 , 46
VBUS
C55
0.1uF
12
1
3
5
U8
PCA9517
VSSOP8
VCCA
1
SCLA
2
SDAA
3
GND
4EN 5
SDAB 6
SCLB 7
VCCB 8
R43 10.0K
21
R31
4.70K
2
1
PCA_SCL_B
C52
0.1uF
12
J34
3
2
1
FTDI_SDA
FTDI_CS
BUS TYPE
VDD_USB
PCA_SDA_B
FB19 600
2
1VPLL
PCA_SCL_B
3V3_FTDI
R40
12.0K
21
R33
10.0K
21
V5
VCCA
C58
0.1uF
12
FTDI_RESET
FTDI_SCL
FTDI_SCL2
U6
FT232HQ
QFN48
OSCI
1OSCO
2
REF
5
DM
6DP
7
RESET#
34
VCCA
37 VCCCORE
38
VCCD
39 VREGIN
40
TEST
42
EEDATA
43 EECLK
44 EECS
45
ADBUS 0 13
ADBUS 1 14
ADBUS 2 15
ADBUS 3 16
ADBUS 4 17
ADBUS 5 18
ADBUS 6 19
ADBUS 7 20
ACBUS 0 21
ACBUS 1 25
ACBUS 2 26
ACBUS 3 27
ACBUS 4 28
ACBUS 5 29
ACBUS 6 30
ACBUS 7 31
ACBUS 8 32
ACBUS 9 33
VPHY
3VPLL
8
VCCIO_12
12 VCCIO_24
24 VCCIO_46
46
AGND_4 4
AGND_9 9
GND_10 10
GND_11 11
GND_22 22
GND_23 23
GND_35 35
GND_36 36
AGND_41 41
GND_47 47
GND_48 48
EP
EP
V5
PCA_SDA_B
BUS
SOURCE
VDDCORE
POS1=LATCH HI
FTDI_SCL2
Assemble R44 and R47
when not assembling U9.
3V3_FTDI
Configuration Latching
SDA
VPHY
R37 10
2
1
SCL
R34 10
2
1
3V3_FTDI
C56
0.1uF
1
2
PCA_SCL_A
C66 0.1uF
12
LOCKPIN
C57
0.1uF
12
Aardvark Connector
on pins 3, 4 and 6
for I2C control.
R39
10.0K
21
POS1=LATCH HI
R46
10.0K
21
C64 27pF
12
C54
10uF
12
POS2=LATCH LO
3V3_FTDI
FTDI_SDA
FB20 600
2
1
OE Pull-Up or Latch HI
R41
4.70K
2
1
C53
10uF
1
2
FLOAT=NO LATCH
VBUS
3V3_FTDI
OE_NCS
I2C
LOCK
FTDI_OSCI
R45
10.0K
21
3V3_FTDI
POS2=LATCH LO
VPLL
C63
47pF
12
R35 10
2
1
PU
FTDI_MOSI
SDA
R38 10
2
1
C61 0.1uF
12
OE Pull-Down or Latch LO
CS Override
U7
Crystal 12MHz
SMD_3225-4
G2
2G4 4
S11S3 3
V5
FTDI_MISO
R44 DNI_0
21
PCA_SCL_A
C59 0.1uF
12
3V3_FTDI
PD
Control CS
2
4
6
D3 1N4448HLP
A2
K
1
USB_DP
C60
DNI_47pF
1 2
R36
5.10K
21
C62 0.1uF
12
PCA_SDA_A
OE_PU
J31
USB Type C
Right Angle
GND_A1
A1
TX1+
A2
TX1-
A3
VBUS_A4
A4
CC1
A5
DA+
A6
DA-
A7
SBU1
A8
VBUS_A9
A9
RX2-
A10
RX2+
A11
GND_A12
A12
SHEILD_S1
S1
SHIELD_S4
S4
GND_B1 B1
TX2+ B2
TX2- B3
VBUS_B4 B4
CC2 B5
DB+ B6
DB- B7
SBU2 B8
VBUS_B9 B9
RX1- B10
RX1+ B11
GND_B12 B12
SHEILD_S2 S2
SHEILD_S3 S3
USB_MODE
RC32504A / RC22504A Evaluation Board Manual
R31UH0001EU0100 Rev.1.0
Apr 21, 2021
Page 18
Item
Qty
Reference
Value
Part Number
Manufacturer
10
2
C85,C88
1uF
GCM155C71A105KE38D
Murata Electronics
11 1 C97 0.010uF GRM155R71E103J Murata Electronics
12
2
D1,D2
LED Green
APT3216CGCK
13 1 D3 1N4448HLP 1N4448HLP
14 21
FB1,FB2,FB3,FB4,FB5,FB6,FB7,FB8,
FB9,FB10,FB11,FB12,FB13,FB14,FB1
5,FB16,FB17,FB18,FB19,FB20,FB21 600 BLM18AG601SN1D Murata
15 3 FID1,FID2,FID3 Fiducial Fiducial DNI
16
4
GND_J1,GND_J2,GND_J3,GND_J4
DNI Headerstrip 1X1
DNI 1x1
17 2 J1,J45 SMA_JACK_STR_50 733910070 Molex
18 14
J2,J3,J4,J6,J7,J9,J10,J12,J13,J15,J41,
J42,J46,J47 Cinch_142_0701_851 142_0701_851 Johnson
19 1 J16 Banana Black 571-0100
20 8 J17,J18,J19,J20,J22,J23,J26,J49 Header 2X2
499-10-202-10-
009000
21 1 J21 Banana Red 571-0500
22
4
J24,J27,J28,J29
Standoff 20mm
R30-1612000
23 4 J25,J30,J32,J33 Headerstrip 2X3 10897062 Molex
24
1
J31
USB Type C
12401598E4#2A
Amphenol
25 3 J34,J35,J48 Headerstrip 1X3 22-28-4035 Molex
26
4
J36,J37,J38,J39
Headerstrip 1X2
22-28-4023
Molex
27 11 R1,R15,R16,R17,R18,R19,R20,R21,R
22,R71,R72 50 ERA-2AEB49R9X Panasonic
28
8
R2,R3,R4,R5,R7,R8,R9,R10
0
ERJ-2GE0R00
Panasonic
29 2 R6,R26 220 CRCW0603220RFK Vishay
30
2
R11,R12
DNI_50
ERA-2AEB49R9X
Panasonic
31 2 R13,R14 DNI_R0402 DNI_R0402
32
4
R23,R24,R25,R48
1
RC0402FR-071RL
Yageo
33 5 R31,R32,R41,R42,R63 4.70K CRCW04024K70FK Vishay
34 12
R33,R39,R43,R45,R46,R50,R51,R52,
R54,R55,R56,R57 10.0K RCG040210K0FK Yageo
35 4 R34,R35,R37,R38 10 RC0402FR-0710RL Yageo
36
1
R36
5.10K
CRCW04025K10FK
Vishay
37 1 R40 12.0K CRCW040212K0FK Vishay
RC32504A / RC22504A Evaluation Board Manual
R31UH0001EU0100 Rev.1.0
Apr 21, 2021
Page 19
Item
Qty
Reference
Value
Part Number
Manufacturer
38
2
R44,R47
DNI_0
ERJ-2GE0R00
Panasonic
39 1 R53 27.0K CRCW040227K0FK Vishay
40
2
R58,R59
DNI_0.00
ERJ-2GE0R00
Panasonic
41 2 R60,R61 0 ERJ-2GE0R00 Panasonic
42 9
R62,R64,R65,R66,R67,R68,R69,R70,
R73 100 CRCW0402100RFK Vishay
43 1 U2 RC32504A RC32504A Renesas
44
1
U3
BSS138
BSS138
On Semi
45 1 U6 FT232HQ FT232HQ-REEL FTDI
46 1 U7 Crystal 12MHz
ABM8G-12.000MHZ-
18-D2Y-T Abracon
47 1 U8 PCA9517 PCA9517 Texas Instruments
48
1
U9
Crystal 50MHz
EXS00A-CG03550
NDK America
49 2 U10,U11 RAA214020 RAA214020 Renesas
50
1
U12
8P34S1208I
8P34S1208I
Renesas
3. Ordering Information
Part Number
Description
RC32504A-EVK
RC32504A / RC22504A Evaluation Board; A-male to USB-C cable.
4. Revision History
Revision
Date
Description
1.0
Apr 21, 2021
Initial release.
Corporate Headquarters
TOYOSU FORESIA, 3-2-24 Toyosu,
Koto-ku, Tokyo 135-0061, Japan
www.renesas.com
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Renesas RC32504A User manual

RC32504A
Renesas
Brand
Renesas
Model
RC32504A
Type
User manual

Renesas RC32504A is a Clock Generator that provides best-in-class performance with four output pairs programmable to CMOS, LVDS, or HCSL styles. It supports Jitter Attenuator and Synthesizer functionality for the RC32504A and only Synthesizer functionality for the RC22504A. Easily configure and program frequencies using Renesas' RICBox™ Software via USB connection and upload to the evaluation board. The combination evaluation with Renesas Low Noise power supply regulators and Renesas Low Noise fan-out buffer enables direct connection of clock output pairs to test equipment through coax cables.

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