2
MachXO Standard Evaluation Board
Lattice Semiconductor Revisions 001 & 002 User’s Guide
Introduction
The MachXO Standard Evaluation board provides a convenient platform to evaluate electrical characteristics of the
MachXO device, and to evaluate, test and de-bug custom logic designs. The board features a MachXO device in a
256-ball fpBGA package. The MachXO I/Os are connected to a rich variety of interfaces, including an 8-bit input
switch, LEDs, PCB test points, 0.10” general purpose headers and optional high-speed SMA connectors. The
board includes selectable power for mixed core I/O voltage operation. A 33MHz oscillator, as well as an ispClock™
PLL synthesis device are also included on the board.
Features
• MachXO in 256-ball fine pitch Ball Grid Array package (MachXO640 or MachXO2280)
• Single printed circuit board solution
• Eight LEDs for visual feedback
• 8-bit input switch
• General purpose push-button
• 1149.1 JTAG programming/boundary-scan interface
• Built-in power supply operating with an DC input between 5V and 20V
• Selectable CORE voltage for the MachXO
• Selectable voltages for a portion of the I/O banks
• Built-in adjustable oscillator for reference clocking source
• Lattice ispClock5610 multiple output PLL
• SMA connector landing pads (SMA connectors not populated) to MachXO clock input/general purpose I/O pins
• RJ-45 connector (not populated)
• LCD/GPIO footprint
• 100mil center-center test point grid
• Impedance controlled Mictor (not populated)
General Description
The heart of the board is the MachXO programmable logic device in a 256-ball fpBGA package. The board is
designed to cover a broad range of core and I/O voltage requirements. The MachXO “C” grade devices require a
core voltage supply between 1.5V to 3.3V and an auxiliary 3.3V supply. The “E” grade devices require a core volt-
age supply at 1.2V and an auxiliary I/O supply at 3.3V. The MachXO Standard Evaluation Board provides three
supply voltages, all sourced from a 5V to 20V external source (or sourced individually via the banana jack inputs).
The board provides fixed 1.2V and 3.3V power rails and a single adjustable voltage that ranges from 1.2V to 3.3V.
It is possible to use external power supplies to override the fixed output levels if desired. The voltage supplied to the
MachXO core is selectable. The core voltage is changed by moving a single current sense resistor.
Once a correct set of supply voltages has been applied to the MachXO, the device can be programmed. The
MachXO can be programmed and verified with a Lattice JTAG download cable, which should be connected to the
1x10 SIP header on the board (1149.1 JTAG interface). The ispVM
®
System software controls the programming
and verification process. The ispVM System software is available for download from www.latticesemi.com/software.
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MachXO Standard Evaluation Board
Lattice Semiconductor Revisions 001 & 002 User’s Guide
The evaluation board also includes a Lattice ispClock5610. This part is also programmed using the same JTAG
interface. The ispClock5610 can be used to generate synthesized clock inputs to the MachXO device.
The evaluation board includes additional components to aid in evaluating the MachXO PLD. These are described in
the following sections in more detail.
Additional Resources
Additional resources related to this board can be downloaded from the web at www.latticesemi.com/boards. Click
on the appropriate evaluation board, then see the blue “Resources” box on the right of the screen for items such as:
updated documentation, downloadable software, sample designs and more.
Getting Started
In order to use the MachXO Standard Evaluation Board, it must first be powered. Follow the guidelines in the
Power Supply section below for details.
The MachXO Standard Evaluation Board is shipped from the factory pre-configured with a sample program loaded
in both the MachXO and ispClock devices. The source code and programming files are available for download from
the Lattice web site at: www.latticesemi.com/boards. The sample programs operate as follows.
MachXO: Setting all of the 8-bit input switches to ON causes the associated LEDs to count in one direction (8-bit
binary counter). Setting all of the 8-bit input switches to OFF reverses the direction of the count. If the switches are
not all ON or all OFF, the LEDs for the switches that are ON will light up. Additionally, other I/Os on the MachXO
device are also toggled using the internal counter outputs. See the source code and preference file available on-
line for more information.
ispClock5610: The ispClock5610 sample program generates a 33MHz clock input to the MachXO device.
To reprogram the board, you will need the following items:
•
ispLEVER Software:
HDL design support for the MachXO device is included in both ispLEVER 5.0 SP1 and
downloadable ispLEVER-Starter 5.0 SP1 (or later) software tools
•
ispVM System:
This is the Lattice programming management tool which is used to download custom ispLEVER
designs from your PC to the MachXO device via an ispDOWNLOAD
®
cable. The ispVM System software is avail-
able for download from the Lattice web site at: www.latticesemi.com/ispvm.
•
ispDOWNLOAD Cable:
An ispDOWNLOAD Cable is required to connect your PC to the MachXO Standard
Evaluation Board. ispDOWNLOAD Cables are available for purchase separately from the Lattice on-line store
(www.latticesemi.com/store) or any Lattice distributor. For more information see:
www.latticesemi.com/products/devtools/hardware/ispdownload/
MachXO Standard Evaluation Board Functional Description
The MachXO Standard Evaluation Board is comprised of several primary functional blocks as shown in Figure 1. In
the descriptions below, locations of components and board features are described relative to a compass symbol
placed adjacent to the Lattice Semiconductor logo. For example, the DIP oscillator is on the southwest corner of
the board, and the Lattice logo is on the northeast corner of the board.
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MachXO Standard Evaluation Board
Lattice Semiconductor Revisions 001 & 002 User’s Guide
Figure 1. MachXO Standard Evaluation Board
Power Supply
The MachXO Standard Evaluation Board includes two locations to apply power. On the east side of the board are a
pair of banana jacks (JP28 and JP29) and a coaxial DC connector (JP30), which receive power from either a bench
power supply or a brick style power supply. A DC source between 5.0V and 28.0V must be applied in order to
power the board. The coaxial DC connector uses a 2.5mm central pin, with a 6.3mm outer diameter barrel.
The output from the DC system is controlled by switch S5. Switch S5 is in the southeast corner of the board. This is
a small surface mount switch that enables and disables the LTC1775 DC-DC conversion chip. The output voltages
from the power supply are enabled when the switch is in the “on” position.
The 5.0V to 28.0V DC input voltage is converted by DC-DC converters and switching power supplies to provide
3.3V, 1.2V, and an adjustable DC source on the board. The output from these supplies travels through surface
mounted fuse holders. Fuses are supplied and prevent over-current conditions from damaging the components on
the board (Vendor: Littlefuse, Make: Nano SMF Very Fast Acting, 1.5A or 3A).
Due west of the fuse blocks are more banana plug connectors. These connectors provide an alternate means for
applying DC voltage levels to the board. To apply voltages not supplied by the on-board power section,
first
remove the appropriate fuse from the fuse holder
. Then connect an alternate DC supply to the banana plug
connector associated with that fuse.
Table 1. Power Supply Fuses
Fuse Number
Supply Rail
Enabled/Disabled
Banana Connector
Input
F1 V
ADJ
JP25
F2 1.2V JP26
F3 3.3V JP27
RJ-45
Connector
Area
SMA
Connector
Area
ispClock5610
DIP Oscillator
8-Bit Input
Switch
Push-Button
Switches
Prototype
Areas
LCD Display
Area
DC Power
Input Jack
Power
Inputs North
South
EastWest
Prototype
Area
JTAG Programming
Interface
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MachXO Standard Evaluation Board
Lattice Semiconductor Revisions 001 & 002 User’s Guide
Adjacent to JP25-27 are current sense resistors. These permit the measurement of the current flowing from each
of the power supplies. A single resistor can be moved to permit 1.2V, 3.3V, or V
ADJ
to supply V
CORE
to the MachXO.
Table 2. MachXO Core Voltage Selection
The remaining current sense resistors permit the measurement of the V
CCIO
current draw.
Table 3. MachXO I/O Voltage Rails
Four V
CCIO
banks are available on the MachXO Standard Evaluation board. Three of the four I/O banks can be
selected. V
CCIO2
is always powered at 3.3V. This forces the JTAG interface to run at 3.3V. V
CCIO0
, V
CCIO1
, and
V
CCIO3
can be altered using jumpers.
Table 4. MachXO I/O Voltage Selection
Figure 2. MachXO Standard Evaluation Board
Programmability
The programming interface for the MachXO (and ispClock5610) is located in the northwest corner of the board.
The 1x10 header, JP7, is the connection point for the JTAG download cable. Jumpers JP6 and JP8 determine how
the TDI/TDO chain and TMS pins behave.
Important Note:
The board must be un-powered when connecting, disconnecting, or reconnecting the ispDOWN-
LOAD Cable. Always connect the ispDOWNLOAD Cable's GND pin (black wire), before connecting any other JTAG
pins. Failure to follow these procedures can in result in damage to the MachXO device and render the board inop-
erable.
Resistor
Voltage Supplied
to the MachXO Core
R141 V
ADJ
R142 1.2V
R144 3.3V
Resistor I/O Bank Voltage
R143 1.2V
R145 3.3V
R148 V
ADJ
Jumper Block V
CCIO
Controlled
JP20
1-2: V
CCIO1
= 3.3V
3-4: V
CCIO1
= V
ADJ
5-6: V
CCIO1
= 1.2V
JP21
1-2: V
CCIO0
= 3.3V
3-4: V
CCIO0
= V
ADJ
5-6: V
CCIO0
= 1.2V
JP22
1-2: V
CCIO3
= 3.3V
3-4: V
CCIO3
= V
ADJ
5-6: V
CCIO3
= 1.2V
Pin 1
Pin 6
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MachXO Standard Evaluation Board
Lattice Semiconductor Revisions 001 & 002 User’s Guide
The default configuration for jumper JP6 is to configure the TDI from JP7 to be routed to the MachXO first. The
TDO from the MachXO is routed to the ispClock device. TDO from the ispClock is connected to the JTAG header
JP7. However Figure 3 shows the board can be configured to only have the MachXO accessible by the JTAG
header. It can also be configured to only have the ispClock accessible by the JTAG header.
Jumper JP8 controls the TMS routing to the MachXO and the ispClock. The default configuration connects TMS to
both the MachXO and the ispClock. When the MachXO is the only device in the JTAG chain, the ispClock TMS is
pulled high, causing it to always go into Test-Logic-Reset mode. The MachXO has its TMS pin pulled high when the
ispClock is the only device in the JTAG chain.
Figure 3. Programming Interface
Push Buttons and Status LEDs
There are three push-buttons and three LEDs in the south portion of the MachXO Standard Evaluation Board.
Switch S2, the westernmost, asserts the Global Set/Reset input on the MachXO. When the button is pressed, LED
D9 (red), illuminates. This gives clear visual evidence the GSR input has toggled. In order for the GSR to operate, it
is necessary to instantiate the GSR macro in the VHDL/Verilog HDL source.
Immediately adjacent to the MachXO reset switch is the ispClock reset switch (S3). Pressing this button asserts
RESET to the ispClock chip.
Finally, there is a general use push-button (S4). S4 is routed to T11 on the MachXO device. It is normally pulled
high, and when pressed is asserted to ground. When pressed, LED D10 (yellow) illuminates.
Adjacent, westward, to S2 is diode D11 (green). This is a LED tied to a general purpose I/O on the MachXO. This
LED signals that the MachXO is done being programmed. However, it can be used to signal any status desired.
Evaluation bitstreams will tie output pin T6 to drive low, turning D11 on.
Global Output Enable
The MachXO device features a global output enable control. The GOE is routed to JP18, and the factory default
setting on JP18 is to enable the MachXO outputs. The jumper on JP18 can be moved from the default setting to
disable (tri-state) all of the MachXO I/Os.
Table 5. Global Output Enable
MachXO and Support Interfaces
The MachXO Standard Evaluation Board includes basic support features for evaluating the performance and func-
tionality of the MachXO device. This includes a prototyping area permitting arbitrary logic functions to be placed on
Jumper Block JP18Output Enable State
1-2 Outputs disabled (tri-state)
2-3 Outputs enabled
JTAG
Pin 1
TDI
Jumpers
MachXO
and
ispClock
MachXO
Only
ispClock
Only TDI
Route
TMS
Route
TMS
Jumpers
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MachXO Standard Evaluation Board
Lattice Semiconductor Revisions 001 & 002 User’s Guide
board. There are also locations to insert connectors and resistors. These connections are useful for performing I/O
characterization.
The silk screen markings on the evaluation board are designed to make it easy to locate resources on the board
and related connections to the MachXO.
• Parts are numbered in a consistent fashion. Each part starts at reference designator ‘1’ in the northwest corner
of the board (i.e. R1, C1, U1, L1…). The component number increases by one in a columnar fashion (i.e. south-
ward). When the south edge of the board is reached, the count resumes slightly east, and at the north side of the
board. Thus the highest numbered components will always be in the southeast corner of the board. This same
numbering sequence is applied to the reverse side of the evaluation board.
• The alphanumeric pin position of the MachXO 256-ball fpBGA is indicated adjacent to most of the switch inputs,
LED outputs, SMA connectors, and test points on the board. For example, the designator (F3) is located next to
the SMA connector JP2. Thus MachXO pin F3 is connected to the center post of JP2.
• A solid white rectangle area near the SMA connectors denotes the positive side of a matched pair. The negative
side of the matched pair has a white outline rectangle area.
Prototype Grids
The board includes five 100-mil center-center prototype grid areas consisting of plated through holes with various
connections.
It is important to note the board conventions used to identify the through hole types:
• Any through hole with a square-shaped plated area is not connected to any device on the board, and provided
for your convenience.
• Any round through-hole outlined with a thin white silkscreen rectangle is connected to ground.
• All other round through-holes are connected to the MachXO pin as indicated by the silkscreen.
Note: Some prototype grid test points may be connected to “no-connect” (NC) pin locations on the MachXO device.
Consult the MachXO device datasheet for further details regarding the MachXO pinout.
Prototype Grid 1 and 2:
Grid 1 is located in the northwest portion of the board. Grid 2 is due south of the MachXO
device. Both areas have an alphanumeric grid located in the silkscreen indicating which plated through hole is
attached to which MachXO pin.
Both grids are intermixed with through holes attached to the ground plane. These ground holes are marked with a
white silkscreened rectangle.
Both grids are also intermixed with unconnected locations. These are indicated with a square-shaped plated area.
For example, starting in the upper-left of Grid 1; location A2 and A3 are unconnected, location A4 is connected to
the MachXO I/O pin A4, etc.
Both grids also have a series of pull-up/pull-down/inline resistors connected to the through holes. Figure 4 shows
how these resistors may be arrayed around the prototype area.
(M12)
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MachXO Standard Evaluation Board
Lattice Semiconductor Revisions 001 & 002 User’s Guide
Figure 4. Prototype Grid 1 and 2 Resistor Pad Configuration
The resistor pads are 0603 surface mount form factor. The 0603 resistor in the center has a short-circuit trace
between the resistor pads. This permits the signal to be driven to the prototype area without the addition of a SMT
zero ohm resistor. If a series resistor with a non-zero value is needed, this short-circuit trace can be removed.
The pull-up resistors within this grid can be configured to be pulled to one of the three available voltage rails on the
board. Table 6 shows how the voltage rails are assigned. Refer to the schematic to determine which resistor pads
connect to which MachXO I/O. The schematic also indicates which jumper block controls the pull-up voltage on
each resistor. The schematic is included in Appendix A.
Table 6. Pull-up Voltage Selection
Prototype Grid 3:
Just west (left) of the MachXO is a small array of nine test points. The MachXO I/O pin connec-
tions are indicated in the silkscreen marking. For example, the top-left location connects to MachXO pin F5, etc.
These test points are directly connected to the MachXO without any series resistors, and do not have any pull-
up/pull-down resistors attached.
Prototype Grid 4:
This grid is located in the south-east part of the board. This grid consists primarily of uncon-
nected, square-plated through holes. The south edge of this grid has a row of through holes connected to ground.
The north edge has a small quantity of through holes connected to the MachXO.
Figure 5 indicates how these test points are connected to the MachXO 256 fpBGA. The LVDS paired test points
connect to a set of 0603 form factor resistors. These resistors permit series and parallel style terminations to be
applied to the MachXO I/O. Note that some of these I/Os may be no-connects on the MachXO device depending
on which MachXO device is populated on the board. Review the schematic and MachXO Family Data Sheet to
determine which are available for use.
Jumper Block Pull-up Voltage
JP10
1-2: 1.2V
3-4: V
ADJ
5-6: 3.3V
JP19
1-2: 1.2V
3-4: V
ADJ
5-6: 3.3V
Pull-up
From MachXO
Pull-down
Short circuit
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MachXO Standard Evaluation Board
Lattice Semiconductor Revisions 001 & 002 User’s Guide
Figure 5. Prototype Grid 4
Prototype Grid 5
: The last of the prototype grid is designed for use with an LCD display. U3 can be populated by a
Lumex LCD-S501C39TR five-element, seven-segement LCD display. When this display is populated, it is mounted
on the rows between U3 and JP23/JP24. JP23 and JP24 can then be populated with general-purpose headers.
Jumpers can then be used to control connections between the MachXO device pins and the LCD.
When this LCD is not populated (default condition), the outer columns of JP23 and JP24 can be used as general-
purpose I/O test points.
LVDS Paired
Direct to
MachXO
Short-circuit
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MachXO Standard Evaluation Board
Lattice Semiconductor Revisions 001 & 002 User’s Guide
LED Displays
On the south edge of the board is a set of eight green 0603 form factor LEDs. These LEDs are connected to I/O
pins dedicated to driving the LEDs. Table 7 shows which MachXO I/O controls each LED. The LEDs illuminate
when the corresponding I/O is driven to V
OL
.
Table 7. LED Pin Assignments
Switches
The evaluation board includes an eight-bit input toggle switch at the south edge of the board. The MachXO I/O
location for each bit in the switch is indicated on the PCB silkscreen. When in the up position, the switch is pulled to
3.3V via a 10K resistor. When in the down position, the switch is tied to ground.
Table 8. Switch Assignments
Oscillator and Clock Inputs
The MachXO Standard Evaluation Board provides the ability to supply selectable reference frequencies to the
MachXO device. The board provides a unique clock source distribution method. A Lattice ispClock5610 is included
on the board to provide a number of different clock frequencies to the MachXO device.
The ispClock5610 receives a reference clock from one of two sources on the board. The primary clock source for
the ispClock5610 is the on-board DIP oscillator. In the southwest corner of the board is XU1. This is a socket for
installing 300mil wide 3.3V DIP oscillators. Figure 7 shows how each type of oscillator can be placed in the DIP
socket.
LED MachXO I/O
D0 R11
D1 R12
D2 P11
D3 P12
D4 T13
D5 T12
D6 R13
D7 R14
Switch MachXO I/O
1T3
2 R4
3 R5
4 P5
5 P6
6 T4
7 T5
8 R6
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MachXO Standard Evaluation Board
Lattice Semiconductor Revisions 001 & 002 User’s Guide
Figure 6. Oscillator Positions
Note: XU2 pin 9 is routed to one of the two PLLs included on larger MachXO devices. These MachXO PLLs are not
available on the MachXO640 device. XU2 pin 9 provides input to the PLL_T input pin M5.
JP2 and JP3 are routed to the second set of PLL input pins on the MachXO device. On the MachXO640, these
input pins are general purpose I/O. For larger MachXO devices, these same I/O pins are combination general pur-
pose I/O and PLL inputs. The traces from JP2/JP3 are 50 ohm impedance, and have the same resistor pad struc-
ture described in Figure 6. JP2/JP3 provide the ability to insert differential clock sources. Review the schematic for
the exact part reference numbers of the resistors.
The second way to provide a clock to the ispClock5610 is to use JP4 and JP5 SMA connectors. These SMA con-
nectors are not installed by default. Also, by default the positive input from JP4 is disconnected from the
ispClock5610. Beneath the ispClock5610 on the reverse side of the board are two resistor sites: R158 and R159.
R158 connects XU2 pin 10 to the ispClock5610 positive clock input. R159 connects JP4 to the ispClock positive
clock input. By default, R158 has a zero ohm resistor installed and R159 is left empty. This is done to prevent unde-
sirable artifacts from appearing on the input clock due to trace stubs. R158 and R159 are placed in a way to reduce
the length of any stub traces to an absolute minimum. When supplying a clock from JP4/JP5, R158 should be
moved to R159 in order to connect JP4 to the ispClock5610.
Table 9. ispClock5610 Clock Source
Once the clock source to the ispClock device has been defined, the ispClock can be programmed to generate clock
frequencies for the MachXO. The ispClock5610 has five outputs from the internal PLL (0-4). The first four, 0-3, are
applied directly to the MachXO clock input pins. The fifth output is brought out to TP2 and TP3, adjacent to the isp-
Clock chip.
Table 10. Clock Connections
Resistor
ispClock5610
Positive Source
R158 XU2 pin 10
R159 JP4
ispClock5610 Pin MachXO Pin
CLK_OUT0 D7
CLK_OUT1 A9
CLK_OUT2 N9
CLK_OUT3 M9
Full-size
to ispClock
Half-size
to ispClock
Full-size to
MachXO PLL
Half-size to
MachXO PLL
OSC
OSC
OSC
OSC
JP9
Pin 1
1-2: Oscillator enabled
2-3: Oscillator disabled
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MachXO Standard Evaluation Board
Lattice Semiconductor Revisions 001 & 002 User’s Guide
See the ispClock5610 Family Data Sheet and the Lattice PAC-Designer
®
design software for information about pro-
gramming the ispClock. More information and software downloads can be found on the Lattice web site at www.lat-
ticesemi.com/ispclock.
ispClock Configuration
The ispClock5610 has multiple configuration pins. The evaluation board includes a number of headers on the board
allowing these configuration pins to be asserted, deasserted, or controlled from the MachXO. The headers have a
general format as shown in Figure 7.
Figure 7. ispClock Configuration Headers
JP11 - JP17 configure all of the ispClock features. Table 11 shows which jumper block controls which ispClock pin.
Refer to the ispClock5610 Family Data Sheet to understand what function each pin performs.
Table 11. ispClock5610 Clock Source
The ispClock has the ability to be programmed with four separate profiles. The profiles are selected using the
PS1:0 input pins. The ispClock is programmed with a unique personality in profile 0. None of the remaining profiles
provide additional frequencies.
Profile 0 is configured to use the ispClock PLL to generate several output frequencies from the base 33MHz input
frequency. The outputs are:
• Output 0: 4x input
• Output 1: 2x input
• Output 2: 1x input
• Output 3: 0.5x input
• Output 4: 0.25x input
Some applications may not require the ispClock to use the PLL to generate higher frequency clocks. It is possible
to turn the ispClock into a clock buffer chip. This is done by moving the PLL Bypass jumper from the default loca-
tion. The PLL will no longer be included in the clock frequency generation. If Profile 0 is still selected the post PLL
clock dividers will still be active, causing the output frequencies to drop dramatically. If a 1:1 input to output fre-
quency ratio is desired the PS1:0 jumpers can be used to select any profile other than Profile 0.
Jumper Block IspClock Control Factory Default Setting
JP11 PS0 5-6
JP12 PLL Bypass 5-6
JP13 OEx 5-6
JP14 GOE 5-6
JP15 SGATE 1-2
JP16 PS1 5-6
JP17 OEy 5-6
Pin 1
Pull-downPull-upMachXO
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MachXO Standard Evaluation Board
Lattice Semiconductor Revisions 001 & 002 User’s Guide
RJ-45 Connection
The west edge of the board provides a place to insert an RJ-45 connector. This connector is not installed at the fac-
tory. The traces to the RJ-45 connector have the same resistor network scheme as shown in Figure 5, described
above. The traces are 50 ohm impedance, and on larger MachXO devices are connected to true LVDS I/O.
Mictor Header
The left-side I/Os on the MachXO which are not used for the RJ-45 and small prototype test points are routed to a
AMP/Tyco Mictor connector for additional off-board expansion. This connector can be mounted on the bottom side
of the board. The connector is not populated by the manufacturer. Review the schematic for the board to determine
which I/O pins are routed to the Mictor connector.
Ordering Information
Technical Support Assistance
Hotline: 1-800-LATTICE (North America)
+1-503-268-8001 (Outside North America)
e-mail: techsuppor[email protected]
Internet: www.latticesemi.com
© 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as
listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of
their respective holders. The specifications and information herein are subject to change without notice.
Revision History
Description Ordering Part Number
China RoHS Environment-
Friendly Use Period (EFUP)
MachXO 2280C Evaluation Board - Standard LCMXO2280C-L-EV
MachXO 640C Evaluation Board - Standard LCMXO640C-L-EV
ispLEVER Base with MachXO 2280 Standard Development Kit LS-X2280-BASE-PC-N
Date Version Change Summary
June 2006 01.0 Initial release.
September2006 01.1 Updated schematic in Appendix A.
February 2007 01.2 Updated Switch Assignments table.
Updated ispClock Configuration section.
March 2007 01.3 Added Ordering Information section.
April 2007 01.4 Added important information for proper connection of ispDOWNLOAD
(Programming) Cables.
June 2007 01.5 Updated Features bullets and General Description section to indicate
the power supply will operate between 5V and 20V, instead of 5V to
28V.
March 2008 01.6 Changed document title from “MachXO Standard Evaluation Board
Revision 001 User’s Guide” to “MachXO Standard Evaluation Board
Revision 001 & 002 User’s Guide”.
10
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MachXO Standard Evaluation Board
Lattice Semiconductor Revisions 001 & 002 User’s Guide
Appendix A. PCB Schematic
Figure 8. MachXO Control and Programming Interfaces
A
A
B
B
C
C
D
D
E
E
4 4
33
2 2
11
TDO_ CL K
CKIN_POS
CKIN_NEG
TDI_ CLK
VCCIO[3..0]
TMS_ CL K
LOCK#
CKIN_POS
CKIN_NEG CLK_OUT[4..0]
V3.3
GND
PLLIN_POS
PLLIN_NEG
TCK
CK_CTRL[7..0]
TDO_ PL D
PB1
LED[7..0]
RJ45[37..0]
LCD[38..0]
PROTO[99..0]
GSR_n
VAUX
TDI_ PL D
SWITCHES[7..0]
HEADER[33..0]
VCORE
GOE_PLD
TMS_ PL D
DONE_n
VCC_ADJ VCC_1.2V
V3.3
GND
VCC_ADJ VCC_1.2V
Title
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Size Document Number Rev
Date: Sh eet of
<Doc> 0
MachXO Evaluation Board
C
112
Title
Size Document Number Rev
Date: Sh eet of
<Doc> 0
MachXO Evaluation Board
C
112
Page 2
Page 3
Page 4
Page 5
Page 6
Page 7
Page 12
B1
Connectors
TDI_ PL D
TMS_ CL K
TCK
TDO_ PL D
CKIN_POS
CKIN_NEG
PLLIN_POS
PLLIN_NEG
RJ45_IO[7..0]
HEADER[33..0]
TDI_ CLK
TDO_ CL K
TMS_ PL D
GSR_n
GOE_PLD
DONE_n
PB1
B2
Power
VCCIO[3..0]
VCORE
VAUX
B3
MachXO
TDO
TDI
TMS
TCK
CK_CTRL[7..0]
LOCK_n
CLK_IN[4..0]
PROTO[99..0]
VCORE
VAUX
VCCIO[3..0]
PLLIN_NEG
PLLIN_POS
SWITCHES[7..0]
LCD[38..0]
LED[7..0]
HEADER[33..0]
RJ45_IO[7..0]
GOE_PLD
GSR_n
DONE_n
PB1
B4
Prototype_Area
PROTO[99..0]
VCCIO[3..0]
B5
Clock_Control
TDO
TDI
TMS
TCK
CK_CTRL[7..0]
CKIN_POS
CKIN_NEG CLK_OUT[4..0]
LOCK_n
B7
Mechanical
B6
Input_Output
LED[7..0]
SWITCHES[7..0]
LCD[38..0]
15
MachXO Standard Evaluation Board
Lattice Semiconductor Revisions 001 & 002 User’s Guide
Figure 9. MachXO I/O Connections
A
A
B
B
C
C
D
D
E
E
4 4
33
2 2
11
VCCIO0
VCCIO0
VCCIO0
VCCIO0
VCCIO1
VCCIO1
VCCIO1
VCCIO1
VCCIO2
VCCIO2
VCCIO2
VCCIO2
VCCIO3
VCCIO3
VCCIO3
VCCIO3
VCCIO[3..0]
CLK_IN[4..0]
SWITCHES[7..0]
LCD11
LCD27
RJ45_IO[7..0]
PROTO10
HEADER4
HEADER5
HEADER0
HEADER1
PROTO1
PROTO0
PROTO3
PROTO2
PROTO5
PROTO4
PROTO[99..0]
HEADER[33..0]
RJ45_IO6
VCCIO0
VCCIO1
VCCIO2
VCCIO3
RJ45_IO4
RJ45_IO5
RJ45_IO2
RJ45_IO3
RJ45_IO1
RJ45_IO0
PROTO11
PROTO16
PROTO17
PROTO12
PROTO15
PROTO13
PROTO14
HEADER28
HEADER24
HEADER20
HEADER18
PROTO50
HEADER22
LED[7..0]
PROTO88
PROTO87
PROTO85
LCD26
LCD24
LCD25
LCD22
LCD18
LCD16
LCD[38..0]
HEADER26
HEADER27
HEADER17
HEADER3
HEADER2
PROTO6
PROTO7
HEADER6
HEADER14
HEADER10
RJ45_IO7
HEADER29
HEADER15
HEADER12
HEADER11
PROTO49
HEADER16
PROTO55
HEADER30
PROTO52
HEADER7
HEADER8
PROTO56
PROTO46
PROTO57
PROTO54
HEADER31
HEADER32
HEADER13
PROTO48
HEADER9
HEADER33
PROTO47
PROTO53
HEADER25
HEADER23
HEADER19
PROTO51
PROTO45
PROTO86
PROTO93
PROTO94
DONE_n
SWITCHES0
SWITCHES1
SWITCHES2
SWITCHES3
SWITCHES4
SWITCHES7
PROTO92
PROTO89
LCD7
LCD8
LCD9
LCD10
LCD12
LCD13
LCD14
LCD15
LCD17
LCD19
LCD20
LCD21
LCD23
PROTO73
PROTO72
PROTO74
PROTO71
PROTO64
PROTO65
PROTO70
LCD38
LCD37
LCD36
LCD35
LCD34
LCD33
LCD32
LCD31
LCD30
LCD29
LCD28
PROTO61
PROTO60
PROTO59
SWITCHES6
SWITCHES5
PROTO90
PROTO91
PROTO9
PROTO8
CLK_IN2
CK_CTRL3
CK_CTRL4
CLK_IN3
CK_CTRL6
CK_CTRL7
LOCK_n
PROTO76
PROTO75
LED0
LED1
LED2
LED3
LED4
LED5
LED6
LED7
PROTO77
PROTO78
CK_CTRL2
PROTO79
PROTO80
PROTO81
PROTO82
PROTO84
PROTO83
CK_CTRL5
PROTO33
PROTO34
PROTO36
PROTO35
PROTO38
PROTO44
PROTO40
PROTO42
PROTO37
PROTO28
PROTO31
PROTO29
PROTO23
PROTO21
PROTO22
PROTO24
PROTO27
PROTO26
PROTO25
PROTO39
PROTO41
PROTO43
CLK_IN1
PROTO30
PROTO20
PROTO19
CLK_IN0
PROTO18
CK_CTRL0
CK_CTRL1
HEADER21
PROTO69
PROTO63
PROTO62
PROTO68
PROTO67
PROTO66
LCD2
LCD3
LCD4
LCD5
LCD6
LCD1
CLK_IN4
PROTO58
LCD0
PROTO32
CLK_IN[4..0]
PROTO[99..0]
VCORE
VAUX
VCCIO[3..0]
SWITCHES[7..0]
LCD[38..0]
HEADER[33..0]
RJ45_IO[7..0]
PLLIN_NEG
PLLIN_POS
GSR_n
LED[7..0]
GOE_PLD
DONE_n
CK_CTRL[7..0]
LOCK_n
PB1
TDI
TMS
TCK
TDO
GND
GND
VCORE
VAUX
GND
Title
Size Document Number Rev
Date: Sheet of
<Doc> 0
MachXO Evaluation Board
C
212
Title
Size Document Number Rev
Date: Sheet of
<Doc> 0
MachXO Evaluation Board
C
212
Title
Size Document Number Rev
Date: Sheet of
<Doc> 0
MachXO Evaluation Board
C
212
RJ45_IO traces are 50 ohm.
Resistors placed close to U2
Place caps close to VCC pins they serve.
PLLIN traces are 50 ohm.
Resistors placed close to U4
R42
100
CR0603
NoPopulate
R42
100
CR0603
NoPopulate
C43
0.1uF
CC0402
Populate
C43
0.1uF
CC0402
Populate
R41
100
CR0603
NoPopulate
R41
100
CR0603
NoPopulate
XO_640 common VCCIO
VCCJ on VCCIO5
XO_640 common VCCIO
XO_640 common VCCIO
XO_640 common VCCIO
U2E
MachXO_fpBGA256
17mmX17mm
Populate
XO_640 common VCCIO
VCCJ on VCCIO5
XO_640 common VCCIO
XO_640 common VCCIO
XO_640 common VCCIO
U2E
MachXO_fpBGA256
17mmX17mm
Populate
VCCIO0_0
F7
VCCIO0_1
F8
VCCIO1_0
F9
VCCIO1_1
F10
VCCIO2_0
G11
VCCIO2_1
H11
VCCIO3_0
J11
VCCIO3_1
K11
VCCIO4_0
L9
VCCIO4_1
L10
VCCIO5_0
L7
VCCIO5_1
L8
VCCIO6_0
J6
VCCIO6_1
K6
VCCIO7_0
G6
VCCIO7_1
H6
GND_0 A16
GND_1 T16
GND_2 F11
GND_3 H10
GND_4 J10
GND_5 G9
GND_6 H9
GND_7 J9
GND_8 K9
GND_9 G8
GND_10 H8
GND_11 J8
GND_12 K8
GND_13 H7
GND_14 J7
GND_15 L6
GND_16 A1
GND_17 T1
VCC_3 K7
VCC_2 G7
VCC_1 K10
VCC_0 G10
VCCAUX_0
A8
VCCAUX_1
T9
R60
100
CR0603
NoPopulate
R60
100
CR0603
NoPopulate
R63
100
CR0603
NoPopulate
R63
100
CR0603
NoPopulate
C41
0.1uF
CC0402
Populate
C41
0.1uF
CC0402
Populate
4OIC
C
V5
OI
C
CV
I/Os in Bank 5
for XO1200
I/Os in Bank 4
for XO2280
Pin name sequence
PB(640,1200,2280)
U2C
MachXO_fpBGA256
17mmX17mm
Populate
4OIC
C
V5
OI
C
CV
I/Os in Bank 5
for XO1200
I/Os in Bank 4
for XO2280
Pin name sequence
PB(640,1200,2280)
U2C
MachXO_fpBGA256
17mmX17mm
Populate
NC/PB2B/PB2B
P3
NC/PB2D/PB2D
N6 NC/PB2C/PB2C
N5
PB2A/PB3A/PB3A
T2
PB2B/PB3B/PB3B
T3
PB2C/PB3C/PB3C
R4
PB3D/PB4D/PB4D
T4
PB3A/PB4A/PB4A
P5
PB3B/PB4B/PB4B
P6
PB3C/PB4C/PB4C
T5
PB4A/PB5A/PB5A
R6
PB2D/PB3D/PB3D
R5
PB4B/PB5B/PB5B
T6
PB4C/PB5C/PB6A
T8
PB4D/PB5D/PB6B
T7
NC/PB6A/PB7C
M7
NC/PB6B/PB7D
M8
PB4E/PB6C/PB8C
R7
PB4F/PB6D/PB8D
R8
PB5C/PB6E/PB9A
P7
PB5D/PB6F/PB9B
P8
PB5B/PB7B/PB10F/CLK2 N9
PB5A/PB7A/PB10E N8
PB7A/PB7C/PB10C P9
PB7B/PB7D/PB10D P10
PB6B/PB7F/PB10B/CLK3 M9
PB6A/PB7E/PB10A M10
PB6C/PB8A/PB11C R9
PB6D/PB8B/PB11D R10
PB7C/PB8C/PB12A T10
PB7D/PB8D/PB12B T11
NC/PB8E/PB12C N10
NC/PB8F/PB12D N11
PB7E/PB9A/PB13A R11
PB7F/PB9B/PB13B R12
PB8A/PB9C/PB13C P11
PB8B/PB9D/PB13D P12
PB8C/PB9E/PB14A T13
PB8D/PB9F/PB14B T12
PB9A/PB10A/PB14C R13
PB9B/PB10B/PB14D R14
PB9C/PB10C/PB15A T14
PB9D/PB10D/PB15B T15
NC/PB11A/PB16A R15
NC/PB11B/PB16B R16
SLEEPN P13
PB9F/PB10F/PB15D P14
NC/PB11C/PB16C P15
NC/PB11D/PB16D P16
TDI
N7
TDO
M6
TMS
P4
TCK
R3
NC/PB2A/PB2A
P2
C39
10uF
CC0805
Populate
C39
10uF
CC0805
Populate
R57
100
CR0603
NoPopulate
R57
100
CR0603
NoPopulate
C44
10uF
CC0805
Populate
C44
10uF
CC0805
Populate
C16
0.1uF
CC0402
Populate
C16
0.1uF
CC0402
Populate
R61
100
CR0603
NoPopulate
R61
100
CR0603
NoPopulate
C17
10uF
CC0805
Populate
C17
10uF
CC0805
Populate
R45
100
CR0603
NoPopulate
R45
100
CR0603
NoPopulate
C14
0.1uF
CC0402
Populate
C14
0.1uF
CC0402
Populate
C15
10uF
CC0805
Populate
C15
10uF
CC0805
Populate
C21
0.1uF
CC0402
Populate
C21
0.1uF
CC0402
Populate
C20
10uF
CC0805
Populate
C20
10uF
CC0805
Populate
C19
0.1uF
CC0402
Populate
C19
0.1uF
CC0402
Populate
C42
10uF
CC0805
Populate
C42
10uF
CC0805
Populate
C38
0.1uF
CC0402
Populate
C38
0.1uF
CC0402
Populate
C40
0.1uF
CC0402
Populate
C40
0.1uF
CC0402
Populate
1
O
I
C
C
V0O
IC
CV
I/Os in Bank 0
for XO1200
I/Os in Bank 1
for XO2280
Pin name sequence
PT(640,1200,2280)
U2A
MachXO_fpBGA256
17mmX17mm
Populate
1
O
I
C
C
V0O
IC
CV
I/Os in Bank 0
for XO1200
I/Os in Bank 1
for XO2280
Pin name sequence
PT(640,1200,2280)
U2A
MachXO_fpBGA256
17mmX17mm
Populate
NC/PT2A/PT2C
B2
NC/PT2B/PT2D
B3
PT2A/PT3A/PT3A
A2
PT2B/PT3B/PT3B
A3
NC/PT2C/PT3C
D3
NC/PT2D/PT3D
D4
PT2F/PT4B/PT4B
C5 PT2E/PT4A/PT4A
C4
PT2C/PT3C/PT5A
D6
PT2D/PT3D/PT5B
D5
PT3A/PT3E/PT5C
B4
PT3B/PT3F/PT5D
B5
NC/PT4D/PT6F
E6 NC/PT4C/PT6E
E7
PT3F/PT5B/PT6D
A4 PT3E/PT5A/PT6C
A5
PT3C/PT5C/PT6A
C6
PT3D/PT5D/PT6B
C7
PT4A/PT5E/PT7A
B6
PT4B/PT5F/PT7B
B7
PT4C/PT6A/PT7C
A6
PT4D/PT6B/PT7D
A7
PT4E/PT6C/PT8C
B8
PT4F/PT6D/PT8D
C8
PT5B/PT6F/PT9B/CLK0
D7 PT5A/PT6E/PT9A
D8
PT9A/PT7A/PT9C E8
PT9B/PT7B/PT9D E9
PT6B/PT7D/PT10B/CLK1 A9
PT6A/PT7C/PT10A A10
PT6C/PT7E/PT10C C9
PT6D/PT7F/PT10D C10
PT8C/PT8A/PT10E D9
PT8D/PT8B/PT10F D10
PT5C/PT8C/PT11A B9
PT5D/PT8D/PT11B B10
PT7C/PT8E/PT12A A11
PT7D/PT8F/PT12B A12
PT7A/PT9A/PT12C B11
PT7B/PT9B/PT12D B12
PT8A/PT9C/PT13C C11
PT8B/PT9D/PT13D C12
PT7F/PT9F/PT14B A14
PT7E/PT9E/PT14A A13
PT9C/PT10A/PT14C D11
PT9D/PT10B/PT14D D12
NC/PT10C/PT15A E10
NC/PT10D/PT15B E11
PT9E/PT10E/PT15C B13
PT9F/P T10 F/PT15D C13
NC/PT11A/PT16A B14
NC/PT11B/PT16B C14
NC/PT11C/PT16C A15
NC/PT11D/PT16D B15
R56
100
CR0603
NoPopulate
R56
100
CR0603
NoPopulate
R44
100
CR0603
NoPopulate
R44
100
CR0603
NoPopulate
R65
100
CR0603
NoPopulate
R65
100
CR0603
NoPopulate
3OICCV2OICCV
Pin name sequence
PR(640,1200,2280)
U2D
MachXO_fpBGA256
17mmX17mm
Populate
3OICCV2OICCV
Pin name sequence
PR(640,1200,2280)
U2D
MachXO_fpBGA256
17mmX17mm
Populate
NC/PR2A/PR3A/LV_T
D14
NC/PR2B/PR3B/LV_C
D13
NC/PR3A/PR4A/LV_T
E13
NC/PR3B/PR4B/LV_C
E12
NC/PR3C/PR4C
F13
NC/PR3D/PR4D
F12
PR3C/PR4A/PR5A/LV_T
E14
PR3D/PR4B/PR5B/LV_C
F14
PR2A/PR4C/PR5C
B16
PR2B/PR4D/PR5D
C16
PR2C/PR5A/PR6A/LV_T
C15
PR2D/PR5B/PR6B/LV_C
D15
PR3A/PR5C/PR6C
D16
PR3B/PR5D/PR6D
E16
PR4A/PR6A/PR7A/LV_T
E15
PR4B/PR6B/PR7B/LV_C
F15
PR5A/PR6C/PR7C
F16
PR5B/PR6D/PR7D
G16
PR4C/PR7A/PR9A/LV_T
G12
PR4D/PR7B/PR9B/LV_C
G13
PR6C/PR7C/PR9C
H12
PR6D/PR7D/PR9D
H13
PR5C/PR8A/PR10A/LV_T
G14
PR5D/PR8B/PR10B/LV_C
H14
PR6A/PR8C/PR10C
G15
PR6B/PR8D/PR10D
H15
PR7A/PR9A/PR11A/LV_T H16
PR7B/PR9B/PR11B/LV_C J16
NC/PR9C/PR11C J12
NC/PR9D/PR11D K12
PR7C/PR10A/PR13A/LV_T J15
PR7D/PR10B/PR13B/LV_C K15
PR8A/PR10C/PR13C J14
PR8B/PR10D/PR13D K14
PR8C/PR11A/PR14A/LV_T J13
PR8D/PR11B/PR14B/LV_C K13
PR9A/PR11C/PR14C K16
PR9B/PR11D/PR14D L16
PR9C/PR12A/PR15A/LV_T L15
PR9D/PR12B/PR15B/LV_C M15
PR10C/PR12C/PR15C M16
PR10D/PR12D/PR15D N16
PR10A/PR13A/PR16A/LV_T L14
PR10B/PR13B/PR16B/LV_C M14
PR11B/PR13D/PR16D L13
PR11A/PR13C/PR16C L12
PR11C/PR14A/PR17A/LV_T N15
PR11D/PR14B/PR17B/LV_C N14
NC/PR14C/PR17C M12
NC/PR14D/PR17D M13
NC/PR15A/PR18A/LV_T N13
NC/PR15B/PR18B/LV_C N12
NC/PR16A/PR20A L11
NC/PR16B/PR20B M11
R58
100
CR0603
NoPopulate
R58
100
CR0603
NoPopulate
C18
10uF
CC0805
Populate
C18
10uF
CC0805
Populate
R59
100
CR0603
NoPopulate
R59
100
CR0603
NoPopulate
R43
100
CR0603
NoPopulate
R43
100
CR0603
NoPopulate
R62
100
CR0603
NoPopulate
R62
100
CR0603
NoPopulate
6O
I
CC
V
7O
I
CC
V
Pin name sequence
PL(640,1200,2280)
U2B
MachXO_fpBGA256
17mmX17mm
Populate
6O
I
CC
V
7O
I
CC
V
Pin name sequence
PL(640,1200,2280)
U2B
MachXO_fpBGA256
17mmX17mm
Populate
NC/PL2A/PL2A/PLL1T_FB
E4
NC/PL2B/PL2B/PLL1C_FB
E5
NC/PL3A/PL3A/LV_T
F5
NC/PL3B/PL3B/LV_C
F6
PL3A/PL3C/PL3C/PLL1T_IN
F3
PL3B/PL3D/PL3D/PLL1C_IN
F4
PL2C/PL4A/PL4A/LV_T
E3
PL2D/PL4B/PL4B/LV_C
E2
NC/PL4C/PL4C
C3
NC/PL4D/PL4D
C2
PL2A/PL5A/PL5A/LV_T
B1
PL2B/PL5B/PL5B/LV_C
C1
PL3C/PL5C/PL6C
D2
PL3D/PL5D/PL6D
D1
PL5A/PL6A/PL7A/LV_T
F2
PL5B/PL6B/PL7B/GSR/LV_C
G2
PL4A/PL6C/PL7C
E1
PL4B/PL6D/PL7D
F1
NC/PL7A/PL8A/LV_T
G4
NC/PL7B/PL8B/LV_C
G5
PL4C/PL7C/PL8C
G3
PL4D/PL7D/PL8D
H3
NC/PL8A/PL9A/LV_T
H4
NC/PL8B/PL9B/LV_C
H5
PL5C/PL8C/PL10C
G1
PL5D/PL8D/PL10D
H1
PL6A/PL9A/PL11A/LV_T H2
PL6B/PL9B/PL11B/LV_C J2
PL7C/PL9C/PL11C J3
PL7D/PL9D/PL11D K3
PL6C/PL10A/PL12A/LV_T J1
PL6D/PL10B/PL12B/LV_C K1
PL9A/PL10C/PL12C K2
PL9B/PL10D/PL12D L2
PL7A/PL11A/PL13A/LV_T L1
TSALL/PL8C/PL11C/PL14C N1
PL8D/PL11D/PL14D P1
PL10A/PL12A/PL15A/LV_T L3
PL10B/PL12B/PL15B/LV_C M3
PL9C/PL12C/PL15C M2
PL9D/PL12D/PL15D N2
PL8A/PL13A/PL16A/LV_T J4
PL8B/PL13B/PL16B/LV_C J5
PL11A/PL13C/PL16C R1
PL11B/PL13D/PL16D R2
NC/PL14A/PL17A/LV_T/PLL0_T_FB K5
NC/PL14B/PL17B/LV_C/PLL0_C_FB K4
PL10C/PL14C/PL17C L5
PL10D/PL14D/PL17D L4
NC/PL15A/PL18A/LV_T/PLL0_T_IN M5
NC/PL15B/PL18B/LV_C/PLL0_C_IN M4
PL11C/PL16A/PL19A N4
PL11D/PL16B/PL19B N3
PL7B/PL11B/PL13B/LV_C M1
R64
100
CR0603
NoPopulate
R64
100
CR0603
NoPopulate
16
MachXO Standard Evaluation Board
Lattice Semiconductor Revisions 001 & 002 User’s Guide
Figure 10. Power Section
A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
11
PWR_ADJ
VCC_IN
V3.3
VCC_1.2V
V3.3
PWR_3.3V
VCCIO1
VCCIO3
VCCIO[3..0]
VAUX
PWR_3.3V
PWR_1.2VDRAIN_1.2
PWR_3.3V
DRAIN_ADJ
VCCIO2
VCCIO0
VCC_ADJ
VAUX
VCC_ADJ
VCC_ADJ
VCC_1.2V
V3.3
VCC_1.2V
DRAIN_ADJ
DRAIN_1.2
VCCIO[3..0]
VAUX
VCORE
GND
GND
GND
GND
GND GND
GNDGND
GND
GND
GND
GND
GND
GND
V3.3
VCC_ADJ
VCC_1.2V
Title
Size Document Number Rev
Date: Sheet of
<Doc> 0
MachXO Evaluation Board
C
312
Title
Size Document Number Rev
Date: Sheet of
<Doc> 0
MachXO Evaluation Board
C
312
Title
Size Document Number Rev
Date: Sheet of
<Doc> 0
MachXO Evaluation Board
C
312
Another P-Channel MOSFET option in SOT23 package Another P-Channel MOSFET option in SOT23 package
On Off
3.3V On/Off Switch
C2012X5ROJ475M
Select only one voltage for each VCCIO
Output Voltage Adjust
Current sense resistors
Voltage across resistor
/ .01 = Current in Amps
4.5VDC to 28VDC
RAPC712
2.5mm Pin, (+)
5.5mm Barrel, (-)
DC-DC converter traces >= 10mil
DC-DC converter traces >= 10mil
DC-DC converter traces >= 10mil
VCCIO0
VCCIO1
VCCIO3
3.3V
ADJ
1.2V
Load only one current
sense resistor for VCC_CORE
Use 1.2V for LFXPxxE devices
Use 1.8V, 2.5V, or 3.3V for LFXPxxC devices
For 1.8V and 2.5V use VCC_ADJ
3.3V
ADJ
1.2V
3.3V
ADJ
1.2V
VCORE1.2V
V_ADJ
3.3V
JP20
HEADER 3X2
Populate
hdr_3x2_100mil
JP20
HEADER 3X2
Populate
hdr_3x2_100mil
2
4
6
1
3
5
Q3
Si5447DC
Populate
1206-8
Q3
Si5447DC
Populate
1206-8
D
1D
2D
3G
4S5
D6
D7
D8
J55
JBLOCK
Populate
J55
JBLOCK
Populate
Q4
Si5447DC
Populate
1206-8
Q4
Si5447DC
Populate
1206-8
D
1D
2D
3G
4S5
D6
D7
D8
R144
0.005
602SJ
NoPopulate
R144
0.005
602SJ
NoPopulate
C29
100uF
SizeD
Populate
C29
100uF
SizeD
Populate
12
U4
LTC1775
Populate
U4
LTC1775
Populate
SGND
6
Run/SS
3TG 13
SW 14
TK 15
EXTVcc
1
Vosence
7
Ith
5
Vprog
8
FCB
4
PGND
9
Boost 12
INTVcc 11
BG 10
Vin 16
L10
6.2uH
7mmX7mm
Populate
L10
6.2uH
7mmX7mm
Populate
1 2
JP25
CONN_RED
cn_joh_111_0701_001
Populate
JP25
CONN_RED
cn_joh_111_0701_001
Populate
S
1
R141
0.005
602SJ
NoPopulate
R141
0.005
602SJ
NoPopulate
C24
1uF
SizeA
Populate
C24
1uF
SizeA
Populate
12
C34
4.7pF
CC0402
Populate
C34
4.7pF
CC0402
Populate
JP29
CONN_RED
cn_joh_111_0701_001
Populate
JP29
CONN_RED
cn_joh_111_0701_001
Populate
S1
S5
SW SPDT
Populate
S5
SW SPDT
Populate
2
1 3
C33
4.7pF
CC0402
Populate
C33
4.7pF
CC0402
Populate
C35
470uF
SizeD
Populate
C35
470uF
SizeD
Populate
12
R147
10
CR0603
Populate
R147
10
CR0603
Populate
JP27
CONN_RED
cn_joh_111_0701_001
Populate
JP27
CONN_RED
cn_joh_111_0701_001
Populate
S
1
C31
2200pF
CC0603
Populate
C31
2200pF
CC0603
Populate
J56
JBLOCK
Populate
J56
JBLOCK
Populate
R153
10
CR0603
Populate
R153
10
CR0603
Populate
R145
0.005
602SJ
Populate
R145
0.005
602SJ
Populate
F1
3A
383milX198mil
Populate
F1
3A
383milX198mil
Populate
1 2
C26
100uF
SizeD
Populate
C26
100uF
SizeD
Populate
12
C23
0.47uF
CC0603
Populate
C23
0.47uF
CC0603
Populate
F2
3A
383milX198mil
Populate
F2
3A
383milX198mil
Populate
1 2
C27
10uF
SizeC
Populate
C27
10uF
SizeC
Populate
12
J57
JBLOCK
Populate
J57
JBLOCK
Populate
R143
0.005
602SJ
Populate
R143
0.005
602SJ
Populate
C25
1uF
SizeA
Populate
C25
1uF
SizeA
Populate
12
JP28
CONN_BLACK
cn_joh_111_0701_001
Populate
JP28
CONN_BLACK
cn_joh_111_0701_001
Populate
S1
D15
B320A
SMA
Populate
D15
B320A
SMA
Populate
R151
10K
CR0603
Populate
R151
10K
CR0603
Populate
C36
470uF
SizeD
Populate
C36
470uF
SizeD
Populate
12
R154
500K POT
5.6mmX3.6mm
Populate
R154
500K POT
5.6mmX3.6mm
Populate
1 3
2
D14
1N5819
Populate
D14
1N5819
Populate
JP22
HEADER 3X2
Populate
hdr_3x2_100mil
JP22
HEADER 3X2
Populate
hdr_3x2_100mil
2
4
6
1
3
5
JP26
CONN_RED
cn_joh_111_0701_001
Populate
JP26
CONN_RED
cn_joh_111_0701_001
Populate
S
1
Q6
Si2323DS
SOT23
NoPopulate
Q6
Si2323DS
SOT23
NoPopulate
G
D S
R150
10K
CR0603
Populate
R150
10K
CR0603
Populate
U6
TPS64203DV B
SOT23-6
Populate
U6
TPS64203DV B
SOT23-6
Populate
/EN
1
GND
2
FB
3ISENSE 4
VIN 5
SW 6
R157
10
CR0603
Populate
R157
10
CR0603
Populate
R142
0.005
602SJ
Populate
R142
0.005
602SJ
Populate
F3
3A
383milX198mil
Populate
F3
3A
383milX198mil
Populate
12
D12
MBRS340
SMC
Populate
D12
MBRS340
SMC
Populate
R148
0.005
602SJ
Populate
R148
0.005
602SJ
Populate
L8
10uH
15.24mmX18.54mm
Populate
L8
10uH
15.24mmX18.54mm
Populate
12
Q2
Si4840DY
Populate
Q2
Si4840DY
Populate
5
4
1
6
2
3
78
Q1
Si4840DY
Populate
Q1
Si4840DY
Populate
5
4
1
6
23
78
C30
4.7uF
CR0805
Populate
C30
4.7uF
CR0805
Populate
12
R156
10K
CR0402
Populate
R156
10K
CR0402
Populate
C22
100uF
SizeD
Populate
C22
100uF
SizeD
Populate
12
L9
6.2uH
7mmX7mm
Populate
L9
6.2uH
7mmX7mm
Populate
12
U5
TPS64203DVB
SOT23-6
Populate
U5
TPS64203DVB
SOT23-6
Populate
/EN
1
GND
2
FB
3ISENSE 4
VIN 5
SW 6
Q5
Si2323DS
SOT23
NoPopulate
Q5
Si2323DS
SOT23
NoPopulate
G
D S
D16
B320A
SMA
Populate
D16
B320A
SMA
Populate
C32
4.7pF
CC0402
Populate
C32
4.7pF
CC0402
Populate
D13
1N5820
267-05
Populate
D13
1N5820
267-05
Populate
C37
10uF
SizeC
Populate
C37
10uF
SizeC
Populate
12
R146
10K
CR0603
Populate
R146
10K
CR0603
Populate
R155
10K
CR0603
Populate
R155
10K
CR0603
Populate
R149
10
CR0603
Populate
R149
10
CR0603
Populate
R152
10K
CR0603
Populate
R152
10K
CR0603
Populate
C28
0.001uF
CC0603
Populate
C28
0.001uF
CC0603
Populate
JP30
PWR JACK
Populate
JP30
PWR JACK
Populate
3
2
1
JP21
HEADER 3X2
Populate
hdr_3x2_100mil
JP21
HEADER 3X2
Populate
hdr_3x2_100mil
2
4
6
1
3
5
17
MachXO Standard Evaluation Board
Lattice Semiconductor Revisions 001 & 002 User’s Guide
Figure 11. Miscellaneous Interfaces
A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
11
RJ45_IO0
RJ45_IO2
RJ45_IO4
RJ45_IO6
RJ45_IO1
RJ45_IO3
RJ45_IO5
RJ45_IO7
RJ45_IO[7..0]
PLLIN_POS
CLKIN_NEG
CLKIN_POS
PLLIN_NEG
TDI
TDO
HEADER29
HEADER17
HEADER4
HEADER3
HEADER5
HEADER25
HEADER26
HEADER6
HEADER0
HEADER13
HEADER31
HEADER15
HEADER24
HEADER2
HEADER10
HEADER9
HEADER8
HEADER14
HEADER12
HEADER22
HEADER33
HEADER21
HEADER27
HEADER16
HEADER28
HEADER1
HEADER19
HEADER32
HEADER23
HEADER7
HEADER18
HEADER30
HEADER20
HEADER11
TDI
VJTAG
TDO
TMS
TMS
TCK
RJ45_IO[7..0]
HEADER[33..0]
PLLIN_POS CKIN_POS
PLLIN_NEG CKIN_NEG
TDI_ PL D
TDO_ CL K
TDO_PLDTDI_ CLK
TMS_ CL K
TMS_PLD
GOE_PLD
GSR_n
DONE_n
PB1
TCK
GND
GND
GND
GND
GND
V3.3
V3.3
GND
GND
V3.3
V3.3
GND
V3.3
GND
V3.3
GND
Title
Size Document Number Rev
Date: Sheet of
<Doc> 0
MachXO Evaluation Board
C
412
Title
Size Document Number Rev
Date: Sheet of
<Doc> 0
MachXO Evaluation Board
C
412
Title
Size Document Number Rev
Date: Sheet of
<Doc> 0
MachXO Evaluation Board
C
412
2
3
4
8
9
10
RJ45 footprint
1
5
6
7
PLD and
ispCLK
PLD only ispCLK
only
PLD and
ispCLK
PLD only ispCLK
only
INIT_n
TRST_ n
PROGRAM_n/ispEN
DONE
RJ45_IO traces are 50 ohm
CLKIN traces are 50 ohm
PLLIN traces are 50 ohm
Mount on secondary side
Silkscreen nomenclature bounded
in yellow rectangles
JTAG Header
MachXO
RESET
Global OE
DONE
1 2 3 1 2 3
Disable Enable
MachXO
RESET
User
Switch
User
Switch
(P14)
JP11
JP16
VJTAG
TDO
TDI
TMS
GND
TCK
P (F3)
121212
121212
N (F4)
P (18)
N (19)
JP1
RJ45_CAT5
635milX840mil
NoPopulate
JP1
RJ45_CAT5
635milX840mil
NoPopulate
12
34
5 6
7 8
910
U7
Mictor debug connector
1000milX343mil
NoPopulate
U7
Mictor debug connector
1000milX343mil
NoPopulate
+5VDC
1
GND DC
3
ODD CLK
5
ODD D15
7
ODD D14
9
ODD D13
11
ODD D12
13
ODD D11
15
ODD D10
17
ODD D9
19
ODD D8
21
ODD D7
23
ODD D6
25
ODD D5
27
ODD D4
29
ODD D3
31
ODD D2
33
ODD D1
35
ODD D0
37
SCL 2
SDA 4
EVEN CLK 6
EVEN D15 8
EVEN D14 10
EVEN D13 12
EVEN D12 14
EVEN D11 16
EVEN D10 18
EVEN D9 20
EVEN D8 22
EVEN D7 24
EVEN D6 26
EVEN D5 28
EVEN D4 30
EVEN D3 32
EVEN D2 34
EVEN D1 36
EVEN D0 38
GND_0
39
GND_1
40
GND_2
41
GND_3
42
GND_4
43
M1
MOUNTING HOLE
Populate
0_125_NPTH
M1
MOUNTING HOLE
Populate
0_125_NPTH
1
JP7
HEADER 10
hdr10x1_100mil
Populate
JP7
HEADER 10
hdr10x1_100mil
Populate
1
2
3
4
5
6
7
8
9
10
JP18
HEADER 3
hdr3x1_100mil
NoPopulate
JP18
HEADER 3
hdr3x1_100mil
NoPopulate
1
2
3
R85
10K
CR0402
Populate
R85
10K
CR0402
Populate
JP2
SMA_TH
275milX275mil
NoPopulate
JP2
SMA_TH
275milX275mil
NoPopulate
1
2
3
4
5
JP3
SMA_TH
275milX275mil
NoPopulate
JP3
SMA_TH
275milX275mil
NoPopulate
1
2
3
4
5
D10
YELLOW_LED
CR0603
Populate
D10
YELLOW_LED
CR0603
Populate
JP4
SMA_TH
275milX275mil
NoPopulate
JP4
SMA_TH
275milX275mil
NoPopulate
1
2
3
4
5
R1
4.7K
CR0402
Populate
R1
4.7K
CR0402
Populate
M2
MOUNTING HOLE
Populate
0_125_NPTH
M2
MOUNTING HOLE
Populate
0_125_NPTH
1
JP5
SMA_TH
275milX275mil
NoPopulate
JP5
SMA_TH
275milX275mil
NoPopulate
1
2
3
4
5
R2
4.7K
CR0402
Populate
R2
4.7K
CR0402
Populate
C1
0.1uF
CC0402
Populate
C1
0.1uF
CC0402
Populate
D11
GREEN_LED
CR0603
Populate
D11
GREEN_LED
CR0603
Populate
R88
470
CR0402
Populate
R88
470
CR0402
Populate
S2
SW PUSHBUTTON
Populate
4.7mmx3.5mm
S2
SW PUSHBUTTON
Populate
4.7mmx3.5mm
1 4
2 3
R122
10K
CR0402
Populate
R122
10K
CR0402
Populate
JP8
HEADER 2X2
hdr_2x2_100mil
Populate
JP8
HEADER 2X2
hdr_2x2_100mil
Populate
1 2
3 4
D9
RED_LED
CR0603
Populate
D9
RED_LED
CR0603
Populate
J4
JBLOCK
Populate
J4
JBLOCK
Populate
R87
470
CR0402
Populate
R87
470
CR0402
Populate
R86
470
CR0402
Populate
R86
470
CR0402
Populate
J5
JBLOCK
Populate
J5
JBLOCK
Populate
J1
JBLOCK
Populate
J1
JBLOCK
Populate
R7
4.7K
CR0402
Populate
R7
4.7K
CR0402
Populate
J2
JBLOCK
Populate
J2
JBLOCK
Populate
M4
MOUNTING HOLE
Populate
0_125_NPTH
M4
MOUNTING HOLE
Populate
0_125_NPTH
1
J3
JBLOCK
Populate
J3
JBLOCK
Populate
S4
SW PUSHBUTTON
Populate
4.7mmx3.5mm
S4
SW PUSHBUTTON
Populate
4.7mmx3.5mm
14
2 3
R29
4.7K
CR0402
Populate
R29
4.7K
CR0402
Populate
M3
MOUNTING HOLE
Populate
0_125_NPTH
M3
MOUNTING HOLE
Populate
0_125_NPTH
1
JP6
HEADER 3X2
hdr_3x2_100mil
Populate
JP6
HEADER 3X2
hdr_3x2_100mil
Populate
2
4
6
1
3
5
18
MachXO Standard Evaluation Board
Lattice Semiconductor Revisions 001 & 002 User’s Guide
Figure 12. ispClock5610 Connections
A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
11
CLK_OUT[4..0]
CLK_OUT0
CLK_OUT1
CLK_OUT2
CLK_OUT4
CLK_OUT3
VCLK_D
VCLK_D VCLK_A
VCLK_A
VCCO_0
VCCO_1
VCCO_2
VCCO_3
VCCO_4
VCCO_0
VCCO_1
VCCO_2
VCCO_3
VCCO_4
CK_CTRL[7..0]
SGATE OEX
OEY
CK_CTRL0 CK_CTRL2
CK_CTRL3
PULLDOWN1
PULLUP1PULLUP1
PULLUP1
PULLUP1
PULLDOWN1
PULLDOWN1
PULLDOWN1
PULLDOWN1
SGATE
GOE_CLK
OEX
OEY
PLL_BYPASS
PS0 PS1
PULLUP0
CK_CTRL4
PULLDOWN0
PULLUP0
CK_CTRL5
PULLDOWN0
PULLUP0
CK_CTRL6
PULLDOWN0
PULLDOWN0
PULLUP0
PS1
PS0
PLL_BYPASS
PLL_RESET
PLL_RESETCK_CTRL7
PULLUP1
CK_CTRL1
GOE_CLK
TDO
TDI
TMS
TCK
CKIN_POS
CLK_OUT[4..0]
LOCK_n
CKIN_NEG
CK_CTRL[7..0]
GND
V3.3
V3.3
GND
V3.3
GND
GND
GND
V3.3 V3.3
GNDGND
V3.3
GND
V3.3
GND
V3.3
GND
V3.3
GND
GND
Title
Size Document Number Rev
Date: Sheet of
<Doc> 0
MachXO Evaluation Board
C
512
Title
Size Document Number Rev
Date: Sheet of
<Doc> 0
MachXO Evaluation Board
C
512
Title
Size Document Number Rev
Date: Sheet of
<Doc> 0
MachXO Evaluation Board
C
512
Zero ohm resistors
must be placed close
to pin 18 of the
ispClock_5510 device.
ispClock
RESET
Oscillator
Input
(M5)
1
5
2
Pullup Pulldown MachXO
JP1-7
(P10)
(M10)
(P7)
(P8)
(R9)
(N8)
(P9)
ispClock
PLL BYPASS
ispClock
PS0
ispClock
PS1
ispClock
OEX
ispClock
OEY
ispClock
SGATE
ispClock
GOE
Osc enable
1 2 3 1 2 3
Enable Disable
ispClock 4A
(31)
ispClock 4B
(30)
C6
0.1uF
CC0402
Populate
C6
0.1uF
CC0402
Populate
L6
FERRITE_BEAD
CR0603
Populate
L6
FERRITE_BEAD
CR0603
Populate
JP14
HEADER 3X2
hdr_3x2_100mil
Populate
JP14
HEADER 3X2
hdr_3x2_100mil
Populate
2
4
6
1
3
5
JP17
HEADER 3X2
hdr_3x2_100mil
Populate
JP17
HEADER 3X2
hdr_3x2_100mil
Populate
2
4
6
1
3
5
C11
0.1uF
CC0402
Populate
C11
0.1uF
CC0402
Populate
C12
10uF
CC0805
Populate
C12
10uF
CC0805
Populate
PROFILE SELECT
PHASE LOCK LOOP
OUTPUT DIVIDERS
OUTPUT CONTROL
AND ROUTING
U1
ispClock_5610
9mmX9mm
Populate
PROFILE SELECT
PHASE LOCK LOOP
OUTPUT DIVIDERS
OUTPUT CONTROL
AND ROUTING
U1
ispClock_5610
9mmX9mm
Populate
REFA+
18
REFA-
19
REFVTT
20
PS0
44
PS1
43
VCCO_0 1
BANK_0B 2
BANK_0A 3
GNDO_0 4
VCCO_1 5
BANK_1B 6
BANK_1A 7
GNDO_1 8
VCCO_2 9
BANK_2B 10
BANK_2A 11
GNDO_2 12
VCCO_3 25
BANK_3B 26
BANK_3A 27
GNDO_3 28
VCCO_4 29
BANK_4B 30
BANK_4A 31
GNDO_4 32
VCCA 13
GNDA
14
SGATE
40
GOE
42
OEX
21
OEY
22
LOCK 34
TDI
39
TDO
35
TMS
37
TCK
38
TEST1
46
TEST2
45
GNDD_0
23
GNDD_1
48
VCCJ
36
PLL_BYPASS
47
RESET
41
VCCD_0 24
VCCD_1 33
GNDD_2
15
GNDD_3
16
GNDD_4
17
R5
4.7K
CR0402
Populate
R5
4.7K
CR0402
Populate
JP16
HEADER 3X2
hdr_3x2_100mil
Populate
JP16
HEADER 3X2
hdr_3x2_100mil
Populate
2
4
6
1
3
5
R3
4.7K
CR0402
Populate
R3
4.7K
CR0402
Populate
S3
SW PUSHBUTTON
Populate
4.7mmx3.5mm
S3
SW PUSHBUTTON
Populate
4.7mmx3.5mm
14
2 3
C2
0.1uF
CC0402
Populate
C2
0.1uF
CC0402
Populate
L7
FERRITE_BEAD
CR0603
Populate
L7
FERRITE_BEAD
CR0603
Populate
C13
10uF
CC0805
Populate
C13
10uF
CC0805
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L5
FERRITE_BEAD
CR0603
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FERRITE_BEAD
CR0603
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C8
0.1uF
CC0402
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C8
0.1uF
CC0402
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L4
FERRITE_BEAD
CR0603
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L4
FERRITE_BEAD
CR0603
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R158
0
CR0603
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0
CR0603
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DIP16
893milX395mil
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DIP16
893milX395mil
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4
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6
7
89
10
14
16
15
13
12
11
C7
0.1uF
CC0402
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C7
0.1uF
CC0402
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R18
10K
CR0402
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R18
10K
CR0402
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L2
FERRITE_BEAD
CR0603
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L2
FERRITE_BEAD
CR0603
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R17
4.7K
CR0402
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R17
4.7K
CR0402
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TP2
TEST POINT
TP2
TEST POINT
1
R4
4.7K
CR0402
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R4
4.7K
CR0402
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C4
0.1uF
CC0402
Populate
C4
0.1uF
CC0402
Populate
R159
0
CR0603
NoPopulate
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0
CR0603
NoPopulate
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hdr_3x2_100mil
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4
6
1
3
5
L3
FERRITE_BEAD
CR0603
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FERRITE_BEAD
CR0603
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4.7K
CR0402
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R6
4.7K
CR0402
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Y1
OSC14A
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Y1
OSC14A
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EN
1
GND
7
OUT 8
VCC 14
JP9
HEADER 3
hdr3x1_100mil
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JP9
HEADER 3
hdr3x1_100mil
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1
2
3
TP3
TEST POINT
TP3
TEST POINT
1
TP1
TEST POINT
TP1
TEST POINT
1
L1
FERRITE_BEAD
CR0603
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FERRITE_BEAD
CR0603
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C9
0.1uF
CC0402
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C3
0.1uF
CC0402
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0.1uF
CC0402
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CC0805
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10uF
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CC0402
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19
MachXO Standard Evaluation Board
Lattice Semiconductor Revisions 001 & 002 User’s Guide
Figure 13. LED and LCD Connections
A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
11
LED_CL0
LED_CL1
LED_CL2
LED_CL3
LED_CL4
LED_CL5
LED_CL6
LED_CL7
LED0
LED1
LED2
LED3
LED4
LED5
LED6
LED7
LED[7..0]
SWITCHES1
SWITCHES2
SWITCHES3
SWITCHES4
SWITCHES[7..0]
SWITCHES0
SWITCHES5
SWITCHES6
SWITCHES7
LCD[38..0]
LIN35
LIN34
LIN33
LIN32
LIN27
LIN26
LIN25
LIN24
LIN19
LIN18
LIN17
LIN16
LIN10
LIN9
LIN8
LIN3
LIN36
LIN37
LIN38
LIN28
LIN20
LIN31
LIN30
LIN29
LIN11
LIN23
LIN21
LIN22
LIN12
LIN14
LIN15
LIN13
LIN5
LIN4
LIN7
LIN6LIN0
LCD7
LCD6
LCD5
LCD4
LCD15
LCD14
LCD13
LCD12
LCD11
LCD23 LCD22
LCD21
LCD20
LCD31
LCD30
LCD29
LCD28
LCD38
LCD37
LCD36
LCD0
LCD1
LCD2
LCD3
LCD8
LCD9
LCD10
LCD16
LCD17 LCD18
LCD19
LCD24
LCD25
LCD26
LCD27
LCD32
LCD33
LCD34
LCD35
LIN2
LIN1
SWITCHES[7..0]
LCD[38..0]
LED[7..0]
V3.3
GND
GND
V3.3
Title
Size Document Number Rev
Date: Sheet of
<Doc> 0
MachXO Evaluation Board
C
612
Title
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Date: Sheet of
<Doc> 0
MachXO Evaluation Board
C
612
Title
Size Document Number Rev
Date: Sheet of
<Doc> 0
MachXO Evaluation Board
C
612
D0 (R11)
D1 (R12)
D2 (P11)
D3 (P12)
D4 (T13)
D5 (T12)
D6 (R13)
D7 (R14)
(T3)
(R4)
(R5)
(P5)
(P6)
(T5)
(R6)
(G14)
(C15)
(D15)
(D16)
(E16)
(L13)
(N15)
(N14)
(E14)
(E15)
(H13)
(H12)
(G13)
(K14)
(J14)
(J15)
(M16)
(M15)
(L15)
(K15)
(L16)
(K16)
(K13)
(J13)
(H16)
(G15)
(H14)
(G12)
(G16)
(H15)
(C11)
(L14)
(M14)
(L12)
(F14)
(C16)
(F15)
(F16)
(B16)
(T4)
J38
JBLOCK
NoPopulate
J38
JBLOCK
NoPopulate
J6
JBLOCK
NoPopulate
J6
JBLOCK
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J43
JBLOCK
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JBLOCK
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GREEN_LED
CR0603
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GREEN_LED
CR0603
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470
CR0402
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470
CR0402
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JBLOCK
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JBLOCK
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JBLOCK
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JBLOCK
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JBLOCK
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JBLOCK
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JBLOCK
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CR0603
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470
CR0402
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470
CR0402
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910
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33 34
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37 38
39 40
J50
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JBLOCK
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JBLOCK
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JBLOCK
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470
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470
CR0402
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LCD_5CHAR
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LCD_5CHAR
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COM
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1G
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QE
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1D
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1C
5
2E
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2D
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2C
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3D
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3C
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DP3
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4E
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4D
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4C
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DP4
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5E
17
5D
18
5C
19
5B
20 5A 21
5F 22
5G 23
4B 24
4A 25
F4 26
4G 27
3B 28
3A 29
3F 30
3G 31
DP2 32
2B 33
2A 34
2F 35
2G 36
DP1 37
1B 38
1A 39
1F 40
D6
GREEN_LED
CR0603
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GREEN_LED
CR0603
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J21
JBLOCK
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JBLOCK
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R28
470
CR0402
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470
CR0402
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J26
JBLOCK
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JBLOCK
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J8
JBLOCK
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JBLOCK
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HEADER 20X2
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910
11 12
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19 20
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31 32
33 34
35 36
37 38
39 40
J22
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JBLOCK
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JBLOCK
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J11
JBLOCK
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CR0603
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GREEN_LED
CR0603
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JBLOCK
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JBLOCK
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J27
JBLOCK
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JBLOCK
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R35
470
CR0402
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R35
470
CR0402
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R209
10K
CR0402
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10K
CR0402
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10K
CR0402
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10K
CR0402
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J9
JBLOCK
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J9
JBLOCK
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JBLOCK
NoPopulate
J23
JBLOCK
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J28
JBLOCK
NoPopulate
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JBLOCK
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470
CR0402
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R50
470
CR0402
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J12
JBLOCK
NoPopulate
J12
JBLOCK
NoPopulate
D5
GREEN_LED
CR0603
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D5
GREEN_LED
CR0603
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J24
JBLOCK
NoPopulate
J24
JBLOCK
NoPopulate
J29
JBLOCK
NoPopulate
J29
JBLOCK
NoPopulate
J10
JBLOCK
NoPopulate
J10
JBLOCK
NoPopulate
R193
10K
CR0402
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R193
10K
CR0402
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D1
GREEN_LED
CR0603
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D1
GREEN_LED
CR0603
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J25
JBLOCK
NoPopulate
J25
JBLOCK
NoPopulate
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10K
CR0402
Populate
R181
10K
CR0402
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J30
JBLOCK
NoPopulate
J30
JBLOCK
NoPopulate
J13
JBLOCK
NoPopulate
J13
JBLOCK
NoPopulate
R33
470
CR0402
Populate
R33
470
CR0402
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J31
JBLOCK
NoPopulate
J31
JBLOCK
NoPopulate
D8
GREEN_LED
CR0603
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D8
GREEN_LED
CR0603
Populate
J36
JBLOCK
NoPopulate
J36
JBLOCK
NoPopulate
J41
JBLOCK
NoPopulate
J41
JBLOCK
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J16
JBLOCK
NoPopulate
J16
JBLOCK
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JBLOCK
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JBLOCK
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S1
SW DIP-8
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SW DIP-8
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2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
J51
JBLOCK
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J51
JBLOCK
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470
CR0402
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R39
470
CR0402
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J37
JBLOCK
NoPopulate
J37
JBLOCK
NoPopulate
D4
GREEN_LED
CR0603
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D4
GREEN_LED
CR0603
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J47
JBLOCK
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J47
JBLOCK
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J42
JBLOCK
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J42
JBLOCK
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J14
JBLOCK
NoPopulate
J14
JBLOCK
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J52
JBLOCK
NoPopulate
J52
JBLOCK
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J32
JBLOCK
NoPopulate
J32
JBLOCK
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10K
CR0402
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R199
10K
CR0402
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J48
JBLOCK
NoPopulate
J48
JBLOCK
NoPopulate
J17
JBLOCK
NoPopulate
J17
JBLOCK
NoPopulate
J53
JBLOCK
NoPopulate
J53
JBLOCK
NoPopulate
R184
10K
CR0402
Populate
R184
10K
CR0402
Populate
J33
JBLOCK
NoPopulate
J33
JBLOCK
NoPopulate
20
MachXO Standard Evaluation Board
Lattice Semiconductor Revisions 001 & 002 User’s Guide
Figure 14. Miscellaneous
A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
11
PROTO[99..0]
PROTO[99..0]
PROTO[99..0]
PROTO[99..0] PROTO[99..0]
VCCIO[3..0]
V_PU_TOP
V3.3
VCC_ADJ
VCC_1.2V
V3.3
PROTO[99..0]
VCCIO[3..0]
VCC_ADJ VCC_1.2VV3.3
Title
Size Document Number Rev
Date: Sheet of
<Doc> 0
MachXO Evaluation Board
C
712
Title
Size Document Number Rev
Date: Sheet of
<Doc> 0
MachXO Evaluation Board
C
712
Title
Size Document Number Rev
Date: Sheet of
<Doc> 0
MachXO Evaluation Board
C
712
73..59
45..0
58..46
95..74
Page 8
Page 9
Page 10
Page 11
The series resistors with a
short circuit should be placed
on the pcb with a footprint
similar to this:
TPx Rx MachXO IO
3.3V
1.2V
ADJ
3.3V
1.2V
ADJ
B8
TOP_IO S
PROTO[99..0]
V_PULLUP
V_PULLUP1
B9
LEFT_IOS
PROTO[99..0]
B10
BOTTOM_IOS
PROTO[99..0]
V_PULLUP
B11
RIGHT_IOS
PROTO[99..0]
JP19
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6
1
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JP10
HEADER 3X2
hdr_3x2_100mil
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2
4
6
1
3
5
J59
JBLOCK
J59
JBLOCK
J58
JBLOCK
J58
JBLOCK
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