Intel 8 LAN User manual

Brand: Intel

Model: 8 LAN

Category: Motherboards

Type: User manual

316234-006

Revision 2.8

Intel® I/O Controller Hub 8 LAN

NVM Map and Information Guide

January 2008

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NVM Information Guide—ICH8

Contents

1.0 Non-Volatile Memory (NVM)......................................................................................5

1.1 Introduction .......................................................................................................5

1.2 NVM Programming Procedure Overview..................................................................5

1.3 EEUPDATE Utility.................................................................................................7

1.3.1 Command Line Parameters........................................................................7

1.4 LAN NVM Format and Contents..............................................................................8

1.4.1 Ethernet Individual Address (Words 00h - 02h) ............................................9

1.4.2 Reserved (Word 03h)................................................................................9

1.4.3 Reserved (Word 04h)..............................................................................10

1.4.4 Image Version Information (Word 05h)..................................................... 10

1.4.5 Reserved (Word 06h)..............................................................................10

1.4.6 Reserved (Word 07h)..............................................................................10

1.4.7 PBA Low, PBA High (Words 08h and 09h) .................................................. 10

1.4.8 PCI Initialization Control (Word 0Ah)......................................................... 11

1.4.9 Subsystem ID (Word 0Bh)....................................................................... 11

1.4.10 Subsystem Vendor ID (Word 0Ch)............................................................11

1.4.11 Device ID (Word 0Dh)............................................................................. 12

1.4.12 Vendor ID (Word 0Eh) ............................................................................ 12

1.4.13 Device Rev ID (word 0Fh) ....................................................................... 12

1.4.14 LAN Power Consumption (Word 10h) ........................................................12

1.4.15 Shared Initialization Control (Word 13h).................................................... 13

1.4.16 Extended Configuration Word 1 (Word 14h)...............................................14

1.4.17 Extended Configuration Word 2 (Word 15h)...............................................14

1.4.18 Extended Configuration Word 3 (Word 16h)...............................................14

1.4.19 LED 1 Configuration and Power Management (Word 17h)............................. 15

1.4.20 LED 0 and 2 Configuration Defaults (Word 18h).......................................... 16

1.4.21 Future Initialization Word 1 (Words 19h) ................................................... 17

1.4.22 Future Init Word 2 (Word 1Ah)................................................................. 17

1.4.23 PXE Words (Words 30h - 3Eh)..................................................................18

1.4.24 Checksum (Word 3Fh) ............................................................................ 22

A ICH8 NVM Contents and Sample Images..................................................................23

A.1 82566DM NVM Image with ICH8 ......................................................................... 24

A.2 82566MM NVM Image with ICH8M....................................................................... 25

A.3 82566MC NVM Image with ICH8.......................................................................... 26

A.4 82562V NVM Image with ICH8............................................................................ 27

Tables

1 LAN NVM Address Map................................................................................................8

2 Ethernet Individual Address (Words 00h - 02h)..............................................................9

3 Reserved (Word 03h) .................................................................................................9

4 Reserved (Word 04h) ............................................................................................... 10

5 Image Version Information (Word 05h)...................................................................... 10

6 Reserved (Word 06h) ............................................................................................... 10

7 Reserved (Word 07h) ............................................................................................... 10

8 PCI Initialization Control Word (Word 0Ah) .................................................................. 11

9 Device IDs for Intel

Platform LAN Connects ...............................................................12

10 LAN Power Consumption (Word 10h) ..........................................................................12

11 Shared Initialization Control (Word 13h) ..................................................................... 13

12 Extended Configuration Word 1 (Word 14h)................................................................. 14

13 Extended Configuration Word 2 (Word 15h)................................................................14

ICH8—NVM Information Guide

14 Extended Configuration Word 3 (Word 16h) ................................................................14

15 LED 1 Configuration and Power Management (Word 17h)...............................................15

16 LED Modes ..............................................................................................................16

17 LED 0 and 2 Configuration Defaults (Word 18h)............................................................16

18 Boot Agent Main Setup Options ..................................................................................18

19 Boot Agent Configuration Customization Options (Word 31h)..........................................20

20 Boot Agent Configuration Customization Options (Word 32h)..........................................21

21 IBA Capabilities........................................................................................................22

22 LAN NVM Contents....................................................................................................23

Revision History

Rev Rev Date Description

2.8 Jan 2008

Updated bit descriptions for words 0Fh, 13h, 14h, 15h, 16h, 32h, and 33h.

Updated NVM images in Appendix A.

2.7 Oct 2007 Updated word 19h bit descriptions. Removed section 1.5.

2.6 April 2007 Updated Table 15 (bits 13:12 description) and Table 24 (word 0Fh).

2.5 April 2007 Removed all references to ICH9. Minor edit all sections.

2.4 Jan 2007

Updated sections 1.2, 1.4.6, 1.4.13, 1.4.14, 1.4.19, and 1.4.20.

Added sections 1.4.25.1 through 1.4.25.4 (PXE words 30h through 33h).

2.3 Jan 2007 Added ICH9 and 82567 NVM information.

2.2 Oct 2006 Added device IDs for the 82562G and 82562GT 10/100 Mb/s Platform LAN Connects.

2.1 July 2006 Changed bit 1 of word 13h to 0b.

2.0 June 2006

Initial public release.

Added new LAN Word Offset 19h description to Tables 1 and 17.

Added new EEPROM images to Appendix A.

Updated bit defaults and descriptions to Tables 9, 10, 13, 15, and 16.

1.75 April 2006 Updated bit descriptions for words 13h, 14h, and 19h.

1.5 Feb 2006

Initial Intel Confidential release.

Converted this to a stand-alone document. Previously, it was AP-478 Addendum.

Added Section 1.1, ”NVM Programming Procedure Overview,” and Section 1.2,

”EEUPDATE Utility.”

Updated the following sections:

Section 2.12, ”Shared Initialization Control (Word 13h),” bits 10 and 0

Section 2.13, ”Extended Configuration Word 1 (Word 14h),” bits 15, 14, and 11:0

Section 2.14, ”Extended Configuration Word 2 (Word 15h),” bits 15:8

Section 2.15, ”Extended Configuration Word 3 (Word 16h)”

Section 2.16, ”LED 1 Configuration and Power Management (Word 17h),” bit 7

Section 2.17, ”LED 0 and 2 Configuration Defaults (Word 18h),” bit 7

Section 2.18, ”Future Initialization Word 1 (Words 19h)”

Section 2.20, ”Checksum (Word 3Fh)”

Appendix A.1 ”82566DM NVM Image with ICH8”

Appendix A.3 ”82562V NVM Image with ICH8”

1.0 Dec 2005

Updated Section 2.12, ”Shared Initialization Control (Word 13h),” Table 9 to add the

Ext Pwr Polarity bit.

Added the 82566 NVM image to A.1 ”82566DM NVM Image with ICH8.”

0.75 July 2005 Initial release (Intel Secret).

ICH8—NVM Information Guide

1.0 Non-Volatile Memory (NVM)

1.1 Introduction

The document is intended for designs using the 10/100/1000 Mb/s LAN controller that

is integrated into the Intel

I/O Control Hub 8 (ICH8) device.

The NVM space is used for hardware and software configuration. It is also read by

software to determine and configure specific design features.

Unless otherwise specified, all numbers in this document use the following numbering

convention:

• Numbers that do not have a suffix are decimal (base 10).

• Numbers with a suffix of “h” are hexadecimal (base 16).

• Numbers with a suffix of “b” are binary (base 2).

1.2 NVM Programming Procedure Overview

The LAN NVM shares space on an SPI Flash device (or devices) along with the BIOS,

Manageability Firmware, and a Flash Descriptor Region. It is programmed through the

ICH8. This combined image is shown in Figure 1. The Flash Descriptor Region is used to

define vendor specific information and the location, allocated space, and read and write

permissions for each region. The Manageability (ME) Region contains the code and

configuration data for ME functions such as Intel

Active Management Technology, ASF,

and Advanced Fan Speed Control. The system BIOS is contained in the BIOS Region.

The ME Region and BIOS Region are beyond the scope of this document and a more

detailed explanation of these areas can be found in the Intel

I/O Controller Hub 8

(ICH8) Family External Design Specification (ICH8 EDS). This document describes the

LAN image contained in the Gigabit Ethernet (GbE) region. Fast Ethernet (82562V)

images are also described.

NVM Information Guide—ICH8

Figure 1. LAN NVM Regions

To access the NVM, it is essential to correctly setup the following:

1. A valid Flash Descriptor Region must be present. Details for the Flash Descriptor

Region are contained in the ICH8 EDS. The

FTOOL.exe utility provides the easiest

method of configuring this descriptor region. This process is described in detail in

the Intel

Active Management Technology OEM Bring-Up Guide.

FTOOL.exe and the Intel

Active Management Technology OEM Bring-Up Guide

can be obtained as part of the Intel Active Client Manager kit on ARMS

(https://platformsw.intel.com/) or by contacting your local Intel representative.

2. The GbE region must be part of the original image flashed onto the part.

3. For Intel LAN tools and drivers to work correctly, the BIOS must set the VSCC

4. The GbE region of the NVM must be accessible. To keep this region accessible, the

Protected Range register of the GbE LAN Memory Mapped Configuration registers

must be set to their default value of 0000 0000h. (The GbE Protected Range

registers are described in the ICH8 EDS).

5. If you are using the 82566, the ICH8 soft strap for the GLCI interface must be set

correctly. Bit 19 of STRP0 must be set to 1b (as described in the ICH8 EDS). For the

82562V, this bit can be set to 0b, since it does not use the GLCI bus.

Flash Descriptor

Region

GbE

Region

BIOS

Region

ICH8—NVM Information Guide

6. The sector size of the NVM must equal 256 bytes, 4 KB, or 64 KB. When a Flash

device that uses a 64 KB sector erase is used, the GbE region size must equal

128 KB. If the Flash part uses a 4 KB or 256-byte sector erase, then the GbE region

size must be set to 8 KB.

The NVM image contains both static and dynamic data. The static data is the basic

platform configuration, and includes OEM specific configuration bits as well as the

unique Printed Circuit Board Assembly (PBA). The dynamic data holds the product’s

Ethernet Individual Address (IA) and Checksum. This file can be created in a simple

text editor and follows the format shown in Appendix A, which provides examples of

GbE Region NVM maps for ICH8-based designs. Fast Ethernet (82562V) images are

also provided.

1.3 EEUPDATE Utility

Intel has created an EEUPDATE utility that can be used to update the GbE region

images during in-circuit programming. The tool uses two basic data files outlined in the

following section (static data file and IA address file). The EEUPDATE utility is flexible

and can be used to update the entire GbE region image or only the IA address of the

LAN controller. In addition, it also corrects the GbE component checksum field after the

region is modified (FTOOL does not have this ability). For more information on how to

use EEUPDATE, refer to the

eeupdate.txt file that is included with the EEUPDATE

utility.

To obtain a copy of this program, contact your Intel representative.

1.3.1 Command Line Parameters

The DOS command format is as follows:

EEUPDATE Parameter_1 Parameter_2

where:

Parameter_1 = /D or /A

/D is used to update the entire GbE region image.

/A is used to update just the Ethernet Individual Address.

Parameter_2 = filename

In Example 1, Parameter_2 is

file1.eep, which contains the complete NVM image in

a specific format used to update the complete GbE region. All comments in the

.eep

file must be preceded by a semicolon (;).

Example 1. EEUPDATE /D file1.eep

In Example 1, Parameter 2 is

file2.dat, which contains a list of IA addresses. The

EEUPDATE utility finds the first unused address from this file and uses it to update the

NVM. An address is marked used if it is followed by a date stamp. When the utility uses

a specific address, a log file called eelog.dat is updated with that address. This updated

file should be used as the

.dat file for the next update.

Appendix A provides an example of the raw GbE region contents. Fast Ethernet

(82562V) images are also provided.

NVM Information Guide—ICH8

1.4 LAN NVM Format and Contents

Table 1 lists the NVM maps for the LAN region. Each word listed is described in detail in

the following sections.

Table 1. LAN NVM Address Map

LAN

Word

Offset

NVM

Byte

Offset

HIgh Byte (Bits 15:8) Low Byte (Bits 7:0) Used By

Image

Value

00h 00

Ethernet Individual Address

Byte 2

Ethernet Individual Address

Byte 1

HW-

Shared

IA (2,1)

01h 02

Ethernet Individual Address

Byte 4

Ethernet Individual Address

Byte 3

HW-

Shared

IA (4,3)

02h 04

Ethernet Individual Address

Byte 6

Ethernet Individual Address

Byte 5

HW-

Shared

IA (6,5)

03h 06 Reserved SW 0800h

04h 08 Reserved SW FFFFh

05h 0A Image Version Information 1 SW

06h 0Ch Reserved SW FFFFh

07h 0Eh Reserved SW FFFFh

08h 10h PBA Low SW

09h 12h PBA High SW

0Ah 14h PCI Initialization Control Word HW-PCI

0Bh 16h Subsystem ID HW-PCI

0Ch 18h Subsystem Vendor ID HW-PCI

0Dh 1Ah Device ID HW-PCI

0Eh 1Ch Vendor ID HW-PCI

0Fh 1Eh Device REV ID HW-PCI

10h 20h LAN Power Consumption HW-PCI

11h 22h Reserved

12h 24h Reserved

13h 26h Shared Initialization Control Word

HW-

Shared

14h 28h Extended Configuration Word 1

HW-

Shared

15h 2Ah Extended Configuration Word 2

HW-

Shared

16h 2Ch Extended Configuration Word 3

HW-

Shared

17h 2Eh LEDCTL 1

HW-

Shared

18h 30h LEDCTL 0 2

HW-

Shared

19h 32h Future Initialization Word 1

HW-

Shared

0000h

1Ah 34h Future Initialization Word 2

HW-

Shared

0000h

ICH8—NVM Information Guide

Notes:

1. SW = Software: This is access from the network configuration tools and drivers.

2. PXE = PXE Boot Agent: This is access from the PXE Option ROM code in BIOS.

3. HW-Shared = Hardware - Shared: This is read on when the Shared Configuration is reset.

4. HW-PCI = Hardware - PCI: This is read when the PCI Configuration is reset.

1.4.1 Ethernet Individual Address (Words 00h - 02h)

The Ethernet Individual Address (IA) is a six-byte field that must be unique for each

adapter card or LOM and unique for each copy of the NVM image. The first three bytes

are vendor specific. (For example, these bytes equal 00 AA 00 or 00 A0 C9 for Intel

products.) The last three bytes must be unique for each copy of the NVM. OEM versions

of the product might be required to have non-Intel ID’s in the first three byte positions.

The value from this field is loaded into the Receive Address Register 0 (RAL0/RAH0).

The Intel default is listed in Table 2.

Note: The Ethernet IA is byte swapped, as listed in Table 2.

The IA bytes read from the NVM are used by the ICH8 until an IA Setup command is

issued by software. The IA defined by the IA Setup command overrides the IA read

from the NVM.

1.4.2 Reserved (Word 03h)

1Bh to

2Fh

32h to

5Eh

Reserved

30h to

3Eh

60h to

7Ch

PXE Software Region PXE

3Fh 7Eh Software Checksum (bytes 00h through 7Dh) SW

LAN

Word

Offset

NVM

Byte

Offset

HIgh Byte (Bits 15:8) Low Byte (Bits 7:0) Used By

Image

Value

Table 2. Ethernet Individual Address (Words 00h - 02h)

Individual Address Byte

Word 00 Word 01 Word 02

Manufacturer MAC Address

Byte

Intel (original) 00AA00XXYYZZh AAh 00h XXh 00h ZZh YYh

Intel (new) 00A0C9XXYYZZh A0h 00h XXh C9h ZZh YYh

Table 3. Reserved (Word 03h)

Bit Name Default Description

15:12 Reserved 0000b These bits are reserved and should be set to 0000b.

11 IBA LOM 1b Must be set to 1b for Intel Boot Agent (IBA) to function correctly.

10:0 Reserved 0h These bits are reserved and should be set to 0h.

NVM Information Guide—ICH8

1.4.3 Reserved (Word 04h)

1.4.4 Image Version Information (Word 05h)

1.4.5 Reserved (Word 06h)

1.4.6 Reserved (Word 07h)

1.4.7 PBA Low, PBA High (Words 08h and 09h)

The nine digit printed board assembly (PBA) number used for Intel manufactured

adapter cards are stored in a four-byte field. The dash and the first digit of the three-

digit suffix are not stored.

1.4.7.1 PBA Example

If the PBA Number is “123456-003”

then word 08h = 1234h and word 09h = 5603h.

Through the course of hardware changes, the suffix field (byte 4) is incremented. The

purpose of this information is to enable customer support (or any user) to identify the

exact revision level of a product. The software device driver should not rely on this field

to identify the product or its capabilities.

Table 4. Reserved (Word 04h)

Bit Name Default Description

15:0 Reserved FFFFh These bits are reserved and should be set to FFFFh.

Table 5. Image Version Information (Word 05h)

Bit Name Default Description

15 Reserved 0b This bit is reserved and should be set to 0b.

14:12 NVM Major Version -- This field represents the LAN NVM major version number.

11:4 NVM Minor Version -- This field represents the LAN NVM minor version number.

3:0 Image ID 2h

This field represents the NVM image identification. This field equals

2h (default) for the 82562V PHY and 0h for the 82566 PHY.

Table 6. Reserved (Word 06h)

Bit Name Default Description

15:0 Reserved FFFFh This field is reserved and should be set to FFFFh.

Table 7. Reserved (Word 07h)

Bit Name Default Description

15:0 Reserved FFFFh This field is reserved and should be set to FFFFh.

ICH8—NVM Information Guide

1.4.8 PCI Initialization Control (Word 0Ah)

This word contains initialization values that:

• Set defaults for some internal registers.

• Enable/disable specific features.

• Determine which PCI configuration space values are loaded from the NVM.

1.4.9 Subsystem ID (Word 0Bh)

If Load Subsystem IDs bit of word 0Ah is set to 1b, this word is read in to initialize the

Subsystem ID. The Subsystem ID default value is 0000h.

1.4.10 Subsystem Vendor ID (Word 0Ch)

If Load Subsystem IDs bit of word 0Ah is set to 1b, this word is read in to initialize the

Subsystem Vendor ID. The Subsystem Vendor ID default value is 8086h.

Table 8. PCI Initialization Control Word (Word 0Ah)

Bit Name Default Description

15:13 Reserved 000b This field is reserved and should be set to 000b.

12 Reserved 1b This field is reserved and should be set to 1b.

11:8 Reserved 0000b These bits are reserved and should be set to 0000b.

7AUX PWR 1b

This bit is used as an auxiliary power indication. It is used in

conjunction with the PM Enable bit.

0b = D3cold wake-up is not advertised.

1b = D3cold wake-up is advertised in the PMC register of the PCI

function if the PM Enable bit is also set.

6PM-Ena 1b

This bit enables the assertion of a PME in the PCI function at any

power state.

0b = PME functionality is disabled.

1b = PME functionality is enabled.

This bit affects the advertised PME_Support indication in the PMC

5:3 Reserved 00b This bit is reserved and should be set to 00b.

2APM Enable 1b

When APM Enable is set, both the PHY (82566 or 82562V) and

the MAC should be initialized to a functional state following power

up.

0b = APM functionality is disabled.

1b = APM functionality is enabled.

Note: This is a reserved bit for the ICH8 (B1 stepping).

1 Load Subsystem IDs 1b

0b = Device loads the default PCI Subsystem ID and Subsystem

Vendor ID.

1b = Device loads its PCIe* Subsystem ID and Subsystem Vendor

ID from the NVM (words 0Bh and 0Ch).

Load Vendor/Device

IDs

0b = Device loads the default PCI Vendor and Device IDs.

1b = Device loads the default values for PCI Vendor and Device IDs

from the NVM (words 0Dh and 0Eh).

NVM Information Guide—ICH8

1.4.11 Device ID (Word 0Dh)

If the Load Vendor/Device IDs bit in word 0Ah is set to 1b, this word is read to initialize

the Device ID of the LAN function.

1.4.12 Vendor ID (Word 0Eh)

If the Load Vendor/Device IDs bit in word 0Ah is set to 1b, this word is read to initialize

the Vendor ID. The default Vendor ID value is 8086h.

1.4.13 Device Rev ID (word 0Fh)

1.4.14 LAN Power Consumption (Word 10h)

This word is only relevant when power management is enabled.

Table 9. Device IDs for Intel

Platform LAN Connects

Device ID Adapter

1049h Intel® 82566MM Gigabit Ethernet Controller

104Ah Intel® 82566DM Gigabit Ethernet Controller

104Dh Intel® 82566MC Gigabit Ethernet Controller

104Ch Intel® 82562V 10/100 Mb/s Platform LAN Connect Device

Bit Name Default Description

15:0 Reserved 00h Reserved

Table 10. LAN Power Consumption (Word 10h)

Bit Name Default Description

15:8

LAN D0

Power

0Dh for 82566

04h for 82562V

The value in this field is reflected in the PCI Power Management

Data Register of the LAN function for D0 power consumption and

dissipation (Data_Select = 0 or 4). Power is defined in 100 mW

units and includes the external logic required for the LAN function.

7:5 Reserved 000b These bits are reserved and should be set to 000b.

4:0

LAN D3

Power

00001b for 82566

00010b for 82562V

The value in this field is reflected in the PCI Power Management

Data Register of the LAN function for D3 power consumption and

dissipation (Data_Select = 3 or 7). Power is defined in 100 mW

units and includes the external logic required for the LAN function.

The most significant bits in the Data Register that reflects the

power values are padded with zeros.

ICH8—NVM Information Guide

1.4.15 Shared Initialization Control (Word 13h)

This word controls general initialization values.

Table 11. Shared Initialization Control (Word 13h)

Bit Name Default Description

15:14 SIGN 10b

Valid Indication

This is a 2-bit field indicating whether a valid NVM is present to the

MAC. If this field does not equal 10b, the MAC does not read the

NVM data and uses default values for device configuration.

00b = Invalid NVM.

01b = Invalid NVM.

10b = Valid NVM present.

11b = Invalid NVM.

13:11 Reserved 010b These bits are reserved and should be set to 010b.

10 Reserved 1b Reserved. Always set to 1b.

9PHY PD Ena 1b

For ICH8 designs that support an ACBS implementation using LAN

Power Control (LAN_PHYPC), this bit enables or disables PHY power

down.

0b = PHY power down feature is disabled.

1b = PHY power down feature is enabled to power down at DMoff/

D3 without Wake on LAN.

This bit is loaded to the PHY Power Down Enable bit in the

CTRL_EXT register.

8 Reserved 0b This bit is reserved and should be set to 0b.

7:6 PHYT 00b

This field indicates the PHY device type.

00b = 82566 PHY - GLCI mode

01b = Reserved

10b = 82562V PHY - PCIe mode, LCI mode

11b = Reserved

This field is reflected in the PHYTYPE field in the Status register.

5 Reserved 0b Reserved. Must be set to 0b.

4FRCSPD 0b

Force Speed Enable

0b = Normal operation.

1b = Use ICH8 speed.

3FD 0b

Force Duplex

0b = Normal operation.

1b = Use ICH8 speed.

2 CLK_CNT_1_16 1b

This bit is loaded to the CTRL_EXT.EnaKumCK16 bit and enables

the reduction of the internal JCLK to one-sixteenth of the external

NJCLK at the GLCI interface in Gigabit Ethernet mode.

0b = Reduction is disabled.

1b = Reduction is enabled.

1 CLK_CNT_1_4 0b

This bit enables the automatic reduction of DMA frequency. It is

mapped to STATUS[31].

0b = Automatic reduction disabled.

1b = Automatic reduction enabled.

Dynamic Clock

Gating

Dynamic Clock Gating

0b = Disable.

1b = Enable.

NVM Information Guide—ICH8

1.4.16 Extended Configuration Word 1 (Word 14h)

1.4.17 Extended Configuration Word 2 (Word 15h)

1.4.18 Extended Configuration Word 3 (Word 16h)

Table 12. Extended Configuration Word 1 (Word 14h)

Bit Name Default Description

15 Reserved 0b Reserved. Must be set to 0b.

14 Reserved 1b

1b = ICH8 (B0/B1 stepping).

0b = ICH8 (A0 stepping).

13 Reserved 1b Set this field to 0b.

12 OEM Write Enable 1b

OEM Write Enable

0b = Disable.

1b = Enable.

Set this field to 0b.

11:0

Extended

Configuration

Pointer

020h

This field defines the base address (in Dwords) of the extended

configuration area in the NVM. It should equal a non-zero value.

Table 13. Extended Configuration Word 2 (Word 15h)

Bit Name Default Description

15:8

Extended PHY

Length

37h

This field identifies the size (in Dwords) of the extended PHY

configuration area.

For the 82566 PHY, if the extended PHY configuration area is

disabled, the length must be set to 37h.

7:0 Reserved 00h These bits are reserved and should be set to 00h.

Table 14. Extended Configuration Word 3 (Word 16h)

Bit Name Default Description

15:0 Reserved 00h These bits are reserved and should be set to 00h.

ICH8—NVM Information Guide

1.4.19 LED 1 Configuration and Power Management (Word 17h)

This field specifies the default values for the LEDCTL register fields controlling the LED1

(LINK_1000) output behaviors and the OEM fields defining the PHY power management

parameters loaded to the PHY_CTRL register.

The following table lists the LED modes defined in bits 3:0 of this word.

Table 15. LED 1 Configuration and Power Management (Word 17h)

Bit Name Default Description

15 B2B Enable 1b

This bit enables Smart Power Down in back-to-back link setup.

0b = B2B disabled.

1b = B2B enabled.

14 GbE Disable 0b

GbE Disable (in all power states)

0b = GbE enabled.

1b = GbE disabled.

13:12 Reserved 00b These bits are reserved and should be set to 00b.

GbE Disable in non-

D0a

GbE Disable (in all power states except D0a)

0b = GbE enabled.

1b = GbE disabled.

LPLU Enable in non-

D0a

The Low Power Link Up enables link at the lowest speed supported

by both link partners in non-D0a states. This bit must be set if

LPLU Enable bit is set.

0b = Low Power Link Up is disabled.

1b = Low Power Link Up is enabled in all non-D0a states.

9LPLU Enable 0b

The Low Power Link Up enables link at the lowest speed supported

by both link partners in all power states. This bit enables a

decrease in link speed in all power states.

0b = Low Power Link Up is disabled.

1b = Low Power Link Up is enabled in all power states.

8SPD Enable 1b

0b = PHY Smart Power Down mode is disabled.

1b = PHY Smart Power Down mode is enabled.

7 LED1 Blink 0b

This bit indicates the initial value of the LED1_BLINK field.

0b = LED1 is non-blinking (recommended).

1b = LED1 is blinking.

6 LED1 Invert 0b

This bit indicates the initial value of the LED1_IVRT field.

0b = LED1 has an active low output.

1b = LED1 has an active high output.

5 LED1 Blink Mode 0b

This bit defines the LED1 blink mode:

0b = Blink at 200 ms on and 200 ms off.

1b = Blink at 83 ms on and 83 ms off.

This field should be identical to LED0 Blink Mode.

4Filtered ACT LED0b

Enable Filtered Activity LED (while operating with the 82562V)

When set to 0b, the activity LED is activated by the PHY.

When set to 1b, the activity LED is driven by Tx activity or Rx

traffic that match any of the MAC's MAC addresses.

For the 82566, this bit is reserved and should be set to 0b.

3:0 LED1 Mode 0111b

These bits represent the initial value of the LED1_MODE field,

which specifies the event, state, or pattern displayed on LED1

(LINK_1000) output. Table 16 defines the values for LED1 Mode.

A value of 0111b indicates that a 1000 Mb/s link is established and

maintained.

NVM Information Guide—ICH8

1.4.20 LED 0 and 2 Configuration Defaults (Word 18h)

This NVM word specifies the hardware defaults for the LEDCTL register fields controlling

the LED0 (LINK/ACTIVITY) and LED2 (LINK_100) output behaviors.

Table 16. LED Modes

Mode (Bits

3:0)

Selected Mode Source Indication

0000b LINK_10/1000

Asserted when either 10 Mb/s or 1000 Mb/s link is established

and maintained.

0001b LINK_100/1000

Asserted when either 100 Mb/s or 1000 Mb/s link is

established and maintained.

0010b LINK-UP Asserted when any speed link is established and maintained.

0011b FILTER_ACTIVITY

Asserted when link is established and packets are being

transmitted or received that passed MAC filtering.

0100b LINK/ACTIVITY

Asserted when link is established and when there is no

transmit or receive activity.

0101b LINK_10 Asserted when a 10 Mb/s link is established and maintained.

0110b LINK_100 Asserted when a 100 Mb/s link is established and maintained.

0111b LINK_1000 Asserted when a 1000 Mb/s link is established and maintained.

1000b Reserved Reserved.

1001b FULL_DUPLEX Asserted when the link is configured for full duplex operation.

1010b COLLISION Asserted when a collision is observed.

1011b ACTIVITY

Asserted when link is established and packets are being

transmitted or received.

1100b BUS_SIZE Asserted when the MAC detects a 1-lane PCIe* connection.

1101b PAUSED Asserted when the MAC transmitter is flow controlled.

1110b LED_ON Always asserted.

1111b LED_OFF Always de-asserted.

Table 17. LED 0 and 2 Configuration Defaults (Word 18h)

Bit Name Default Description

15 LED2 Blink 0b

This bit indicates the initial value of the LED2_BLINK field.

0b = LED2 is non-blinking.

1b = LED2 is blinking.

14 LED2 Invert 0b

This bit indicates the initial value of the LED2_IVRT field.

0b = LED2 has an active low output.

1b = LED2 has an active high output.

13 LED2 Blink Mode 0b

This bit defines the LED2 blink mode:

0b = Blink at 200 ms on and 200 ms off.

1b = Blink at 83 ms on and 83 ms off.

Note: This field should be identical to the LED0 Blink Mode.

12 Reserved 0b This bit is reserved and should be set to 0b.

11:8 LED2 Mode 0110b

These bits represent the initial value of the LED2_MODE field,

which specifies the event, state, or pattern displayed on LED2

(LINK_100) output. A value of 0110b causes this to indicate

100 Mb/s operation.

ICH8—NVM Information Guide

Table 16, “LED Modes” above summarizes the LED modes defined in bits 3:0 of this

word.

1.4.21 Future Initialization Word 1 (Words 19h)

1.4.22 Future Init Word 2 (Word 1Ah)

Bit Name Default Description

7 LED0 Blink 1b

This bit indicates the initial value of the LED0_BLINK field.

0b = LED0 is non-blinking (recommended).

1b = LED0 is blinking.

6 LED0 Invert 0b

This bit indicates the initial value of the LED0_IVRT field.

0b = LED0 has an active low output.

1b = LED0 has an active high output.

5 LED0 Blink Mode 0b

This bit define the LED0 blink mode:

0b = Blink at 200 ms on and 200 ms off.

1b = Blink at 83 ms on and 83 ms off.

Note: This field initializes the GLOBAL_BLINK_MODE field in the

LEDCTL register.

4 Reserved 0b This bit is reserved and should be set to 0b.

3:0 LED0 Mode 0100b

These bits represent the initial value of the LED0_MODE field,

which specifies the event, state, or pattern displayed on LED0

(Link/Activity) output. Table 16 defines the values for LED0 Mode.

Table 17. LED 0 and 2 Configuration Defaults (Word 18h)

Bit Name Default Description

15:0 Reserved X

This field is loaded to bits 15:0 of the FEXTNVM register.

For the 82562V, must be set to 301h.

For 82566 SKUs that include ACBS, must be set to 181h.

For 82566 SKUs without ACBS, must be set to 301h.

Bit Name Default Description

15:0 Reserved X

Reserved

This field is loaded to bits 15:0 of the FEXTNVM register.

For ICH8, set these bits to 0800h.

For ICH8M:

All 82566 SKUs that include ACBS, must be set to 0803h.

All 82566 SKUs without ACBS, must be set to 2803h.

NVM Information Guide—ICH8

1.4.23 PXE Words (Words 30h - 3Eh)

Words 30h through 3Eh (bytes 60h through 7Dh) have been reserved for configuration

and version values to be used by PXE code.

1.4.23.1 Boot Agent Main Setup Options (Word 30h)

The boot agent software configuration is controlled by the NVM with the main setup

options stored in word 30h. These options are those that can be changed by using the

Control-S setup menu or by using the IBA Intel Boot Agent utility. Note that these

settings only apply to Boot Agent software.

Table 18. Boot Agent Main Setup Options

Bit Name Description

15 PPB

PXE Presence.

Setting this bit to 0b Indicates that the image in the Flash contains a

PXE image.

Setting this bit to 1b indicates that no PXE image is contained.

The default for this bit is 0b for backwards compatibility with existing

systems already in the field.

If this bit is set to 0b, EEPROM word 32h (PXE Version) is valid. When

EPB is set to 1b and this bit is set to 0b, indicates that both images are

present in the Flash.

14 EPB

EFI Presence.

Setting this bit to 1b Indicates that the image in the Flash contains an

EFI image.

Setting this bit to 0b indicates that no EFI image is contained.

The default for this bit is 0b for backwards compatibility with existing

systems already in the field.

If this bit is set to 1b, EEPROM word 33h (EFI Version) is valid. When

PPB is set to 0b and this bit is set to 1b, indicates that both images

(PXE and EFI) are present in the Flash.

13 Reserved Reserved for future use. This bit must be set to 0b.

12 FDP

Force Full Duplex.

Set this bit to 0b for half duplex and 1b for full duplex.

Note that this bit is a don’t care unless bits 10 and 11 are set.

11:10 FSP

Force Speed.

These bits determine speed.

01b = 10 Mb/s

10b = 100 Mb/s

11b = Not allowed.

All zeros indicate auto-negotiate (the current bit state).

Note that bit 12 is a don’t care unless these bits are set.

9 Reserved

Reserved

Set this bit to 0b.

8DSM

Display Setup Message.

If this bit is set to 1b, the "Press Control-S" message appears after the

title message.

The default for this bit is 1b.

ICH8—NVM Information Guide

1.4.23.2 Boot Agent Configuration Customization Options (Word 31h)

Word 31h contains settings that can be programmed by an OEM or network

administrator to customize the operation of the software. These settings cannot be

changed from within the Control-S setup menu or the IBA Intel Boot Agent utility. The

lower byte contains settings that would typically be configured by a network

administrator using the Intel Boot Agent utility; these settings generally control which

setup menu options are changeable. The upper byte are generally settings that would

be used by an OEM to control the operation of the agent in a LOM environment,

although there is nothing in the agent to prevent their use on a NIC implementation.

7:6 PT

Prompt Time. These bits control how long the "Press Control-S" setup

prompt message appears, if enabled by DIM.

00b = 2 seconds (default)

01b = 3 seconds

10b = 5 seconds

11b = 0 seconds

Note that the Ctrl-S message does not appear if 0 seconds prompt time

is selected.

5 Reserved Reserved

4:3 DBS

Default Boot Selection. These bits select which device is the default

boot device. These bits are only used if the agent detects that the BIOS

does not support boot order selection or if the MODE field of word 31h

is set to MODE_LEGACY.

00b = Network boot, then local boot

01b = Local boot, then network boot

10b = Network boot only

11b = Local boot only

2 Reserved Reserved

1:0 PS

Protocol Select. These bits select the boot protocol.

00b = PXE (default value)

01b = RPL protocol

Other values are undefined.

Bit Name Description

NVM Information Guide—ICH8

Table 19. Boot Agent Configuration Customization Options (Word 31h)

Bit Name Description

15:14 SIG

Signature. These bits must be set to 01b to indicate that this word has

been programmed by the agent or other configuration software.

13:11 Reserved Reserved for future use. All bits must be set to 0b.

10:8 MODE

Selects the agent's boot order setup mode. This field changes the

agent's default behavior in order to make it compatible with systems

that do not completely support the BBS and PnP Expansion ROM

standards. Valid values and their meanings are:

000b = Normal behavior. The agent attempts to detect BBS and PnP

Expansion ROM support as it normally does.

001b = Force Legacy mode. The agent does not attempt to detect BBS

or PnP Expansion ROM supports in the BIOS and assumes the BIOS is

not compliant. The BIOS boot order can be changed in the Setup Menu.

010b = Force BBS mode. The agent assumes the BIOS is BBS-

compliant, even though it may not be detected as such by the agent's

detection code. The BIOS boot order CANNOT be changed in the Setup

Menu.

011b = Force PnP Int18 mode. The agent assumes the BIOS allows

boot order setup for PnP Expansion ROMs and hooks interrupt 18h (to

inform the BIOS that the agent is a bootable device) in addition to

registering as a BBS IPL device. The BIOS boot order CANNOT be

changed in the Setup Menu.

100b = Force PnP Int19 mode. The agent assumes the BIOS allows

boot order setup for PnP Expansion ROMs and hooks interrupt 19h (to

inform the BIOS that the agent is a bootable device) in addition to

registering as a BBS IPL device. The BIOS boot order CANNOT be

changed in the Setup Menu.

101b = Reserved for future use. If specified, treated as value 000b.

110b = Reserved for future use. If specified, treated as value 000b.

111b = Reserved for future use. If specified, treated as value 000b.

7:6 Reserved Reserved for future use. These bits must be set to 0b.

5DFU

Disable Flash Update.

If set to 1b, no updates to the Flash image using PROSet is allowed.

The default for this bit is 0b; allow Flash image updates using PROSet.

4DLWS

Disable Legacy Wakeup Support.

If set to 1b, no changes to the Legacy OS Wakeup Support menu

option is allowed.

The default for this bit is 0b; allow Legacy OS Wakeup Support menu

option changes.

3DBS

Disable Boot Selection.

If set to 1b, no changes to the boot order menu option is allowed.

The default for this bit is 0b; allow boot order menu option changes.

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